ARM: tegra20: cpuidle: add power-down state

The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes.

For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI.

Quoted 9 lines · Joseph Lo

The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes.

Quoted 5 lines

For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI.

Is this feature something that can/should be added to the core GIC driver, rather than something custom in the Tegra code?

Part of the reason I ask is that I'd like to avoid any more:

static void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);

since that requires static page tables to be set up, whereas I'd like to reduce, as much as possible, the set of pages Tegra maps statically.

Quoted 10 lines · Stephen Warren

Quoted 9 lines · Joseph Lo

The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes.

Quoted 9 lines

Quoted 5 lines

For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI.

Is this feature something that can/should be added to the core GIC driver, rather than something custom in the Tegra code?

This function is SoC specific code not a generic common code even I modify it to more generic for checking the pending irq (SGI, PPI and SPI). Different SoC had different design about it. For ex, some SoC only put CPU core to power saving mode not include GIC, or there is another irq controller can handle the case when CPU go into power saving mode. Differenc SoC had different usage here (some need to check all pending irq, some need to check SGI only and some even no need to consider this).

Quoted 6 lines

Part of the reason I ask is that I'd like to avoid any more:

static void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);

since that requires static page tables to be set up, whereas I'd like to reduce, as much as possible, the set of pages Tegra maps statically.

I can move this into the function as a temp variable.

The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <[email protected]>
Gary King <[email protected]>

Signed-off-by Joseph Lo <[email protected]>

---
V2:
* no change

---
 arch/arm/mach-tegra/cpuidle-tegra20.c |   84 +++++++++++++++++++
 arch/arm/mach-tegra/pm.c              |    2 +
 arch/arm/mach-tegra/sleep-tegra20.S   |  145 +++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.h           |   23 +++++
 4 files changed, 254 insertions(+), 0 deletions(-)

arch/arm/mach-tegra/cpuidle-tegra20.c +14 -0

index d32e8b0..9d59a46 100644
@@ -22,21 +22,105 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/clockchips.h>
 
 #include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/smp_plat.h>
+
+#include "pm.h"
+#include "sleep.h"
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra20_idle_lp2(struct cpuidle_device *dev,
+                           struct cpuidle_driver *drv,
+                           int index);
+#endif

arch/arm/mach-tegra/cpuidle-tegra20.c +11 -0

        .states = {
                [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+#ifdef CONFIG_PM_SLEEP
+               [1] = {
+                       .enter                  = tegra20_idle_lp2,
+                       .exit_latency           = 5000,
+                       .target_residency       = 10000,
+                       .power_usage            = 0,
+                       .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                       .name                   = "powered-down",
+                       .desc                   = "CPU power gated",
+               },
+#endif
        },
 };
 
 static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);

arch/arm/mach-tegra/cpuidle-tegra20.c +46 -0

+
+       cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
+
+       tegra20_cpu_clear_resettable();
+
+       clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+       return true;
+}
+#else
+static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
+                                               struct cpuidle_driver *drv,
+                                               int index)
+{
+       return true;
+}
+#endif
+
+static int __cpuinit tegra20_idle_lp2(struct cpuidle_device *dev,
+                                     struct cpuidle_driver *drv,
+                                     int index)
+{
+       u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
+       bool entered_lp2 = false;
+
+       local_fiq_disable();
+
+       tegra_set_cpu_in_lp2(cpu);
+       cpu_pm_enter();
+
+       if (cpu == 0)
+               cpu_do_idle();
+       else
+               entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
+
+       cpu_pm_exit();
+       tegra_clear_cpu_in_lp2(cpu);
+
+       local_fiq_enable();
+
+       smp_rmb();
+
+       return (entered_lp2) ? index : 0;
+}
+#endif
+
 int __init tegra20_cpuidle_init(void)
 {
        int ret;

arch/arm/mach-tegra/pm.c +2 -0

index 1b11707..db72ea9 100644
@@ -173,6 +173,8 @@ bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)
 
        if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
                last_cpu = true;
+       else if (phy_cpu_id == 1)
+               tegra20_cpu_set_resettable_soon();
 
        spin_unlock(&tegra_lp2_lock);
        return last_cpu;

arch/arm/mach-tegra/sleep-tegra20.S +47 -0

index 72ce709..dfb2be5 100644
@@ -21,6 +21,8 @@
 #include <linux/linkage.h>
 
 #include <asm/assembler.h>
+#include <asm/proc-fns.h>
+#include <asm/cp15.h>
 
 #include "sleep.h"
 #include "flowctrl.h"

@@ -78,3 +80,146 @@ ENTRY(tegra20_cpu_shutdown)
        mov     pc, lr
 ENDPROC(tegra20_cpu_shutdown)
 #endif
+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]
+ * on cpu1:
+ * SCRATCH39 = r2 = flag[1]
+ * SCRATCH38 = r3 = flag[0]
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       add     r1, r3, #PMC_SCRATCH37
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addeq   r3, r3, #PMC_SCRATCH39
+       addne   r2, r3, #PMC_SCRATCH39
+       addne   r3, r3, #PMC_SCRATCH38
+
+       mov     r12, #1
+       str     r12, [r2]               @ flag[cpu] = 1
+       dsb
+       str     r12, [r1]               @ !turn = cpu
+1:     dsb
+       ldr     r12, [r3]
+       cmp     r12, #1                 @ flag[!cpu] == 1?
+       ldreq   r12, [r1]
+       cmpeq   r12, r0                 @ !turn == cpu?
+       beq     1b                      @ while !turn == cpu && flag[!cpu] == 1
+
+       mov     pc, lr                  @ locked
+ENDPROC(tegra_pen_lock)
+
+ENTRY(tegra_pen_unlock)

arch/arm/mach-tegra/sleep-tegra20.S +75 -0

+
+/*
+ * tegra20_cpu_clear_resettable(void)
+ *
+ * Called to clear the "resettable soon" flag in PMC_SCRATCH41 when
+ * it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra20_cpu_clear_resettable)
+       mov32   r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+       mov     r12, #CPU_NOT_RESETTABLE
+       str     r12, [r1]
+       mov     pc, lr
+ENDPROC(tegra20_cpu_clear_resettable)
+
+/*
+ * tegra20_cpu_set_resettable_soon(void)
+ *
+ * Called to set the "resettable soon" flag in PMC_SCRATCH41 when
+ * it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra20_cpu_set_resettable_soon)
+       mov32   r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+       mov     r12, #CPU_RESETTABLE_SOON
+       str     r12, [r1]
+       mov     pc, lr
+ENDPROC(tegra20_cpu_set_resettable_soon)
+
+/*
+ * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
+ *
+ * Enters WFI on secondary CPU by exiting coherency.
+ */
+ENTRY(tegra20_sleep_cpu_secondary_finish)
+       mrc     p15, 0, r11, c1, c0, 1  @ save actlr before exiting coherency
+
+       /* Flush and disable the L1 data cache */
+       bl      tegra_disable_clean_inv_dcache
+
+       mov32   r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
+       mov     r3, #CPU_RESETTABLE
+       str     r3, [r0]
+
+       bl      cpu_do_idle
+
+       /*
+        * cpu may be reset while in wfi, which will return through
+        * tegra_resume to cpu_resume
+        * or interrupt may wake wfi, which will return here
+        * cpu state is unchanged - MMU is on, cache is on, coherency
+        * is off, and the data cache is off
+        *
+        * r11 contains the original actlr
+        */
+
+       bl      tegra_pen_lock
+
+       mov32   r3, TEGRA_PMC_VIRT
+       add     r0, r3, #PMC_SCRATCH41
+       mov     r3, #CPU_NOT_RESETTABLE
+       str     r3, [r0]
+
+       bl      tegra_pen_unlock
+
+       /* Re-enable the data cache */
+       mrc     p15, 0, r10, c1, c0, 0
+       orr     r10, r10, #CR_C
+       mcr     p15, 0, r10, c1, c0, 0
+       isb
+
+       mcr     p15, 0, r11, c1, c0, 1  @ reenable coherency
+
+       /* Invalidate the TLBs & BTAC */
+       mov     r1, #0
+       mcr     p15, 0, r1, c8, c3, 0   @ invalidate shared TLBs
+       mcr     p15, 0, r1, c7, c1, 6   @ invalidate shared BTAC

arch/arm/mach-tegra/cpuidle-tegra20.c line 50

Quoted 9 lines · Joseph Lo

 static struct cpuidle_driver tegra_idle_driver = {
        .name = "tegra_idle",
        .owner = THIS_MODULE,
        .en_core_tk_irqen = 1,

arch/arm/mach-tegra/cpuidle-tegra20.c +4 -0

+#ifdef CONFIG_PM_SLEEP
+       .state_count = 2,
+#else
        .state_count = 1,
+#endif

These hardcoded values are not nice.

Quoted 18 lines

        .states = {
                [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),

arch/arm/mach-tegra/cpuidle-tegra20.c +11 -0

+#ifdef CONFIG_PM_SLEEP
+               [1] = {
+                       .enter                  = tegra20_idle_lp2,
+                       .exit_latency           = 5000,
+                       .target_residency       = 10000,
+                       .power_usage            = 0,
+                       .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                       .name                   = "powered-down",
+                       .desc                   = "CPU power gated",
+               },
+#endif
        },
 };
 
 static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);

arch/arm/mach-tegra/cpuidle-tegra20.c line 77

Quoted 9 lines

arch/arm/mach-tegra/cpuidle-tegra20.c +9 -0

+#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_SMP
+static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
+                                        struct cpuidle_driver *drv,
+                                        int index)
+{
+       clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+
+       smp_wmb();

Can you explain to me the need for this barrier ?

Quoted 59 lines

arch/arm/mach-tegra/sleep-tegra20.S +59 -0

+
+       cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
+
+       tegra20_cpu_clear_resettable();
+
+       clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+       return true;
+}
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]
+ * on cpu1:
+ * SCRATCH39 = r2 = flag[1]
+ * SCRATCH38 = r3 = flag[0]
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       add     r1, r3, #PMC_SCRATCH37
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addeq   r3, r3, #PMC_SCRATCH39
+       addne   r2, r3, #PMC_SCRATCH39
+       addne   r3, r3, #PMC_SCRATCH38
+
+       mov     r12, #1
+       str     r12, [r2]               @ flag[cpu] = 1
+       dsb
+       str     r12, [r1]               @ !turn = cpu
+1:     dsb
+       ldr     r12, [r3]
+       cmp     r12, #1                 @ flag[!cpu] == 1?
+       ldreq   r12, [r1]
+       cmpeq   r12, r0                 @ !turn == cpu?
+       beq     1b                      @ while !turn == cpu && flag[!cpu] == 1
+
+       mov     pc, lr                  @ locked
+ENDPROC(tegra_pen_lock)
+
+ENTRY(tegra_pen_unlock)
+       dsb
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addne   r2, r3, #PMC_SCRATCH39

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 137

Quoted 4 lines

arch/arm/mach-tegra/sleep-tegra20.S +4 -0

+       mov     r12, #0
+       str     r12, [r2]
+       mov     pc, lr
+ENDPROC(tegra_pen_unlock)

There is an ongoing work to make this locking scheme for MMU/coherency off paths ARM generic, and we do not want to merge yet another platform specific locking mechanism. I will point you to the patchset when it hits LAK.

Quoted 48 lines

arch/arm/mach-tegra/sleep-tegra20.S +48 -0

+/*
+ * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
+ *
+ * Enters WFI on secondary CPU by exiting coherency.
+ */
+ENTRY(tegra20_sleep_cpu_secondary_finish)
+       mrc     p15, 0, r11, c1, c0, 1  @ save actlr before exiting coherency
+
+       /* Flush and disable the L1 data cache */
+       bl      tegra_disable_clean_inv_dcache
+
+       mov32   r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
+       mov     r3, #CPU_RESETTABLE
+       str     r3, [r0]
+
+       bl      cpu_do_idle
+
+       /*
+        * cpu may be reset while in wfi, which will return through
+        * tegra_resume to cpu_resume
+        * or interrupt may wake wfi, which will return here
+        * cpu state is unchanged - MMU is on, cache is on, coherency
+        * is off, and the data cache is off
+        *
+        * r11 contains the original actlr
+        */
+
+       bl      tegra_pen_lock
+
+       mov32   r3, TEGRA_PMC_VIRT
+       add     r0, r3, #PMC_SCRATCH41
+       mov     r3, #CPU_NOT_RESETTABLE
+       str     r3, [r0]
+
+       bl      tegra_pen_unlock
+
+       /* Re-enable the data cache */
+       mrc     p15, 0, r10, c1, c0, 0
+       orr     r10, r10, #CR_C
+       mcr     p15, 0, r10, c1, c0, 0
+       isb
+
+       mcr     p15, 0, r11, c1, c0, 1  @ reenable coherency
+
+       /* Invalidate the TLBs & BTAC */
+       mov     r1, #0
+       mcr     p15, 0, r1, c8, c3, 0   @ invalidate shared TLBs
+       mcr     p15, 0, r1, c7, c1, 6   @ invalidate shared BTAC

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 222

Quoted 10 lines

arch/arm/mach-tegra/sleep-tegra20.S +10 -0

+       dsb
+       isb
+
+       /* the cpu was running with coherency disabled,
+        * caches may be out of date */
+       bl      v7_flush_kern_cache_louis
+
+       ldmia   sp!, {r1 - r3}          @ pop phys pgd, virt SP, phys resume fn
+       mov     r0, #0                  @ return success
+       mov     sp, r2                  @ sp is stored in r2 by __cpu_suspend

This is not true. sp is retrieved from the r2 value popped above. Anyway, all this code is a copy'n'paste from __cpu_suspend. Now if I got what you want to do right, all you want to do is return to cpu_suspend with r0 == 0.

(1) You should not rely on the register layout of __cpu_suspend since if it changes we have to patch this code as well. Do not rely on that.
(2) Why do you want to return with r0 == 0 ? To me that's a mistery. Is that because you want cpu_suspend to restore the page table pointer ? Even in that case I am afraid I am against this code. Usage of cpu_suspend must be consistent and you *must* not use it as a plaster or rely on any specific register layout, it has to be used for the purpose it has been designed for.

Quoted 13 lines · Lorenzo Pieralisi

arch/arm/mach-tegra/cpuidle-tegra20.c line 50

Quoted 9 lines · Joseph Lo

 static struct cpuidle_driver tegra_idle_driver = {
        .name = "tegra_idle",
        .owner = THIS_MODULE,
        .en_core_tk_irqen = 1,

arch/arm/mach-tegra/cpuidle-tegra20.c +4 -0

+#ifdef CONFIG_PM_SLEEP
+       .state_count = 2,
+#else
        .state_count = 1,
+#endif

These hardcoded values are not nice.

OK. I will change it to runtime detection when idle driver registration.

Quoted 15 lines

Quoted 15 lines

        .states = {
                [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),

arch/arm/mach-tegra/cpuidle-tegra20.c +11 -0

+#ifdef CONFIG_PM_SLEEP
+               [1] = {
+                       .enter                  = tegra20_idle_lp2,
+                       .exit_latency           = 5000,
+                       .target_residency       = 10000,
+                       .power_usage            = 0,
+                       .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                       .name                   = "powered-down",
+                       .desc                   = "CPU power gated",
+               },
+#endif
        },
 };

Quoted 67 lines · Joseph Lo

The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <[email protected]>
Gary King <[email protected]>

Signed-off-by Joseph Lo <[email protected]>

arch/arm/mach-tegra/sleep-tegra20.S +51 -0

+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]
+ * on cpu1:
+ * SCRATCH39 = r2 = flag[1]
+ * SCRATCH38 = r3 = flag[0]
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       add     r1, r3, #PMC_SCRATCH37
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addeq   r3, r3, #PMC_SCRATCH39
+       addne   r2, r3, #PMC_SCRATCH39
+       addne   r3, r3, #PMC_SCRATCH38
+
+       mov     r12, #1
+       str     r12, [r2]               @ flag[cpu] = 1
+       dsb
+       str     r12, [r1]               @ !turn = cpu
+1:     dsb
+       ldr     r12, [r3]
+       cmp     r12, #1                 @ flag[!cpu] == 1?
+       ldreq   r12, [r1]
+       cmpeq   r12, r0                 @ !turn == cpu?
+       beq     1b                      @ while !turn == cpu && flag[!cpu] == 1
+
+       mov     pc, lr                  @ locked
+ENDPROC(tegra_pen_lock)
+
+ENTRY(tegra_pen_unlock)
+       dsb
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addne   r2, r3, #PMC_SCRATCH39

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 137

Quoted 4 lines

arch/arm/mach-tegra/sleep-tegra20.S +4 -0

+       mov     r12, #0
+       str     r12, [r2]
+       mov     pc, lr
+ENDPROC(tegra_pen_unlock)

There is an ongoing work to make this locking scheme for MMU/coherency off paths ARM generic, and we do not want to merge yet another platform specific locking mechanism. I will point you to the patchset when it hits LAK.

Hi Lorenzo,

Quoted 68 lines · Lorenzo Pieralisi

Quoted 67 lines · Joseph Lo

The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <[email protected]>
Gary King <[email protected]>

Signed-off-by Joseph Lo <[email protected]>

arch/arm/mach-tegra/sleep-tegra20.S +51 -0

+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]
+ * on cpu1:
+ * SCRATCH39 = r2 = flag[1]
+ * SCRATCH38 = r3 = flag[0]
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       add     r1, r3, #PMC_SCRATCH37
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addeq   r3, r3, #PMC_SCRATCH39
+       addne   r2, r3, #PMC_SCRATCH39
+       addne   r3, r3, #PMC_SCRATCH38
+
+       mov     r12, #1
+       str     r12, [r2]               @ flag[cpu] = 1
+       dsb
+       str     r12, [r1]               @ !turn = cpu
+1:     dsb
+       ldr     r12, [r3]
+       cmp     r12, #1                 @ flag[!cpu] == 1?
+       ldreq   r12, [r1]
+       cmpeq   r12, r0                 @ !turn == cpu?
+       beq     1b                      @ while !turn == cpu && flag[!cpu] == 1
+
+       mov     pc, lr                  @ locked
+ENDPROC(tegra_pen_lock)
+
+ENTRY(tegra_pen_unlock)
+       dsb
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addne   r2, r3, #PMC_SCRATCH39

Quoted 9 lines

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 137

Quoted 4 lines

arch/arm/mach-tegra/sleep-tegra20.S +4 -0

+       mov     r12, #0
+       str     r12, [r2]
+       mov     pc, lr
+ENDPROC(tegra_pen_unlock)

There is an ongoing work to make this locking scheme for MMU/coherency off paths ARM generic, and we do not want to merge yet another platform specific locking mechanism. I will point you to the patchset when it hits LAK.

You did mention there is an ARM generic locking scheme for MMU/coherency off case before. Do you mean the patch below?

https://patchwork.kernel.org/patch/1957911/
https://patchwork.kernel.org/patch/1957901/

I gave it a review today. Looks it can't fit our usage for CPU idle powered-down mode on Tegra20.

The generic mechanism only can be used when CPUs in non coherent world. But our usage needs the mechanism could be used in both coherent and non coherent case. OK. The case is we need to sync the status about the CPU1 was ready to power down. In this case, the CPU0 is still in coherent world but the CPU1 isn't. So we need the locking scheme could be still safe in this situation.

And the proposed scheme looks only for b.L system?

Quoted 79 lines · Joseph Lo

Quoted 68 lines · Lorenzo Pieralisi

Quoted 67 lines · Joseph Lo

The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <[email protected]>
Gary King <[email protected]>

Signed-off-by Joseph Lo <[email protected]>

arch/arm/mach-tegra/sleep-tegra20.S +51 -0

+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]
+ * on cpu1:
+ * SCRATCH39 = r2 = flag[1]
+ * SCRATCH38 = r3 = flag[0]
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       add     r1, r3, #PMC_SCRATCH37
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addeq   r3, r3, #PMC_SCRATCH39
+       addne   r2, r3, #PMC_SCRATCH39
+       addne   r3, r3, #PMC_SCRATCH38
+
+       mov     r12, #1
+       str     r12, [r2]               @ flag[cpu] = 1
+       dsb
+       str     r12, [r1]               @ !turn = cpu
+1:     dsb
+       ldr     r12, [r3]
+       cmp     r12, #1                 @ flag[!cpu] == 1?
+       ldreq   r12, [r1]
+       cmpeq   r12, r0                 @ !turn == cpu?
+       beq     1b                      @ while !turn == cpu && flag[!cpu] == 1
+
+       mov     pc, lr                  @ locked
+ENDPROC(tegra_pen_lock)
+
+ENTRY(tegra_pen_unlock)
+       dsb
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addne   r2, r3, #PMC_SCRATCH39

Quoted 9 lines

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 137

Quoted 4 lines

arch/arm/mach-tegra/sleep-tegra20.S +4 -0

+       mov     r12, #0
+       str     r12, [r2]
+       mov     pc, lr
+ENDPROC(tegra_pen_unlock)

There is an ongoing work to make this locking scheme for MMU/coherency off paths ARM generic, and we do not want to merge yet another platform specific locking mechanism. I will point you to the patchset when it hits LAK.

Quoted 5 lines

You did mention there is an ARM generic locking scheme for MMU/coherency off case before. Do you mean the patch below?

https://patchwork.kernel.org/patch/1957911/
https://patchwork.kernel.org/patch/1957901/

Those are used for first-man election when multiple CPUs come out of idle at once.

You should have a look at the entire series and in particular:

https://patchwork.kernel.org/patch/1957891/
https://patchwork.kernel.org/patch/1957951/

Quoted 9 lines

I gave it a review today. Looks it can't fit our usage for CPU idle powered-down mode on Tegra20.

The generic mechanism only can be used when CPUs in non coherent world. But our usage needs the mechanism could be used in both coherent and non coherent case. OK. The case is we need to sync the status about the CPU1 was ready to power down. In this case, the CPU0 is still in coherent world but the CPU1 isn't. So we need the locking scheme could be still safe in this situation.

I know, I implemented something of that sort for an A9 based development platform, that's why I pointed you to this new patchset.

Have a look at the series, it should do what you want.

Quoted 104 lines · Lorenzo Pieralisi

Quoted 79 lines · Joseph Lo

Quoted 68 lines · Lorenzo Pieralisi

Quoted 67 lines · Joseph Lo

The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <[email protected]>
Gary King <[email protected]>

Signed-off-by Joseph Lo <[email protected]>

arch/arm/mach-tegra/sleep-tegra20.S +51 -0

+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]
+ * on cpu1:
+ * SCRATCH39 = r2 = flag[1]
+ * SCRATCH38 = r3 = flag[0]
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       add     r1, r3, #PMC_SCRATCH37
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addeq   r3, r3, #PMC_SCRATCH39
+       addne   r2, r3, #PMC_SCRATCH39
+       addne   r3, r3, #PMC_SCRATCH38
+
+       mov     r12, #1
+       str     r12, [r2]               @ flag[cpu] = 1
+       dsb
+       str     r12, [r1]               @ !turn = cpu
+1:     dsb
+       ldr     r12, [r3]
+       cmp     r12, #1                 @ flag[!cpu] == 1?
+       ldreq   r12, [r1]
+       cmpeq   r12, r0                 @ !turn == cpu?
+       beq     1b                      @ while !turn == cpu && flag[!cpu] == 1
+
+       mov     pc, lr                  @ locked
+ENDPROC(tegra_pen_lock)
+
+ENTRY(tegra_pen_unlock)
+       dsb
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addne   r2, r3, #PMC_SCRATCH39

Quoted 9 lines

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 137

Quoted 4 lines

arch/arm/mach-tegra/sleep-tegra20.S +4 -0

+       mov     r12, #0
+       str     r12, [r2]
+       mov     pc, lr
+ENDPROC(tegra_pen_unlock)

There is an ongoing work to make this locking scheme for MMU/coherency off paths ARM generic, and we do not want to merge yet another platform specific locking mechanism. I will point you to the patchset when it hits LAK.

Quoted 5 lines

You did mention there is an ARM generic locking scheme for MMU/coherency off case before. Do you mean the patch below?

https://patchwork.kernel.org/patch/1957911/
https://patchwork.kernel.org/patch/1957901/

Those are used for first-man election when multiple CPUs come out of idle at once.

You should have a look at the entire series and in particular:

https://patchwork.kernel.org/patch/1957891/
https://patchwork.kernel.org/patch/1957951/

Quoted 9 lines

I gave it a review today. Looks it can't fit our usage for CPU idle powered-down mode on Tegra20.

The generic mechanism only can be used when CPUs in non coherent world. But our usage needs the mechanism could be used in both coherent and non coherent case. OK. The case is we need to sync the status about the CPU1 was ready to power down. In this case, the CPU0 is still in coherent world but the CPU1 isn't. So we need the locking scheme could be still safe in this situation.

Quoted 5 lines

I know, I implemented something of that sort for an A9 based development platform, that's why I pointed you to this new patchset.

Have a look at the series, it should do what you want.

Hi Lorenzo,

May I upstream this stuff first? I can promise to you I will re-work a common CPUs and cluster power sync wrappers (platform_power_ops) for all Tegra series that based on the generic framework. Because we didn't have this work in Tegra tree yet and we indeed need it for supporting cluster power down and switching.

But it need lots of time for re-work, testing and verification. And I have lots of patches that need the function of cpu suspend that be introduced in this patch series to support platform suspend for Tegra.

So I am asking the permission here for upstream this series first and I will continue the job to come out a common CPUs and cluster power sync wrappers for Tegra that we indeed need it to support cluster power down and switching.

Quoted 41 lines · Joseph Lo

Quoted 27 lines · Lorenzo Pieralisi

Quoted 7 lines · Joseph Lo

Quoted 1 line · Lorenzo Pieralisi

On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:

You did mention there is an ARM generic locking scheme for MMU/coherency off case before. Do you mean the patch below?

https://patchwork.kernel.org/patch/1957911/
https://patchwork.kernel.org/patch/1957901/

Those are used for first-man election when multiple CPUs come out of idle at once.

You should have a look at the entire series and in particular:

https://patchwork.kernel.org/patch/1957891/
https://patchwork.kernel.org/patch/1957951/

Quoted 9 lines

I gave it a review today. Looks it can't fit our usage for CPU idle powered-down mode on Tegra20.

The generic mechanism only can be used when CPUs in non coherent world. But our usage needs the mechanism could be used in both coherent and non coherent case. OK. The case is we need to sync the status about the CPU1 was ready to power down. In this case, the CPU0 is still in coherent world but the CPU1 isn't. So we need the locking scheme could be still safe in this situation.

Quoted 5 lines

I know, I implemented something of that sort for an A9 based development platform, that's why I pointed you to this new patchset.

Have a look at the series, it should do what you want.

Hi Lorenzo,

May I upstream this stuff first? I can promise to you I will re-work a common CPUs and cluster power sync wrappers (platform_power_ops) for all Tegra series that based on the generic framework. Because we didn't have this work in Tegra tree yet and we indeed need it for supporting cluster power down and switching.

Quoted 8 lines

But it need lots of time for re-work, testing and verification. And I have lots of patches that need the function of cpu suspend that be introduced in this patch series to support platform suspend for Tegra.

So I am asking the permission here for upstream this series first and I will continue the job to come out a common CPUs and cluster power sync wrappers for Tegra that we indeed need it to support cluster power down and switching.

I understand that and you should not ask me permission :-) since I am not a maintainer. I just wanted to save you some effort, you will end up rewriting the whole thing anyway IMHO and I think the power API would have saved you time if it were there before.

If you need help to integrate the power API please do ask questions.

Hi Lorenzo,

Quoted 68 lines · Lorenzo Pieralisi

Quoted 67 lines · Joseph Lo

The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <[email protected]>
Gary King <[email protected]>

Signed-off-by Joseph Lo <[email protected]>

arch/arm/mach-tegra/sleep-tegra20.S +51 -0

+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]
+ * on cpu1:
+ * SCRATCH39 = r2 = flag[1]
+ * SCRATCH38 = r3 = flag[0]
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       add     r1, r3, #PMC_SCRATCH37
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addeq   r3, r3, #PMC_SCRATCH39
+       addne   r2, r3, #PMC_SCRATCH39
+       addne   r3, r3, #PMC_SCRATCH38
+
+       mov     r12, #1
+       str     r12, [r2]               @ flag[cpu] = 1
+       dsb
+       str     r12, [r1]               @ !turn = cpu
+1:     dsb
+       ldr     r12, [r3]
+       cmp     r12, #1                 @ flag[!cpu] == 1?
+       ldreq   r12, [r1]
+       cmpeq   r12, r0                 @ !turn == cpu?
+       beq     1b                      @ while !turn == cpu && flag[!cpu] == 1
+
+       mov     pc, lr                  @ locked
+ENDPROC(tegra_pen_lock)
+
+ENTRY(tegra_pen_unlock)
+       dsb
+       mov32   r3, TEGRA_PMC_VIRT
+       cpu_id  r0
+       cmp     r0, #0
+       addeq   r2, r3, #PMC_SCRATCH38
+       addne   r2, r3, #PMC_SCRATCH39

Quoted 9 lines

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 137

Quoted 4 lines

arch/arm/mach-tegra/sleep-tegra20.S +4 -0

+       mov     r12, #0
+       str     r12, [r2]
+       mov     pc, lr
+ENDPROC(tegra_pen_unlock)

There is an ongoing work to make this locking scheme for MMU/coherency off paths ARM generic, and we do not want to merge yet another platform specific locking mechanism. I will point you to the patchset when it hits LAK.

You did mention there is an ARM generic locking scheme for MMU/coherency off case before. Do you mean the patch below?

https://patchwork.kernel.org/patch/1957911/
https://patchwork.kernel.org/patch/1957901/

I gave it a review today. Looks it can't fit our usage for CPU idle powered-down mode on Tegra20.

The generic mechanism only can be used when CPUs in non coherent world. But our usage needs the mechanism could be used in both coherent and non coherent case. OK. The case is we need to sync the status about the CPU1 was ready to power down. In this case, the CPU0 is still in coherent world but the CPU1 isn't. So we need the locking scheme could be still safe in this situation.

And the proposed scheme looks only for b.L system?

The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down".

Quoted 10 lines · Joseph Lo

The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down".

arch/arm/mach-tegra/cpuidle-tegra20.c line 120

Quoted 5 lines

arch/arm/mach-tegra/cpuidle-tegra20.c +2 -0

 
+static int __cpuinit tegra20_idle_lp2(struct cpuidle_device *dev,
 
+	return (entered_lp2) ? index : 0;

No need for the brackets there.

BTW, could you Cc Colin Cross on any future revisions of these patches; it'd be good to get his take on them.

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 95

Quoted 8 lines

arch/arm/mach-tegra/sleep-tegra20.S +5 -0

 
+/*
+ * tegra_pen_lock
 
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]

It would be slightly clearer if that was written:

* r2 = flag[0] (in SCRATCH38)
* r3 = flag[1] (in SCRATCH39)

since the meaning of r2/r3 is what's being selected.

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 116

Quoted 4 lines

arch/arm/mach-tegra/sleep-tegra20.S +4 -0

+	mov	r12, #1
+	str	r12, [r2]		@ flag[cpu] = 1
+	dsb
+	str	r12, [r1]		@ !turn = cpu

Should that be "str r0, [r1]"? Otherwise, you're always writing 1 there, not writing the CPU ID as expected.

Quoted 26 lines · Stephen Warren

Quoted 12 lines · Joseph Lo

The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down".

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 95

Quoted 7 lines

arch/arm/mach-tegra/sleep-tegra20.S +5 -0

 
+/*
+ * tegra_pen_lock
 
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]

It would be slightly clearer if that was written:

* r2 = flag[0] (in SCRATCH38)
* r3 = flag[1] (in SCRATCH39)

Quoted 2 lines

since the meaning of r2/r3 is what's being selected.

OK. Will fix.

Quoted 2 lines

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 114

Quoted 2 lines

arch/arm/mach-tegra/sleep-tegra20.S +2 -0

+	mov	r12, #1
+	str	r12, [r2]		@ flag[cpu] = 1

Quoted 2 lines

arch/arm/mach-tegra/sleep-tegra20.S ENTRY(tegra20_cpu_shutdown) · line 116

Quoted 2 lines

arch/arm/mach-tegra/sleep-tegra20.S +2 -0

+	dsb
+	str	r12, [r1]		@ !turn = cpu

Quoted 2 lines

Should that be "str r0, [r1]"? Otherwise, you're always writing 1 there, not writing the CPU ID as expected.

The CPU_ID was not used to lock or un-lock the flag. Wriging 1 to lock and 0 to release.

	return ret;

drivers/gpio/gpio-tegra.c +35 -1

index 63cb643..32ecdb6 100644
@@ -71,6 +71,7 @@ struct tegra_gpio_bank {
 	u32 oe[4];
 	u32 int_enb[4];
 	u32 int_lvl[4];
+	u32 wake_enb[4];
 #endif
 };
 

@@ -332,6 +333,9 @@ static int tegra_gpio_suspend(struct device *dev)
 			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
 			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
 			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
+
+			/* Enable gpio irq for wake up source */
+			tegra_gpio_writel(bank->wake_enb[p], GPIO_INT_ENB(gpio));
 		}
 	}
 	local_irq_restore(flags);

@@ -341,6 +345,36 @@ static int tegra_gpio_suspend(struct device *dev)
 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 {
 	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+	u8 port, bit, mask;
+	int gpio = d->hwirq;
+
+	if (gpio < 0)
+		return -EIO;
+
+	port = GPIO_PORT(gpio);
+	bit = GPIO_BIT(gpio);
+	mask = BIT(bit);
+
+	if (enable)
+		bank->wake_enb[port] |= mask;
+	else
+		bank->wake_enb[port] &= ~mask;
+
+	return 0;
+}
+
+static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
+{
+	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+	int ret;
+
+	ret = tegra_gpio_wake_enable(d, enable);
+	if (ret) {
+		pr_err("Failed gpio wake %s for irq=%d error=%d\n",
+				(enable ? "enable" : "disable"), d->irq, ret);
+		return ret;
+	}
+printk(KERN_EMERG "gpio back->irq: %d hwirq: %d irq: %d\n", bank->irq, d->hwirq, d->irq);
 	return irq_set_irq_wake(bank->irq, enable);
 }
 #endif

@@ -352,7 +386,7 @@ static struct irq_chip tegra_gpio_irq_chip = {
 	.irq_unmask	= tegra_gpio_irq_unmask,
 	.irq_set_type	= tegra_gpio_irq_set_type,
 #ifdef CONFIG_PM_SLEEP
-	.irq_set_wake	= tegra_gpio_wake_enable,
+	.irq_set_wake	= tegra_gpio_irq_set_wake,
 #endif
 };
 

drivers/input/keyboard/gpio_keys.c +4 -3

index 79435de..0a14ec0 100644
@@ -398,7 +398,7 @@ static irqreturn_t gpio_keys_irq_isr(int irq, void *dev_id)
 	BUG_ON(irq != bdata->irq);
 
 	spin_lock_irqsave(&bdata->lock, flags);
-
+printk(KERN_EMERG "key pressed irq %d\n", bdata->irq);
 	if (!bdata->key_pressed) {
 		if (bdata->button->wakeup)
 			pm_wakeup_event(bdata->input->dev.parent, 0);

@@ -809,8 +809,10 @@ static int gpio_keys_suspend(struct device *dev)
 	if (device_may_wakeup(dev)) {
 		for (i = 0; i < ddata->pdata->nbuttons; i++) {
 			struct gpio_button_data *bdata = &ddata->data[i];
-			if (bdata->button->wakeup)
+			if (bdata->button->wakeup) {
+printk(KERN_EMERG "gpio-key wake irq:%d\n", bdata->irq);
 				enable_irq_wake(bdata->irq);
+			}
 		}
 	} else {
 		mutex_lock(&input->mutex);
--

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config ARCH_TEGRA_3x_SOC

(quoted diff) +1 -0

 	bool "Enable support for Tegra30 family"
+	select ARCH_NEEDS_CPU_IDLE_COUPLED
 	select ARCH_REQUIRE_GPIOLIB
 	select ARM_ERRATA_743622
 	select ARM_ERRATA_751472

arch/arm/mach-tegra/cpuidle-tegra30.c +60 -20

index 5e8cbf5..f880350 100644
@@ -23,6 +23,7 @@
 #include <linux/module.h>
 #include <linux/cpuidle.h>
 #include <linux/cpu_pm.h>
+#include <linux/cpumask.h>
 #include <linux/clockchips.h>
 
 #include <asm/cpuidle.h>

@@ -30,14 +31,18 @@
 #include <asm/suspend.h>
 #include <asm/smp_plat.h>
 
+#include "irq.h"
 #include "pm.h"
 #include "sleep.h"
 #include "tegra_cpu_car.h"
 
 #ifdef CONFIG_PM_SLEEP
-static int tegra30_idle_lp2(struct cpuidle_device *dev,
-			    struct cpuidle_driver *drv,
-			    int index);
+static bool abort_flag;
+static atomic_t abort_barrier;
+static cpumask_t cpus_out_lp2;
+static int tegra30_idle_lp2_coupled(struct cpuidle_device *dev,
+				    struct cpuidle_driver *drv,
+				    int index);
 #endif
 
 static struct cpuidle_driver tegra_idle_driver = {

@@ -53,11 +58,12 @@ static struct cpuidle_driver tegra_idle_driver = {
 		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
 #ifdef CONFIG_PM_SLEEP
 		[1] = {
-			.enter			= tegra30_idle_lp2,
+			.enter			= tegra30_idle_lp2_coupled,
 			.exit_latency		= 2000,
 			.target_residency	= 2200,
 			.power_usage		= 0,
-			.flags			= CPUIDLE_FLAG_TIME_VALID,
+			.flags			= CPUIDLE_FLAG_TIME_VALID |
+						  CPUIDLE_FLAG_COUPLED,
 			.name			= "powered-down",
 			.desc			= "CPU power gated",
 		},

@@ -79,8 +85,8 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
 	/* All CPUs entering LP2 is not working.
 	 * Don't let CPU0 enter LP2 when any secondary CPU is online.
 	 */
-	if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
-		cpu_do_idle();
+	if (num_online_cpus() > 1 && !tegra_cpu_rail_off_ready()) {
+//		cpu_do_idle();
 		return false;
 	}
 

@@ -94,6 +100,13 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
 }
 
 #ifdef CONFIG_SMP
+static void tegra30_wake_up_secondary_cpus(u32 cpu)
+{
+//	if (!cpumask_test_cpu(cpu, &cpus_out_lp2))
+		arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+//		gic_raise_softirq(cpumask_of(cpu), 0);
+}                                       
+
 static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 					struct cpuidle_driver *drv,
 					int index)

@@ -113,6 +126,11 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 	return true;
 }
 #else
+static inline void tegra30_wake_up_secondary_cpus(u32 cpu)
+{
+	return;
+}
+
 static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 					       struct cpuidle_driver *drv,
 					       int index)

@@ -121,36 +139,56 @@ static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 }
 #endif
 
-static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
-				      struct cpuidle_driver *drv,
-				      int index)
+static int __cpuinit tegra30_idle_lp2_coupled(struct cpuidle_device *dev,
+					      struct cpuidle_driver *drv,
+					      int index)
 {
 	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
 	bool entered_lp2 = false;
-	bool last_cpu;
+int i;
+	abort_flag = tegra_pending_irq();
+	cpumask_clear(&cpus_out_lp2);
+	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+//printk(KERN_EMERG "cpu %d in\n", cpu);
+	if (abort_flag)
+		return -EINTR;
 
 	local_fiq_disable();
 
-	last_cpu = tegra_set_cpu_in_lp2(cpu);
+	tegra_set_cpu_in_lp2(cpu);
 	cpu_pm_enter();
 
 	if (cpu == 0) {
-		if (last_cpu)
-			entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
-								     index);
-		else
-			cpu_do_idle();
+		while (num_online_cpus() > 1 && !tegra_cpu_rail_off_ready()) {
+			cpu_relax();
+			
+//			if (!cpumask_empty(&cpus_out_lp2))
+//				goto out;
+		}
+		entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index);
+
+out:
+//		if (!entered_lp2) {
+//			int i;
+			for_each_online_cpu(i)
+				if (i != cpu)
+					tegra30_wake_up_secondary_cpus(i);
+//		}
 	} else {
 		entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
+		cpumask_set_cpu(cpu, &cpus_out_lp2);
 	}
 
+
 	cpu_pm_exit();
 	tegra_clear_cpu_in_lp2(cpu);
-
+//
+//
 	local_fiq_enable();
 
 	smp_rmb();
-
+//printk(KERN_EMERG "cpu %d out\n", cpu);
+cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
 	return (entered_lp2) ? index : 0;
 }
 #endif

@@ -175,6 +213,9 @@ int __init tegra30_cpuidle_init(void)
 	for_each_possible_cpu(cpu) {
 		dev = &per_cpu(tegra_idle_device, cpu);
 		dev->cpu = cpu;
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+		dev->coupled_cpus = *cpu_online_mask;
+#endif
 
 		dev->state_count = drv->state_count;
 		ret = cpuidle_register_device(dev);
--

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