EXYNOS: Add support for Exynos4x12
Subsystems (2)
v2 cover EXYNOS: Add support for Exynos4x12
This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12.
Changes in v2:
- Fixed the GPIO base address macro for exynos4x12_gpio_part3_get_nr in arch/arm/include/asm/arch-exynos/gpio.h
Chander Kashyap (3):
EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +++++- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++ 3 files changed, 402 insertions(+), 7 deletions(-)
Signature · 1 line
1.7.9.5
PATCH v2 1/3 EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
This patch populates base addresses of Exynos4x12 registers.
--- arch/arm/include/asm/arch-exynos/cpu.h | 48 +++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 7 deletions(-)
arch/arm/include/asm/arch-exynos/cpu.h +41 -7
@@ -27,7 +27,7 @@#define EXYNOS_CPU_NAME "Exynos"#define EXYNOS4_ADDR_BASE 0x10000000 -/* EXYNOS4 */ +/* EXYNOS4 Common*/ #define EXYNOS4_GPIO_PART3_BASE 0x03860000#define EXYNOS4_PRO_ID 0x10000000#define EXYNOS4_SYSREG_BASE 0x10010000
@@ -58,7 +58,37 @@#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE -/* EXYNOS5 */ +/* EXYNOS4X12 */ +#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 +#define EXYNOS4X12_PRO_ID 0x10000000 +#define EXYNOS4X12_SYSREG_BASE 0x10010000 +#define EXYNOS4X12_POWER_BASE 0x10020000 +#define EXYNOS4X12_SWRESET 0x10020400 +#define EXYNOS4X12_USBPHY_CONTROL 0x10020704 +#define EXYNOS4X12_CLOCK_BASE 0x10030000 +#define EXYNOS4X12_SYSTIMER_BASE 0x10050000 +#define EXYNOS4X12_WATCHDOG_BASE 0x10060000 +#define EXYNOS4X12_DMC0_BASE 0x10600000 +#define EXYNOS4X12_DMC1_BASE 0x10610000 +#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 +#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_FIMD_BASE 0x11C00000 +#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 +#define EXYNOS4X12_USBOTG_BASE 0x12480000 +#define EXYNOS4X12_MMC_BASE 0x12510000 +#define EXYNOS4X12_SROMC_BASE 0x12570000 +#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000 +#define EXYNOS4X12_USBPHY_BASE 0x125B0000 +#define EXYNOS4X12_UART_BASE 0x13800000 +#define EXYNOS4X12_I2C_BASE 0x13860000 +#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000 + +#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE + +/* EXYNOS5 Common*/ #define EXYNOS5_I2C_SPACING 0x10000#define EXYNOS5_GPIO_PART4_BASE 0x03860000
@@ -146,17 +176,21 @@ static inline int proid_is_##type(void) \ } IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250)#define SAMSUNG_BASE (device, base) \ static inline unsigned int samsung_get_base_##device(void) \ { \ - if (cpu_is_exynos4()) \ - return EXYNOS4_##base; \ - else if (cpu_is_exynos5()) \ + if (cpu_is_exynos4()) { \ + if (proid_is_exynos4412()) \ + return EXYNOS4X12_##base; \ + else \ + return EXYNOS4_##base; \ + } else if (cpu_is_exynos5()) { \ return EXYNOS5_##base; \ - else \ - return 0; \ + } \ + return 0; \ }SAMSUNG_BASE (adc,ADC_BASE )
Signature · 1 line
1.7.9.5
PATCH v2 2/3 EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
In reply to Chander KashyapThis patch adds clock structure for Exynos4x12.
--- arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ 1 file changed, 276 insertions(+)
arch/arm/include/asm/arch-exynos/clock.h +276 -0
@@ -251,6 +251,282 @@ struct exynos4_clock {unsigned int div_iem_l1; }; +struct exynos4x12_clock { +unsigned char res1[0x4200 ]; +unsigned int src_leftbus; +unsigned char res2[0x1fc ]; +unsigned int mux_stat_leftbus; +unsigned char res3[0xfc ]; +unsigned int div_leftbus; +unsigned char res4[0xfc ]; +unsigned int div_stat_leftbus; +unsigned char res5[0x1fc ]; +unsigned int gate_ip_leftbus; +unsigned char res6[0x12c ]; +unsigned int gate_ip_image; +unsigned char res7[0xcc ]; +unsigned int clkout_leftbus; +unsigned int clkout_leftbus_div_stat; +unsigned char res8[0x37f8 ]; +unsigned int src_rightbus; +unsigned char res9[0x1fc ]; +unsigned int mux_stat_rightbus; +unsigned char res10[0xfc ]; +unsigned int div_rightbus; +unsigned char res11[0xfc ]; +unsigned int div_stat_rightbus; +unsigned char res12[0x1fc ]; +unsigned int gate_ip_rightbus; +unsigned char res13[0x15c ]; +unsigned int gate_ip_perir; +unsigned char res14[0x9c ]; +unsigned int clkout_rightbus; +unsigned int clkout_rightbus_div_stat; +unsigned char res15[0x3608 ]; +unsigned int epll_lock; +unsigned char res16[0xc ]; +unsigned int vpll_lock; +unsigned char res17[0xec ]; +unsigned int epll_con0; +unsigned int epll_con1; +unsigned int epll_con2; +unsigned char res18[0x4 ]; +unsigned int vpll_con0; +unsigned int vpll_con1; +unsigned int vpll_con2; +unsigned char res19[0xe4 ]; +unsigned int src_top0; +unsigned int src_top1; +unsigned char res20[0x8 ]; +unsigned int src_cam; +unsigned int src_tv; +unsigned int src_mfc; +unsigned int src_g3d; +unsigned char res21[0x4 ]; +unsigned int src_lcd; +unsigned int src_isp; +unsigned int src_maudio; +unsigned int src_fsys; +unsigned char res22[0xc ]; +unsigned int src_peril0; +unsigned int src_peril1; +unsigned int src_cam1; +unsigned char res23[0xb4 ]; +unsigned int src_mask_top; +unsigned char res24[0xc ]; +unsigned int src_mask_cam; +unsigned int src_mask_tv; +unsigned char res25[0xc ]; +unsigned int src_mask_lcd; +unsigned int src_mask_isp; +unsigned int src_mask_maudio; +unsigned int src_mask_fsys; +unsigned char res26[0xc ]; +unsigned int src_mask_peril0; +unsigned int src_mask_peril1; +unsigned char res27[0xb8 ]; +unsigned int mux_stat_top0; +unsigned int mux_stat_top1; +unsigned char res28[0x10 ]; +unsigned int mux_stat_mfc; +unsigned int mux_stat_g3d; +unsigned char res29[0x28 ]; +unsigned int mux_stat_cam1; +unsigned char res30[0xb4 ]; +unsigned int div_top; +unsigned char res31[0xc ]; +unsigned int div_cam; +unsigned int div_tv; +unsigned int div_mfc; +unsigned int div_g3d; +unsigned char res32[0x4 ]; +unsigned int div_lcd; +unsigned int div_isp; +unsigned int div_maudio; +unsigned int div_fsys0; +unsigned int div_fsys1; +unsigned int div_fsys2; +unsigned int div_fsys3; +unsigned int div_peril0; +unsigned int div_peril1; +unsigned int div_peril2; +unsigned int div_peril3; +unsigned int div_peril4; +unsigned int div_peril5; +unsigned int div_cam1; +unsigned char res33[0x14 ]; +unsigned int div2_ratio; +unsigned char res34[0x8c ]; +unsigned int div_stat_top; +unsigned char res35[0xc ]; +unsigned int div_stat_cam; +unsigned int div_stat_tv; +unsigned int div_stat_mfc; +unsigned int div_stat_g3d; +unsigned char res36[0x4 ]; +unsigned int div_stat_lcd; +unsigned int div_stat_isp; +unsigned int div_stat_maudio; +unsigned int div_stat_fsys0; +unsigned int div_stat_fsys1; +unsigned int div_stat_fsys2; +unsigned int div_stat_fsys3; +unsigned int div_stat_peril0; +unsigned int div_stat_peril1; +unsigned int div_stat_peril2; +unsigned int div_stat_peril3; +unsigned int div_stat_peril4; +unsigned int div_stat_peril5; +unsigned int div_stat_cam1; +unsigned char res37[0x14 ]; +unsigned int div2_stat; +unsigned char res38[0x29c ]; +unsigned int gate_ip_cam; +unsigned int gate_ip_tv; +unsigned int gate_ip_mfc; +unsigned int gate_ip_g3d; +unsigned char res39[0x4 ]; +unsigned int gate_ip_lcd; +unsigned int gate_ip_isp; +unsigned char res40[0x4 ]; +unsigned int gate_ip_fsys; +unsigned char res41[0x8 ]; +unsigned int gate_ip_gps; +unsigned int gate_ip_peril; +unsigned char res42[0xc ]; +unsigned char res43[0x4 ]; +unsigned char res44[0xc ]; +unsigned int gate_block; +unsigned char res45[0x8c ]; +unsigned int clkout_cmu_top; +unsigned int clkout_cmu_top_div_stat; +unsigned char res46[0x3600 ]; +unsigned int mpll_lock; +unsigned char res47[0xfc ]; +unsigned int mpll_con0; +unsigned int mpll_con1; +unsigned char res48[0xf0 ]; +unsigned int src_dmc; +unsigned char res49[0xfc ]; +unsigned int src_mask_dmc; +unsigned char res50[0xfc ]; +unsigned int mux_stat_dmc; +unsigned char res51[0xfc ]; +unsigned int div_dmc0; +unsigned int div_dmc1; +unsigned char res52[0xf8 ]; +unsigned int div_stat_dmc0; +unsigned int div_stat_dmc1; +unsigned char res53[0xf8 ]; +unsigned int gate_bus_dmc0; +unsigned int gate_bus_dmc1; +unsigned char res54[0x1f8 ]; +unsigned int gate_ip_dmc0; +unsigned int gate_ip_dmc1; +unsigned char res55[0xf8 ]; +unsigned int clkout_cmu_dmc; +unsigned int clkout_cmu_dmc_div_stat; +unsigned char res56[0x5f8 ]; +unsigned int dcgidx_map0; +unsigned int dcgidx_map1; +unsigned int dcgidx_map2; +unsigned char res57[0x14 ]; +unsigned int dcgperf_map0; +unsigned int dcgperf_map1; +unsigned char res58[0x18 ]; +unsigned int dvcidx_map; +unsigned char res59[0x1c ]; +unsigned int freq_cpu; +unsigned int freq_dpm; +unsigned char res60[0x18 ]; +unsigned int dvsemclk_en; +unsigned int maxperf; +unsigned char res61[0x8 ]; +unsigned int dmc_freq_ctrl; +unsigned int dmc_pause_ctrl; +unsigned int dddrphy_lock_ctrl; +unsigned int c2c_state; +unsigned char res62[0x2f60 ]; +unsigned int apll_lock; +unsigned char res63[0x8 ]; +unsigned char res64[0xf4 ]; +unsigned int apll_con0; +unsigned int apll_con1; +unsigned char res65[0xf8 ]; +unsigned int src_cpu; +unsigned char res66[0x1fc ]; +unsigned int mux_stat_cpu; +unsigned char res67[0xfc ]; +unsigned int div_cpu0; +unsigned int div_cpu1; +unsigned char res68[0xf8 ]; +unsigned int div_stat_cpu0; +unsigned int div_stat_cpu1; +unsigned char res69[0x2f8 ]; +unsigned int clk_gate_ip_cpu; +unsigned char res70[0xfc ]; +unsigned int clkout_cmu_cpu; +unsigned int clkout_cmu_cpu_div_stat; +unsigned char res71[0x5f8 ]; +unsigned int armclk_stopctrl; +unsigned int atclk_stopctrl; +unsigned char res72[0x10 ]; +unsigned char res73[0x8 ]; +unsigned int pwr_ctrl; +unsigned int pwr_ctrl2; +unsigned char res74[0xd8 ]; +unsigned int apll_con0_l8; +unsigned int apll_con0_l7; +unsigned int apll_con0_l6; +unsigned int apll_con0_l5; +unsigned int apll_con0_l4; +unsigned int apll_con0_l3; +unsigned int apll_con0_l2; +unsigned int apll_con0_l1; +unsigned int iem_control; +unsigned char res75[0xdc ]; +unsigned int apll_con1_l8; +unsigned int apll_con1_l7; +unsigned int apll_con1_l6; +unsigned int apll_con1_l5; +unsigned int apll_con1_l4; +unsigned int apll_con1_l3; +unsigned int apll_con1_l2; +unsigned int apll_con1_l1; +unsigned char res76[0xe0 ]; +unsigned int div_iem_l8; +unsigned int div_iem_l7; +unsigned int div_iem_l6; +unsigned int div_iem_l5; +unsigned int div_iem_l4; +unsigned int div_iem_l3; +unsigned int div_iem_l2; +unsigned int div_iem_l1; +unsigned char res77[0xe0 ]; +unsigned int l2_status; +unsigned char res78[0xc ]; +unsigned int cpu_status; +unsigned char res79[0xc ]; +unsigned int ptm_status; +unsigned char res80[0x2edc ]; +unsigned int div_isp0; +unsigned int div_isp1; +unsigned char res81[0xf8 ]; +unsigned int div_stat_isp0; +unsigned int div_stat_isp1; +unsigned char res82[0x3f8 ]; +unsigned int gate_ip_isp0; +unsigned int gate_ip_isp1; +unsigned char res83[0x1f8 ]; +unsigned int clkout_cmu_isp; +unsigned int clkout_cmu_ispd_div_stat; +unsigned char res84[0xf8 ]; +unsigned int cmu_isp_spar0; +unsigned int cmu_isp_spar1; +unsigned int cmu_isp_spar2; +unsigned int cmu_isp_spar3; +}; +struct exynos5_clock {unsigned int apll_lock;unsigned char res1[0xfc ];
Signature · 1 line
1.7.9.5
PATCH v2 3/3 EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
In reply to Chander KashyapThis patch adds gpio structure for Exynos4x12.
--- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+)
arch/arm/include/asm/arch-exynos/gpio.h +85 -0
@@ -79,6 +79,67 @@ struct exynos4_gpio_part3 {struct s5p_gpio_bank z; }; +struct exynos4x12_gpio_part1 { +struct s5p_gpio_bank a0; +struct s5p_gpio_bank a1; +struct s5p_gpio_bank b; +struct s5p_gpio_bank c0; +struct s5p_gpio_bank c1; +struct s5p_gpio_bank d0; +struct s5p_gpio_bank d1; +struct s5p_gpio_bank res1[0x5 ]; +struct s5p_gpio_bank f0; +struct s5p_gpio_bank f1; +struct s5p_gpio_bank f2; +struct s5p_gpio_bank f3; +struct s5p_gpio_bank res2[0x2 ]; +struct s5p_gpio_bank j0; +struct s5p_gpio_bank j1; +}; + +struct exynos4x12_gpio_part2 { +struct s5p_gpio_bank res1[0x2 ]; +struct s5p_gpio_bank k0; +struct s5p_gpio_bank k1; +struct s5p_gpio_bank k2; +struct s5p_gpio_bank k3; +struct s5p_gpio_bank l0; +struct s5p_gpio_bank l1; +struct s5p_gpio_bank l2; +struct s5p_gpio_bank y0; +struct s5p_gpio_bank y1; +struct s5p_gpio_bank y2; +struct s5p_gpio_bank y3; +struct s5p_gpio_bank y4; +struct s5p_gpio_bank y5; +struct s5p_gpio_bank y6; +struct s5p_gpio_bank res2[0x3 ]; +struct s5p_gpio_bank m0; +struct s5p_gpio_bank m1; +struct s5p_gpio_bank m2; +struct s5p_gpio_bank m3; +struct s5p_gpio_bank m4; +struct s5p_gpio_bank res3[0x48 ]; +struct s5p_gpio_bank x0; +struct s5p_gpio_bank x1; +struct s5p_gpio_bank x2; +struct s5p_gpio_bank x3; +}; + +struct exynos4x12_gpio_part3 { +struct s5p_gpio_bank z; +}; + +struct exynos4x12_gpio_part4 { +struct s5p_gpio_bank v0; +struct s5p_gpio_bank v1; +struct s5p_gpio_bank res1[0x1 ]; +struct s5p_gpio_bank v2; +struct s5p_gpio_bank v3; +struct s5p_gpio_bank res2[0x1 ]; +struct s5p_gpio_bank v4; +}; +struct exynos5_gpio_part1 {struct s5p_gpio_bank a0;struct s5p_gpio_bank a1;
@@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) +#define exynos4x12_gpio_part1_get_nr (bank, pin) \ + ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ + EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part2_get_nr (bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ + EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) + +#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part3_get_nr (bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ + EXYNOS4X12_GPIO_PART3_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) +#define exynos5_gpio_part1_get_nr (bank, pin) \ ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ EXYNOS5_GPIO_PART1_BASE)->bank)) \
Signature · 1 line
1.7.9.5
v2 cover EXYNOS: Add support for Exynos4x12
In reply to Chander KashyapDear Chander Kashyap,
Quoted 11 lines
This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12.
Changes in v2:
- Fixed the GPIO base address macro forexynos4x12_gpio_part3_get_nrinarch/arm/include/asm/arch-exynos/gpio.h
Chander Kashyap (3):
EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
Quoted 5 lines
arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +++++- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++ 3 files changed, 402 insertions(+), 7 deletions(-)
CCing Minkyu
Best regards,
Marek Vasut
v2 cover EXYNOS: Add support for Exynos4x12
Dear Marek,
thanks.
Quoted 13 lines · Marek Vasut
Dear Chander Kashyap,
Quoted 11 lines
This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12.
Changes in v2:
- Fixed the GPIO base address macro forexynos4x12_gpio_part3_get_nrinarch/arm/include/asm/arch-exynos/gpio.h
Chander Kashyap (3):
EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
Quoted 7 lines
Quoted 5 lines
arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +++++- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++ 3 files changed, 402 insertions(+), 7 deletions(-)CCing Minkyu
mk7.kang at samsung.com is also Minkyu's ID.
Quoted 3 lines
Best regards,
Marek Vasut
Signature · 2 lines
with warm regards, Chander Kashyap
v2 cover EXYNOS: Add support for Exynos4x12
Quoted 3 lines · Chander Kashyap
Quoted 1 line
CCing Minkyu
mk7.kang at samsung.com is also Minkyu's ID.
Quoted 1 line
Tip: Always place a blank line before/after your comments, when replying mails. That makes it much more readable to others.
v2 cover EXYNOS: Add support for Exynos4x12
In reply to Chander Kashyapping
Quoted 19 lines · Chander Kashyap
This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12.
Changes in v2:
- Fixed the GPIO base address macro forexynos4x12_gpio_part3_get_nrinarch/arm/include/asm/arch-exynos/gpio.h
Chander Kashyap (3):
EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +++++- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++ 3 files changed, 402 insertions(+), 7 deletions(-)--
1.7.9.5
Signature · 2 lines
with warm regards, Chander Kashyap
v2 cover EXYNOS: Add support for Exynos4x12
Dear Chander Kashyap,
Quoted 1 line
ping
CCing custodian.
Quoted 15 lines · Chander Kashyap
Quoted 14 lines
This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12.
Changes in v2:
- Fixed the GPIO base address macro for
exynos4x12_gpio_part3_get_nrin
arch/arm/include/asm/arch-exynos/gpio.hChander Kashyap (3):
EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
Quoted 8 lines
Quoted 8 lines
arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +++++- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++ 3 files changed, 402 insertions(+), 7 deletions(-)--
1.7.9.5
Best regards,
Marek Vasut
v2 cover EXYNOS: Add support for Exynos4x12
In reply to Chander KashyapDear Chander,
Quoted 19 lines · Chander Kashyap
ping
Quoted 16 lines · Chander Kashyap
This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12.
Changes in v2:
- Fixed the GPIO base address macro forexynos4x12_gpio_part3_get_nrinarch/arm/include/asm/arch-exynos/gpio.h
Chander Kashyap (3):
EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +++++- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++ 3 files changed, 402 insertions(+), 7 deletions(-)
Patches are looks good.
Please rebase this patchset.
Thanks.
Minkyu Kang.
v2 cover EXYNOS: Add support for Exynos4x12
Dear Minkyu,
Quoted 17 lines · Minkyu Kang
Dear Chander,
Quoted 14 lines · Chander Kashyap
ping
Quoted 11 lines · Chander Kashyap
This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12.
Changes in v2:
- Fixed the GPIO base address macro forexynos4x12_gpio_part3_get_nrinarch/arm/include/asm/arch-exynos/gpio.h
Chander Kashyap (3):
EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
Quoted 8 lines
Quoted 5 lines
Quoted 5 lines
arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +++++- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++ 3 files changed, 402 insertions(+), 7 deletions(-)Patches are looks good.
Please rebase this patchset.
Sure i will resend after re-basing.
Quoted 4 lines
Thanks.
Minkyu Kang.
Signature · 2 lines
with warm regards, Chander Kashyap