V4 S3C64XX: Switch all I/O to use readl/writel functio and Clear SMDK64XX

index 04caeef..47326d6 100644
@@ -54,7 +54,7 @@
 /* input clock of PLL: SMDK6400 has 12MHz input clock */
 #define CONFIG_SYS_CLK_FREQ	12000000
 
-#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
+#if !defined(CONFIG_NAND_U_BOOT) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
 #define CONFIG_ENABLE_MMU
 #endif
 

new file mode 100644
index 0000000..a1bf3ab
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_NAND_H__
+#define __ASM_ARCH_NAND_H__
+
+#define NFCONF_OFFSET		0x00
+#define NFCONT_OFFSET		0x04
+
+#define NFCONF_ECC_4BIT		(1<<24)
+
+#define NFCONT_ECC_ENC		(1<<18)
+#define NFCONT_WP		(1<<16)
+#define NFCONT_MECCLOCK		(1<<7)
+#define NFCONT_SECCLOCK		(1<<6)
+#define NFCONT_INITMECC		(1<<5)
+#define NFCONT_INITSECC		(1<<4)
+#define NFCONT_INITECC		(NFCONT_INITMECC | NFCONT_INITSECC)
+#define NFCONT_CS_ALT		(1<<2)
+#define NFCONT_CS		(1<<1)
+#define NFCONT_ENABLE		(1<<0)
+
+#define NFSTAT_ECCENCDONE	(1<<7)
+#define NFSTAT_ECCDECDONE	(1<<6)
+#define NFSTAT_RnB		(1<<0)
+
+#define NFESTAT0_ECCBUSY	(1<<31)
+
+#ifndef __ASSEMBLY__
+/* NAND FLASH */
+struct s3c64xx_nand {
+	u32	nfconf;
+	u32	nfcont;
+	u32	nfcmmd;
+	u32	nfaddr;
+	u32	nfdata;
+	u32	nfmeccdata0;
+	u32	nfmeccdata1;
+	u32	nfseccdata0;
+	u32	nfsblk;
+	u32	nfeblk;
+	u32	nfstat;
+	u32	nfestat0;
+	u32	nfestat1;
+	u32	nfmecc0;
+	u32	nfmecc1;
+	u32	nfsecc;
+	u32	nfmlcbitpt;
+};
+#endif
+
+#endif

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index d6c5dd9..77b9509 100644
@@ -582,62 +582,6 @@
  */
 #define ELFIN_UART_BASE		0x7F005000
 
-#define ELFIN_UART0_OFFSET	0x0000
-#define ELFIN_UART1_OFFSET	0x0400
-#define ELFIN_UART2_OFFSET	0x0800
-
-#define ULCON_OFFSET		0x00
-#define UCON_OFFSET		0x04
-#define UFCON_OFFSET		0x08
-#define UMCON_OFFSET		0x0C
-#define UTRSTAT_OFFSET		0x10
-#define UERSTAT_OFFSET		0x14
-#define UFSTAT_OFFSET		0x18
-#define UMSTAT_OFFSET		0x1C
-#define UTXH_OFFSET		0x20
-#define URXH_OFFSET		0x24
-#define UBRDIV_OFFSET		0x28
-#define UDIVSLOT_OFFSET		0x2C
-#define UINTP_OFFSET		0x30
-#define UINTSP_OFFSET		0x34
-#define UINTM_OFFSET		0x38
-
-#define ULCON0_REG		__REG(0x7F005000)
-#define UCON0_REG		__REG(0x7F005004)
-#define UFCON0_REG		__REG(0x7F005008)
-#define UMCON0_REG		__REG(0x7F00500C)
-#define UTRSTAT0_REG		__REG(0x7F005010)
-#define UERSTAT0_REG		__REG(0x7F005014)
-#define UFSTAT0_REG		__REG(0x7F005018)
-#define UMSTAT0_REG		__REG(0x7F00501c)
-#define UTXH0_REG		__REG(0x7F005020)
-#define URXH0_REG		__REG(0x7F005024)
-#define UBRDIV0_REG		__REG(0x7F005028)
-#define UDIVSLOT0_REG		__REG(0x7F00502c)
-#define UINTP0_REG		__REG(0x7F005030)
-#define UINTSP0_REG		__REG(0x7F005034)
-#define UINTM0_REG		__REG(0x7F005038)
-
-#define ULCON1_REG		__REG(0x7F005400)
-#define UCON1_REG		__REG(0x7F005404)
-#define UFCON1_REG		__REG(0x7F005408)
-#define UMCON1_REG		__REG(0x7F00540C)
-#define UTRSTAT1_REG		__REG(0x7F005410)
-#define UERSTAT1_REG		__REG(0x7F005414)
-#define UFSTAT1_REG		__REG(0x7F005418)
-#define UMSTAT1_REG		__REG(0x7F00541c)
-#define UTXH1_REG		__REG(0x7F005420)
-#define URXH1_REG		__REG(0x7F005424)
-#define UBRDIV1_REG		__REG(0x7F005428)
-#define UDIVSLOT1_REG		__REG(0x7F00542c)
-#define UINTP1_REG		__REG(0x7F005430)
-#define UINTSP1_REG		__REG(0x7F005434)
-#define UINTM1_REG		__REG(0x7F005438)
-
-#define UTRSTAT_TX_EMPTY	(1 << 2)
-#define UTRSTAT_RX_READY	(1 << 0)
-#define UART_ERR_MASK		0xF
-
 /*
  * PWM timer
  */

@@ -804,17 +748,12 @@
 #define DMC_DDR_USER_CONFIG	1
 
 #ifndef __ASSEMBLY__
-enum s3c64xx_uarts_nr {
-	S3C64XX_UART0,
-	S3C64XX_UART1,
-	S3C64XX_UART2,
-};
 
 #include "s3c64x0.h"
 
-static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
+static inline unsigned long s3c64xx_get_base_uart(void)
 {
-	return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
+	return ELFIN_UART_BASE;
 }
 
 static inline unsigned long s3c64xx_get_base_nand(void)

index 0bbf1d0..7add68c 100644
@@ -40,37 +40,6 @@
 
 #include <asm/types.h>
 
-/* UART (see manual chapter 11) */
-typedef struct {
-	volatile u32	ULCON;
-	volatile u32	UCON;
-	volatile u32	UFCON;
-	volatile u32	UMCON;
-	volatile u32	UTRSTAT;
-	volatile u32	UERSTAT;
-	volatile u32	UFSTAT;
-	volatile u32	UMSTAT;
-#ifdef __BIG_ENDIAN
-	volatile u8	res1[3];
-	volatile u8	UTXH;
-	volatile u8	res2[3];
-	volatile u8	URXH;
-#else /* Little Endian */
-	volatile u8	UTXH;
-	volatile u8	res1[3];
-	volatile u8	URXH;
-	volatile u8	res2[3];
-#endif
-	volatile u32	UBRDIV;
-#ifdef __BIG_ENDIAN
-	volatile u8	res3[2];
-	volatile u16	UDIVSLOT;
-#else
-	volatile u16	UDIVSLOT;
-	volatile u8	res3[2];
-#endif
-} s3c64xx_uart;
-
 /* PWM TIMER (see manual chapter 10) */
 typedef struct {
 	volatile u32	TCNTB;

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index 47326d6..d85ddeb 100644
@@ -141,6 +141,9 @@
 
 #define CONFIG_SYS_HZ			1000
 
+/* PWM */
+#define CONFIG_PWM			1
+
 /*-----------------------------------------------------------------------
  * Stack sizes
  *

index f16a37b..47d7731 100644
@@ -1,23 +1,8 @@
 /*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
+ * Copyright (C) 2012
+ * Zhong Hongbo <[email protected]>
  *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <[email protected]>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <[email protected]>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <[email protected]>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <[email protected]>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <[email protected]>
+ * based on arch/arm/cpu/armv7/s5p-common/timer.c
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -39,64 +24,29 @@
  */
 
 #include <common.h>
-#include <asm/proc-armv/ptrace.h>
+#include <asm/io.h>
 #include <asm/arch/s3c6400.h>
-#include <div64.h>
-
-static ulong timer_load_val;
+#include <asm/arch/pwm.h>
+#include <pwm.h>
 
-#define PRESCALER	167
+DECLARE_GLOBAL_DATA_PTR;
 
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
-	return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
+static unsigned long get_current_tick(void);
 
 /* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
+static inline struct s3c_timer *s3c_get_base_timer(void)
 {
-	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-	return timers->TCNTO4;
+	return (struct s3c_timer *)s3c64xx_get_base_timer();
 }
 
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
 int timer_init(void)
 {
-	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-	/* use PWM Timer 4 because it has no output */
-	/*
-	 * We use the following scheme for the timer:
-	 * Prescaler is hard fixed at 167, divider at 1/4.
-	 * This gives at PCLK frequency 66MHz approx. 10us ticks
-	 * The timer is set to wrap after 100s, at 66MHz this obviously
-	 * happens after 10,000,000 ticks. A long variable can thus
-	 * keep values up to 40,000s, i.e., 11 hours. This should be
-	 * enough for most uses:-) Possible optimizations: select a
-	 * binary-friendly frequency, e.g., 1ms / 128. Also calculate
-	 * the prescaler automatically for other PCLK frequencies.
-	 */
-	timers->TCFG0 = PRESCALER << 8;
-	if (timer_load_val == 0) {
-		timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
-		timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
-	}
-
-	/* load value for 10 ms timeout */
-	lastdec = timers->TCNTB4 = timer_load_val;
-	/* auto load, manual update of Timer 4 */
-	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
-		TCON_4_UPDATE;
+	/* PWM Timer 4 */
+	pwm_init(4, MUX_DIV_2, 0);
+	pwm_config(4, 0, 0);
+	pwm_enable(4);
 
-	/* auto load, start Timer 4 */
-	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
-	timestamp = 0;
+	reset_timer_masked();
 
 	return 0;
 }

@@ -104,57 +54,100 @@ int timer_init(void)
 /*
  * timer without interrupts
  */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
+unsigned long get_timer(unsigned long base)
 {
-	ulong now = read_timer();
+	return get_timer_masked() - base;
+}
 
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+	struct s3c_timer *timer = s3c_get_base_timer();
+	unsigned long tmo, tmp, count_value;
+
+	count_value = readl(&timer->tcntb4);
+
+	if (usec >= 1000) {
+		/*
+		 * if "big" number, spread normalization
+		 * to seconds
+		 * 1. start to normalize for usec to ticks per sec
+		 * 2. find number of "ticks" to wait to achieve target
+		 * 3. finish normalize.
+		 */
+		tmo = usec / 1000;
+		tmo *= (CONFIG_SYS_HZ * count_value);
+		tmo /= 1000;
 	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + timer_load_val - now;
+		/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ * count_value;
+		tmo /= (1000 * 1000);
 	}
-	lastdec = now;
 
-	return timestamp;
+	/* get current timestamp */
+	tmp = get_current_tick();
+
+	/* if setting this fordward will roll time stamp */
+	/* reset "advancing" timestamp to 0, set lastinc value */
+	/* else, set advancing stamp wake up time */
+	if ((tmo + tmp + 1) < tmp)
+		reset_timer_masked();
+	else
+		tmo += tmp;
+
+	/* loop till event */
+	while (get_current_tick() < tmo)
+
+		;	/* nop */
 }
 
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
+void reset_timer_masked(void)
 {
-	/* We overrun in 100s */
-	return (ulong)(timer_load_val / 100);
+	struct s3c_timer *timer = s3c_get_base_timer();
+
+	/* reset time */
+	gd->lastinc = readl(&timer->tcnto4);
+	gd->tbl = 0;
 }
 
-ulong get_timer_masked(void)
+unsigned long get_timer_masked(void)
 {
-	unsigned long long res = get_ticks();
-	do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
-	return res;
+	struct s3c_timer *timer = s3c_get_base_timer();
+	unsigned long count_value = readl(&timer->tcntb4);
+
+	return get_current_tick() / count_value;
 }
 
-ulong get_timer(ulong base)
+static unsigned long get_current_tick(void)
 {
-	return get_timer_masked() - base;
+	struct s3c_timer *timer = s3c_get_base_timer();
+	unsigned long now = readl(&timer->tcnto4);
+	unsigned long count_value = readl(&timer->tcntb4);
+
+	if (gd->lastinc >= now)
+		gd->tbl += gd->lastinc - now;
+	else
+		gd->tbl += gd->lastinc + count_value - now;
+
+	gd->lastinc = now;
+
+	return gd->tbl;
 }
 
-void __udelay(unsigned long usec)
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
 {
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = (usec + 9) / 10;
-	tmp = get_ticks() + tmo;	/* get current timestamp */
+	return get_timer(0);
+}
 
-	while (get_ticks() < tmp)/* loop till event */
-		 /*NOP*/;
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
 }

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index 3199bf1..b85b641 100644
@@ -39,7 +39,7 @@
 #define MAX_CHIPS	2
 static int nand_cs[MAX_CHIPS] = {0, 1};
 
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
 #define printf(arg...) do {} while (0)
 #endif
 

@@ -285,7 +285,7 @@ int board_nand_init(struct nand_chip *nand)
 	nand->dev_ready		= s3c_nand_device_ready;
 	nand->select_chip	= s3c_nand_select_chip;
 	nand->options		= 0;
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
 	nand->read_byte		= nand_read_byte;
 	nand->write_buf		= nand_write_buf;
 	nand->read_buf		= nand_read_buf;

index d85ddeb..c63aef8 100644
@@ -238,11 +238,10 @@
 #define CONFIG_SYS_NAND_YAFFS_WRITE	1  /* support yaffs write		      */
 #define CONFIG_SYS_NAND_BBT_2NDPAGE	1  /* bad-block markers in 1st and 2nd pages  */
 
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_PHY_UBOOT_BASE	/* NUB load-addr      */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST	/* NUB start-addr     */
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(4 * 1024)	/* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(252 * 1024)	/* Size of RAM U-Boot image   */
+/* Offset to RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 * 1024)
+/* Size of RAM U-Boot image   */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(252 * 1024)
 
 /* NAND chip page size		*/
 #define CONFIG_SYS_NAND_PAGE_SIZE	2048

@@ -266,8 +265,6 @@
 				 48, 49, 50, 51, 52, 53, 54, 55, \
 				 56, 57, 58, 59, 60, 61, 62, 63}
 
-/* Boot configuration (define only one of next 3) */
-#define CONFIG_BOOT_NAND
 /* None of these are currently implemented. Left from the original Samsung
  * version for reference
 #define CONFIG_BOOT_NOR

@@ -275,7 +272,15 @@
 #define CONFIG_BOOT_ONENAND
 */
 
-#define CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE	0x0
+#define CONFIG_SPL_STACK  CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
 #define CONFIG_NAND_S3C64XX
 /* Unimplemented or unsupported. See comment above.
 #define CONFIG_ONENAND

index c63aef8..6ea587d 100644
@@ -54,7 +54,7 @@
 /* input clock of PLL: SMDK6400 has 12MHz input clock */
 #define CONFIG_SYS_CLK_FREQ	12000000
 
-#if !defined(CONFIG_NAND_U_BOOT) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
+#if !defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
 #define CONFIG_ENABLE_MMU
 #endif
 

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index b884763..d2ee9d2 100644
@@ -471,14 +471,6 @@
  */
 #define ELFIN_SROM_BASE		0x70000000
 
-#define SROM_BW_REG	__REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG	__REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG	__REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG	__REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG	__REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG	__REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG	__REG(ELFIN_SROM_BASE + 0x18)
-
 /*
  * SDRAM Controller
  */

@@ -722,6 +714,11 @@ static inline unsigned long s3c64xx_get_base_timer(void)
 {
 	return ELFIN_TIMER_BASE;
 }
+
+static inline unsigned long s3c64xx_get_base_sromc(void)
+{
+	return ELFIN_SROM_BASE;
+}
 #endif
 
 #endif /*__S3C6400_H__*/

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index c40d1f9..be0e18b 100644
@@ -30,6 +30,7 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <asm/arch/sromc.h>
 #include <asm/arch/s3c6400.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -53,25 +54,40 @@ static inline void delay(unsigned long loops)
 /*
  * Miscellaneous platform dependent initialisations
  */
-
+#ifdef CONFIG_CS8900
 static void cs8900_pre_init(void)
 {
-	SROM_BW_REG &= ~(0xf << 4);
-	SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
-	SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
-			(CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
-			(CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
+	u32 smc_bw_conf, smc_bc_conf;
+
+	/* Ethernet needs bus width of 16 bits */
+	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
+			| SROMC_WAIT_ENABLE(CONFIG_ENV_SROM_BANK)
+			| SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
+	smc_bc_conf = SROMC_BC_TACS(CS8900_Tacs)
+			| SROMC_BC_TCOS(CS8900_Tcos)
+			| SROMC_BC_TACC(CS8900_Tacc)
+			| SROMC_BC_TCOH(CS8900_Tcoh)
+			| SROMC_BC_TAH(CS8900_Tah)
+			| SROMC_BC_TACP(CS8900_Tacp)
+			| SROMC_BC_PMC(CS8900_PMC);
+
+	/* Select and configure the SROMC bank */
+	s3c64xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+
+}
+#else
+#define cs8900_pre_init() do {} while (0)
+#endif
+
+static void norflash_srom_init(void)
+{
+	u32 smc_bw_conf, smc_bc_conf;
 }
 
 int board_init(void)
 {
 	cs8900_pre_init();
 
-	/* NOR-flash in SROM0 */
-
-	/* Enable WAIT */
-	SROM_BW_REG |= 4 | 8 | 1;
-
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
 	return 0;

index 6ea587d..b770463 100644
@@ -78,6 +78,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_ENV_SROM_BANK		2 /* Select SROM Bank-2 for Ethernet*/
 #define CONFIG_CS8900			/* we have a CS8900 on-board	*/
 #define CONFIG_CS8900_BASE	  	0x18800300
 #define CONFIG_CS8900_BUS16		/* follow the Linux driver	*/

new file mode 100644
index 0000000..773cffa
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2012
+ * Zhong Hongbo <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/s3c6400.h>
+#include <asm/arch/clock.h>
+
+void reset_cpu(ulong addr)
+{
+	unsigned long sys_id;
+	struct s3c64xx_clock *clk =
+		(struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+	sys_id = readl(&clk->sys_id);
+	sys_id >>= 12;
+	sys_id &= 0xffff;
+	writel(sys_id, &clk->sw_rst);
+}

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index cd295da..74b5951 100644
@@ -25,21 +25,45 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/s3c6400.h>
+#include <asm/arch/clock.h>
 
 int usb_cpu_init(void)
 {
-	OTHERS_REG |= 0x10000;
+	unsigned int val;
+	struct s3c64xx_clock *clk =
+			(struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+	val = readl(&clk->others);
+	val |= 0x10000;
+	writel(val, &clk->others);
+
 	return 0;
 }
 
 int usb_cpu_stop(void)
 {
-	OTHERS_REG &= ~0x10000;
+	unsigned int val;
+	struct s3c64xx_clock *clk =
+			(struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+	val = readl(&clk->others);
+	val &= ~0x10000;
+	writel(val, &clk->others);
+
 	return 0;
 }
 
 void usb_cpu_init_fail(void)
 {
-	OTHERS_REG &= ~0x10000;
+	unsigned int val;
+	struct s3c64xx_clock *clk =
+			(struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+	val = readl(&clk->others);
+	val &= ~0x10000;
+	writel(val, &clk->others);
+
+	return 0;
 }

new file mode 100644
index 0000000..979173c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2012
+ * Zhong Hongbo <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_GPIO_H_
+#define __ASM_ARM_ARCH_GPIO_H_
+
+#define GPACON_OFFSET		0x00
+#define GPADAT_OFFSET		0x04
+#define GPAPUD_OFFSET		0x08
+
+#define GPNCON_OFFSET		0x830
+#define GPNDAT_OFFSET		0x834
+#define GPNPUD_OFFSET		0x838
+
+#define GPKCON0_OFFSET		0x800
+#define GPKCON1_OFFSET		0x804
+#define GPKDAT_OFFSET		0x808
+#define GPKPUD_OFFSET		0x80C
+
+#endif

new file mode 100644
index 0000000..49e3ae4
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2012
+ * Zhong Hongbo <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_INTERRUPT_H_
+#define __ASM_ARM_ARCH_INTERRUPT_H_
+
+#define INTMOD		0x0C	/* VIC INT SELECT (IRQ or FIQ) */
+#define INTUNMSK	0x10	/* VIC INT EN (write 1 to unmask) */
+#define INTMSK		0x14	/* VIC INT EN CLEAR (write 1 to mask) */
+#define INTSUBMSK	0x1C	/* VIC SOFT INT CLEAR */
+#define VECTADDR	0xF00	/* VIC ADDRESS */
+#define EINTPEND_OFFSET	0x924
+#endif

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index 91b1c48..5e97b27 100644
@@ -36,12 +36,17 @@
 #define STARTUP_APLLDIV		0
 
 #define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
-	(STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
+		(STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
 
 #define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | (STARTUP_PDIV << 8) | \
-	STARTUP_SDIV)
+		 STARTUP_SDIV)
 
 #define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | (STARTUP_PDIV << 8) | \
-	STARTUP_SDIV)
+		 STARTUP_SDIV)
 
+#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
+		     STARTUP_PDIV) * STARTUP_MDIV)
+
+#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
+		     (STARTUP_HCLKDIV + 1))
 #endif

new file mode 100644
index 0000000..758e750
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2012
+ * Zhong Hongbo <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef __ASM_ARCH_DMC_H__
+#define __ASM_ARCH_DMC_H__
+
+#ifndef __ASSEMBLY__
+
+struct s3c64xx_dmc {
+	unsigned int	memstat;
+	unsigned int	memcmd;
+	unsigned int	directcmd;
+	unsigned int	memcfg;
+	unsigned int	refresh;
+	unsigned int	caslat;
+	unsigned int	t_dqss;
+	unsigned int	t_mrd;
+	unsigned int	t_ras;
+	unsigned int	t_rc;
+	unsigned int	t_rcd;
+	unsigned int	t_rfc;
+	unsigned int	t_rp;
+	unsigned int	t_rrd;
+	unsigned int	t_wr;
+	unsigned int	t_wtr;
+	unsigned int	t_xp;
+	unsigned int	t_xsr;
+	unsigned int	t_esr;
+	unsigned int	memcfg2;
+#if defined(CONFIG_S3C6410)
+	unsigned int	memcfg3;
+	unsigned char	res1[0xac];
+#else
+	unsigned char	res1[0xb0];
+#endif
+	unsigned int	id_0_cfg[16];
+	unsigned char	res2[0xc0];
+	unsigned int	chip_0_cfg;
+	unsigned int	chip_1_cfg;
+	unsigned char	res3[0xf8];
+	unsigned int	user_status;
+	unsigned int	user_config;
+};
+#endif
+#endif

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index fff2c68..534901a 100644
@@ -27,7 +27,7 @@
 #include <errno.h>
 #include <pwm.h>
 #include <asm/io.h>
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/pwm.h>
 
 int pwm_enable(int pwm_id)

index 773cffa..03cb306 100644
@@ -23,7 +23,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 
 void reset_cpu(ulong addr)

index 05b44b9..5e68090 100644
@@ -32,7 +32,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 
 #define APLL 0

index f1b2b34..92fb7af 100644
@@ -25,7 +25,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/sromc.h>
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 /*
  * s3c64xx_config_sromc() - select the proper SROMC Bank and configure the
  * band width control and bank control registers

index 47d7731..eebd0c0 100644
@@ -25,7 +25,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/pwm.h>
 #include <pwm.h>
 

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index 776536c..4d5deeb 100644
@@ -24,7 +24,7 @@
 #include <config.h>
 #include <asm/io.h>
 #include <asm/arch/dmc.h>
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 #include "setup.h"
 
 void memory_timing_parameter(struct s3c64xx_dmc *dmc)

index be0e18b..3464b1f 100644
@@ -31,7 +31,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/arch/sromc.h>
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

index b85b641..44a6d79 100644
@@ -30,7 +30,7 @@
 #include <nand.h>
 #include <linux/mtd/nand.h>
 
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/nand.h>
 
 #include <asm/io.h>

index e411085..5559441 100644
@@ -23,7 +23,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;

index 74b5951..c193e81 100644
@@ -26,7 +26,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/s3c6400.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 
 int usb_cpu_init(void)

index b770463..e005be1 100644
@@ -108,9 +108,6 @@
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_NAND
-#if defined(CONFIG_BOOT_ONENAND)
-#define CONFIG_CMD_ONENAND
-#endif
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT

@@ -266,13 +263,6 @@
 				 48, 49, 50, 51, 52, 53, 54, 55, \
 				 56, 57, 58, 59, 60, 61, 62, 63}
 
-/* None of these are currently implemented. Left from the original Samsung
- * version for reference
-#define CONFIG_BOOT_NOR
-#define CONFIG_BOOT_MOVINAND
-#define CONFIG_BOOT_ONENAND
-*/
-
 #define CONFIG_SPL
 #define CONFIG_SPL_NAND
 #define CONFIG_SPL_NAND_SIMPLE

@@ -283,11 +273,6 @@
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
 #define CONFIG_NAND_S3C64XX
-/* Unimplemented or unsupported. See comment above.
-#define CONFIG_ONENAND
-#define CONFIG_MOVINAND
-*/
-
 /* Settings as above boot configuration */
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_BOOTARGS		"console=ttySAC,115200"