apf27: add support of armadeus apf27

Add some missing constant (chip select, ...), and
a file mxc_nand.h with the NFC constant.

Signed-off-by Philippe Reynes <[email protected]>

Signed-off-by Eric Jarrige <[email protected]>

---

 arch/arm/cpu/arm926ejs/mx27/asm-offsets.c |   34 ++++++++++++
 arch/arm/include/asm/arch-mx27/imx-regs.h |   11 ++++-
 arch/arm/include/asm/arch-mx27/mxc_nand.h |   83 +++++++++++++++++++++++++++++
 3 files changed, 127 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-mx27/mxc_nand.h

arch/arm/cpu/arm926ejs/mx27/asm-offsets.c +34 -0

index f3a8d7b..b95c58c 100644
@@ -34,6 +34,7 @@ int main(void)
 	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
 	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
 	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
+	DEFINE(CCSR, IMX_PLL_BASE + offsetof(struct pll_regs, ccsr));
 
 	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
 	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));

@@ -41,5 +42,38 @@ int main(void)
 	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
 	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
 
+	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
+	       offsetof(struct system_control_regs, gpcr));
+	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
+	       offsetof(struct system_control_regs, fmcr));
+	DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE +
+	       offsetof(struct system_control_regs, dscr2));
+	DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE +
+	       offsetof(struct system_control_regs, dscr3));
+	DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE +
+	       offsetof(struct system_control_regs, dscr7));
+	DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE +
+	       offsetof(struct system_control_regs, dscr10));
+
+	DEFINE(CS0U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0u));
+	DEFINE(CS0L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0l));
+	DEFINE(CS0A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0a));
+	DEFINE(CS1U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1u));
+	DEFINE(CS1L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1l));
+	DEFINE(CS1A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1a));
+	DEFINE(CS2U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2u));
+	DEFINE(CS2L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2l));
+	DEFINE(CS2A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2a));
+	DEFINE(CS3U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3u));
+	DEFINE(CS3L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3l));
+	DEFINE(CS3A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3a));
+	DEFINE(CS4U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4u));
+	DEFINE(CS4L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4l));
+	DEFINE(CS4A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4a));
+	DEFINE(CS5U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5u));
+	DEFINE(CS5L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5l));
+	DEFINE(CS5A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5a));
+	DEFINE(EIM,  IMX_WEIM_BASE + offsetof(struct weim_regs, eim));
+
 	return 0;
 }

arch/arm/include/asm/arch-mx27/imx-regs.h +0 -0

index 2f6c823..d3a14e1 100644

arch/arm/include/asm/arch-mx27/imx-regs.h +9 -0

 struct fuse_bank0_regs {

@@ -511,4 +511,13 @@ struct fuse_bank0_regs {
 #define IIM_ERR_SNSE	(1 << 2)
 #define IIM_ERR_PARITYE	(1 << 1)
 
+/*
+ * Memory areas of the NFC
+ */
+#define IMX_NFC_BASE                    (0xD8000000)
+#define IMX_NFC_MAIN_AREA0              (0xD8000000)
+#define IMX_NFC_MAIN_AREA1              (0xD8000200)
+#define IMX_NFC_SPARE_AREA0             (0xD8000800)
+#define IMX_NFC_REGS                    (0xD8000E00)
+
 #endif				/* _IMX_REGS_H */

arch/arm/include/asm/arch-mx27/mxc_nand.h new file +45 -0

new file mode 100644
index 0000000..564419e
@@ -0,0 +1,83 @@
+/*
+ * (c) 2012 Philippe Reynes <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MXC_NAND_H
+#define __MXC_NAND_H
+
+/*
+ * NFC registers address offset
+ */
+#define NFC_OFFSET_BUFSIZE             (0x00) /* Internal SRAM Size */
+#define NFC_OFFSET_BLCK_ADD_LOCK       (0x02) /* NAND Flash Block Address for
+						 Lock Check */
+#define NFC_OFFSET_BUF_ADDR            (0x04) /* Buffer Number for Page Data
+						 Transfer To/From Flash Mem */
+#define NFC_OFFSET_FLASH_ADDR          (0x06) /* NAND Flash Address */
+#define NFC_OFFSET_FLASH_CMD           (0x08) /* NAND Flash Command */
+#define NFC_OFFSET_CONFIG              (0x0A) /* NFC Internal Buffer Lock
+						 Control */
+#define NFC_OFFSET_ECC_STATUS_RESULT   (0x0C) /* Controller Status/Result of
+						 Flash Operation */
+#define NFC_OFFSET_ECC_RSLT_MAIN_AREA  (0x0E) /* ECC Error Position of Main
+						 Area Data Error */
+#define NFC_OFFSET_ECC_RSLT_SPARE_AREA (0x10) /* ECC Error Position of Spare
+						 Area Data Error */
+#define NFC_OFFSET_WRPROT              (0x12) /* Nand Flash Write Protection */
+#define NFC_OFFSET_UNLOCKSTART_BLKADDR (0x14) /* Start Address for Write

Signed-off-by Philippe Reynes <[email protected]>

Signed-off-by Eric Jarrige <[email protected]>

Signed-off-by Nicolas Colombain <[email protected]>

---
 MAINTAINERS                         |    5 +
 board/armadeus/apf27/Makefile       |   48 +++
 board/armadeus/apf27/apf27.c        |  347 ++++++++++++++++++++++
 board/armadeus/apf27/apf27.h        |  477 +++++++++++++++++++++++++++++++
 board/armadeus/apf27/start.S        |  538 +++++++++++++++++++++++++++++++++++
 board/armadeus/apf27/u-boot-spl.lds |   86 ++++++
 boards.cfg                          |    1 +
 include/configs/apf27.h             |  445 +++++++++++++++++++++++++++++
 8 files changed, 1947 insertions(+), 0 deletions(-)
 create mode 100644 board/armadeus/apf27/Makefile
 create mode 100644 board/armadeus/apf27/apf27.c
 create mode 100644 board/armadeus/apf27/apf27.h
 create mode 100644 board/armadeus/apf27/start.S
 create mode 100644 board/armadeus/apf27/u-boot-spl.lds
 create mode 100644 include/configs/apf27.h

board/armadeus/apf27/apf27.c new file +13 -0

+/*
+ * Fuse bank 1 row 8 is "reserved for future use" and therefore available for
+ * customer use. The APF27 board uses this fuse to store the board revision:
+ * 0: initial board revision
+ * 1: first revision - Presence of the second RAM chip on the board is blown in
+ *     fuse bank 1 row 9  bit 0 - No hardware change
+ * N: to be defined
+ */
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+
+	return readl(&iim->bank[1].fuse_regs[8]);

+++ b/board/armadeus/apf27/apf27.h

board/armadeus/apf27/apf27.h new file +8 -0

@@ -0,0 +1,477 @@
+#ifndef __APF27_H
+#define __APF27_H
+
+/* FPGA program pin configuration */
+#define ACFG_FPGA_PWR	(GPIO_PORTF | 19)	/* FPGA prog pin  */
+#define ACFG_FPGA_PRG	(GPIO_PORTF | 11)	/* FPGA prog pin  */
+#define ACFG_FPGA_CLK	(GPIO_PORTF | 15)	/* FPGA clk pin   */
+#define ACFG_FPGA_RDATA	0xD6000000		/* FPGA data addr  */

board/armadeus/apf27/apf27.h new file +5 -0

+#ifndef CONFIG_MX27_CLK26
+#if (CONFIG_MX27_CLK32 == 32000)
+#define ACFG_MPCTL0_VAL		0x00211803	/* 398.998 MHz */
+#define ACFG_MPCTL1_VAL		0
+#define CONFIG_MPLL_FREQ	399

board/armadeus/apf27/apf27.h new file +126 -0

+
+/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
+#define CONFIG_ARM_FREQ		399	/* up to 400 MHz */
+
+/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
+#define CONFIG_HCLK_FREQ	133	/* (ACFG_CLK_FREQ/2) */
+
+#define CONFIG_PERIF1_FREQ	16	/* 16.625 MHz UART, GPT, PWM*/
+#define CONFIG_PERIF2_FREQ	33	/* 33.25 MHz CSPI and SDHC */
+#define CONFIG_PERIF3_FREQ	33	/* 33.25 MHz LCD*/
+#define CONFIG_PERIF4_FREQ	33	/* 33.25 MHz CSI*/
+#define CONFIG_SSI1_FREQ	66	/* 66.50 MHz SSI1*/
+#define CONFIG_SSI2_FREQ	66	/* 66.50 MHz SSI2*/
+#define CONFIG_MSHC_FREQ	66	/* 66.50 MHz MSHC*/
+#define CONFIG_H264_FREQ	66	/* 66.50 MHz H264*/
+#define CONFIG_CLK0_DIV      3  /* Divide CLK0 by 4 */
+#define CONFIG_CLK0_EN       1  /* CLK0 enabled */
+
+/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
+#define CONFIG_NFC_FREQ		44	/* NFC Clock up to 44 MHz wh 133MHz*/
+
+/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
+#define CONFIG_USB_FREQ		60	/* 60 MHz */
+
+/*
+ * SDRAM
+ */
+#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
+/* micron 64MB */
+#define ACFG_SDRAM_NUM_COL		9  /* 8, 9, 10 or 11
+						      column address bits */
+#define ACFG_SDRAM_NUM_ROW		13 /* 11, 12 or 13
+						      row address bits */
+#define ACFG_SDRAM_REFRESH		3  /* 0=OFF 1=2048
+						      2=4096 3=8192 refresh */
+#define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
+						      down delay */
+#define ACFG_SDRAM_W2R_DELAY		1  /* write to read
+						      cycle delay > 0 */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY	18 /* ns */
+#define ACFG_SDRAM_TMRD_DELAY		2  /* Load mode register
+						      cycle delay 1..4 */
+#define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck;
+						      SDRAM: 0=1ck 1=2ck*/
+#define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE
+						      delay */
+#define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE
+						      delay */
+#define ACFG_SDRAM_RCD_DELAY		18 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY		70 /* ns Row cycle delay (tRFC
+						      refresh to command) */
+#define ACFG_SDRAM_CLOCK_CYCLE_CL_1	0 /* ns clock cycle time
+						     estimated fo CL=1
+						     0=force 3 for lpddr */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR	0  /* 0=full 1=half 2=quater
+						      3=Eighth 4=Sixteenth */
+#define ACFG_SDRAM_DRIVE_STRENGH		0  /* 0=Full-strength 1=half
+						      2=quater 3=Eighth */
+#define ACFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS		0  /* 1= single access;
+						      0 = Burst mode */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 128)
+/* micron 128MB */
+#define ACFG_SDRAM_NUM_COL		9  /* 8, 9, 10 or 11
+						      column address bits */
+#define ACFG_SDRAM_NUM_ROW		14 /* 11, 12 or 13
+						      row address bits */
+#define ACFG_SDRAM_REFRESH		3  /* 0=OFF 1=2048
+						      2=4096 3=8192 refresh */
+#define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
+						      down delay */
+#define ACFG_SDRAM_W2R_DELAY		1  /* write to read
+						      cycle delay > 0 */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY	18 /* ns */
+#define ACFG_SDRAM_TMRD_DELAY		2  /* Load mode register
+						      cycle delay 1..4 */
+#define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck;
+						      SDRAM: 0=1ck 1=2ck*/
+#define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE
+						      delay */
+#define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE
+						      delay */
+#define ACFG_SDRAM_RCD_DELAY		18 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY		70 /* ns Row cycle delay (tRFC
+						      refresh to command)*/
+#define ACFG_SDRAM_CLOCK_CYCLE_CL_1	0 /* ns clock cycle time
+						     estimated fo CL=1
+						     0=force 3 for lpddr*/
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR	0  /* 0=full 1=half 2=quater
+						      3=Eighth 4=Sixteenth */
+#define ACFG_SDRAM_DRIVE_STRENGH		0  /* 0=Full-strength 1=half
+						      2=quater 3=Eighth */
+#define ACFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS		0  /* 1= single access;
+						      0 = Burst mode */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 256)
+/* micron 256MB */
+#define ACFG_SDRAM_NUM_COL		10  /* 8, 9, 10 or 11
+						       column address bits */
+#define ACFG_SDRAM_NUM_ROW		14 /* 11, 12 or 13
+						      row address bits */
+#define ACFG_SDRAM_REFRESH		3  /* 0=OFF 1=2048
+						      2=4096 3=8192 refresh */
+#define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
+						      down delay */
+#define ACFG_SDRAM_W2R_DELAY		1  /* write to read cycle
+						      delay > 0 */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY	18 /* ns */
+#define ACFG_SDRAM_TMRD_DELAY		2  /* Load mode register
+						      cycle delay 1..4 */
+#define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck;
+						      SDRAM: 0=1ck 1=2ck */
+#define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE
+						      delay */
+#define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE
+						      delay */
+#define ACFG_SDRAM_RCD_DELAY		18 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY		70 /* ns Row cycle delay (tRFC
+						      refresh to command) */
+#define ACFG_SDRAM_CLOCK_CYCLE_CL_1	0 /* ns clock cycle time
+						     estimated fo CL=1
+						     0=force 3 for lpddr */

board/armadeus/apf27/apf27.h new file +8 -0

+/*
+ * Default configuration for GPIOs and peripherals
+ */
+#ifndef ACFG_APF27_CUSTOM
+#define ACFG_DDIR_A_VAL		0x00000000
+#define ACFG_OCR1_A_VAL		0x00000000
+#define ACFG_OCR2_A_VAL		0x00000000
+#define ACFG_ICFA1_A_VAL		0xFFFFFFFF

board/armadeus/apf27/start.S new file +92 -0

new file mode 100644
index 0000000..05d5de0
@@ -0,0 +1,538 @@
+/*
+ *  IMX27 NAND Flash SPL (Secondary Program Loader)
+ *
+ *  Copyright (c) 2008  Armadeus Project / eja
+ *
+ *  Based on Freescale NAND SPL
+ *
+ *  Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+ *  Copyright (c) 2008-2012 Eric Jarrige <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <generated/asm-offsets.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/mxc_nand.h>
+#include <asm/arch/imx-regs.h>
+#include "apf27.h"
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0		0
+#define NAND_CMD_READ1		1
+#define NAND_CMD_PAGEPROG	0x10
+#define NAND_CMD_READOOB	0x50
+#define NAND_CMD_ERASE1		0x60
+#define NAND_CMD_STATUS		0x70
+#define NAND_CMD_STATUS_MULTI	0x71
+#define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_READID		0x90
+#define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_RESET		0xff
+
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART	0x30
+#define NAND_CMD_CACHEDPROG	0x15
+
+/* Status bits */
+#define NAND_STATUS_FAIL	0x01
+#define NAND_STATUS_FAIL_N1	0x02
+#define NAND_STATUS_TRUE_READY	0x20
+#define NAND_STATUS_READY	0x40
+#define NAND_STATUS_WP		0x80
+
+	.macro nand_boot
+
+#ifdef CONFIG_BOOT_TRACE_REG
+/*
+ * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the following
+ * 2 command after SDRAM init
+ */
+
+/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/
+#define BACKUP_TRACE()			\
+	ldr r4, =CONFIG_BOOT_TRACE_REG;	\
+	ldr r3, [r4];			\
+	str r3, [r4, #0x04];
+
+/* Save a state of boot at CONFIG_BOOT_TRACE_REG */
+#define BOOT_TRACE(val)		\
+	ldr r4, =CONFIG_BOOT_TRACE_REG;	\
+	ldr r3, =val;			\
+	str r3, [r4];
+#else
+#define BACKUP_TRACE()
+#define BOOT_TRACE(val)
+#endif
+
+nand_boot_setup:
+
+	/* Copy SPL image from flash to SDRAM first */
+	BOOT_TRACE(1)

board/armadeus/apf27/start.S new file +38 -0

+.globl _start
+_start:
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * invalidate I/D cache/TLB and drain write buffer
+	 */
+	mov r0, #0
+	mcr p15, 0, r0, c7, c7, 0	/* invalidate I cache and D cache */
+	mcr p15, 0, r0, c8, c7, 0	/* invalidate TLBs */
+	mcr p15, 0, r0, c7, c10, 4   /* Drain the write buffer */
+

board/armadeus/apf27/start.S new file +6 -0

+/*
+ * SPL
+ */
+/* Copy SPL+U-Boot here	     */
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_TEXT_BASE - 0x800)
+/* Size is the partion size  */