Add support for SAMSUNG Exynos4 SoCs and ORIGEN_QUAD board
Subsystems (4)
cover Add support for SAMSUNG Exynos4 SoCs and ORIGEN_QUAD board
This patch series adds support for Exynos4 SoCs and ORIGEN_QUAD board. Exynos4212/4412 are SAMSUNG's ARM Cortex-A15 boased SoCs and Exynos4 series SoCs. ORIGEN_QUAD board is based on Exynos4212.
[PATCH 1/4] EXYNOS4: Add pinmux support for UART [PATCH 2/4] EXYNOS4: Add pinmux support for I2C [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs [PATCH 4/4] EXYNOS4: Add ORIGEN_QUAD board support
Makefile | 2 +- arch/arm/cpu/armv7/exynos/clock.c | 7 +- arch/arm/cpu/armv7/exynos/pinmux.c | 92 +++++++++ arch/arm/include/asm/arch-exynos/clock.h | 240 +++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 1 + board/samsung/origen_quad/Makefile | 59 ++++++ board/samsung/origen_quad/boot.c | 72 +++++++ board/samsung/origen_quad/clock.c | 103 ++++++++++ board/samsung/origen_quad/dmc.c | 163 ++++++++++++++++ board/samsung/origen_quad/lowlevel_init.S | 151 +++++++++++++++ board/samsung/origen_quad/origen_quad.c | 163 ++++++++++++++++ board/samsung/origen_quad/setup.h | 300 +++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/origen_quad.h | 179 +++++++++++++++++ tools/Makefile | 2 + 15 files changed, 1533 insertions(+), 2 deletions(-) create mode 100644 board/samsung/origen_quad/Makefile create mode 100644 board/samsung/origen_quad/boot.c create mode 100644 board/samsung/origen_quad/clock.c create mode 100644 board/samsung/origen_quad/dmc.c create mode 100644 board/samsung/origen_quad/lowlevel_init.S create mode 100644 board/samsung/origen_quad/origen_quad.c create mode 100644 board/samsung/origen_quad/setup.h create mode 100644 include/configs/origen_quad.h
PATCH 1/4 EXYNOS4: Add pinmux support for UART
From: Jeong-Hyeon Kim <[email protected]>
This patch adds pinmux support for UART channels
Signed-off-by Jeong-Hyeon Kim <[email protected]>
--- arch/arm/cpu/armv7/exynos/pinmux.c | 41 ++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+)
arch/arm/cpu/armv7/exynos/pinmux.c +41 -0
@@ -366,6 +366,41 @@ static int exynos4_mmc_config(int peripheral, int flags)return 0 ; } +static void exynos4_uart_config (int peripheral) +{ +struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1 (); +struct s5p_gpio_bank *bank; +int i, start, count; + +switch (peripheral) { +case PERIPH_ID_UART0 : + bank = &gpio1->a0; + start =0 ; + count =4 ; +break ; +case PERIPH_ID_UART1 : + bank = &gpio1->a0; + start =4 ; + count =4 ; +break ; +case PERIPH_ID_UART2 : + bank = &gpio1->a1; + start =0 ; + count =4 ; +break ; +case PERIPH_ID_UART3 : + bank = &gpio1->a1; + start =4 ; + count =2 ; +break ; + } +for (i = start; i < start + count; i++) { +s5p_gpio_set_pull (bank, i,GPIO_PULL_NONE ); +s5p_gpio_cfg_pin (bank, i,GPIO_FUNC (0x2 )); + } +} +static int exynos4_pinmux_config (int peripheral,int flags) {switch (peripheral) {
@@ -377,6 +412,12 @@ static int exynos4_pinmux_config(int peripheral, int flags)case PERIPH_ID_SDMMC4 :printf ("SDMMC device %d not implemented\n" , peripheral);return -1 ; +case PERIPH_ID_UART0 : +case PERIPH_ID_UART1 : +case PERIPH_ID_UART2 : +case PERIPH_ID_UART3 : +exynos4_uart_config (peripheral); +break ;default :debug ("%s: invalid peripheral %d" , __func__, peripheral);return -1 ;
Signature · 1 line
1.7.9.5
PATCH 2/4 EXYNOS4: Add pinmux support for I2C
In reply to Jeong Hyeon KimFrom: Jeong-Hyeon Kim <[email protected]>
This patch adds pinmux support for I2C channels
Signed-off-by Jeong-Hyeon Kim <[email protected]>
--- arch/arm/cpu/armv7/exynos/pinmux.c | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
arch/arm/cpu/armv7/exynos/pinmux.c +51 -0
@@ -401,6 +401,48 @@ static void exynos4_uart_config(int peripheral) } } +static void exynos4_i2c_config (int peripheral,int flags) +{ + +struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1 (); + +switch (peripheral) { +case PERIPH_ID_I2C0 : +s5p_gpio_cfg_pin (&gpio1->d1,0 ,GPIO_FUNC (0x2 )); +s5p_gpio_cfg_pin (&gpio1->d1,1 ,GPIO_FUNC (0x2 )); +break ; +case PERIPH_ID_I2C1 : +s5p_gpio_cfg_pin (&gpio1->d1,2 ,GPIO_FUNC (0x2 )); +s5p_gpio_cfg_pin (&gpio1->d1,3 ,GPIO_FUNC (0x2 )); +break ; +case PERIPH_ID_I2C2 : +s5p_gpio_cfg_pin (&gpio1->a0,6 ,GPIO_FUNC (0x3 )); +s5p_gpio_cfg_pin (&gpio1->a0,7 ,GPIO_FUNC (0x3 )); +break ; +case PERIPH_ID_I2C3 : +s5p_gpio_cfg_pin (&gpio1->a1,2 ,GPIO_FUNC (0x3 )); +s5p_gpio_cfg_pin (&gpio1->a1,3 ,GPIO_FUNC (0x3 )); +break ; +case PERIPH_ID_I2C4 : +s5p_gpio_cfg_pin (&gpio1->b,0 ,GPIO_FUNC (0x3 )); +s5p_gpio_cfg_pin (&gpio1->b,1 ,GPIO_FUNC (0x3 )); +break ; +case PERIPH_ID_I2C5 : +s5p_gpio_cfg_pin (&gpio1->b,2 ,GPIO_FUNC (0x3 )); +s5p_gpio_cfg_pin (&gpio1->b,3 ,GPIO_FUNC (0x3 )); +break ; +case PERIPH_ID_I2C6 : +s5p_gpio_cfg_pin (&gpio1->c1,3 ,GPIO_FUNC (0x4 )); +s5p_gpio_cfg_pin (&gpio1->c1,4 ,GPIO_FUNC (0x4 )); +break ; +case PERIPH_ID_I2C7 : +s5p_gpio_cfg_pin (&gpio1->d0,2 ,GPIO_FUNC (0x3 )); +s5p_gpio_cfg_pin (&gpio1->d0,3 ,GPIO_FUNC (0x3 )); +break ; + } +} +static int exynos4_pinmux_config (int peripheral,int flags) {switch (peripheral) {
@@ -417,6 +459,15 @@ static int exynos4_pinmux_config(int peripheral, int flags)case PERIPH_ID_UART2 :case PERIPH_ID_UART3 :exynos4_uart_config (peripheral); +case PERIPH_ID_I2C0 : +case PERIPH_ID_I2C1 : +case PERIPH_ID_I2C2 : +case PERIPH_ID_I2C3 : +case PERIPH_ID_I2C4 : +case PERIPH_ID_I2C5 : +case PERIPH_ID_I2C6 : +case PERIPH_ID_I2C7 : +exynos4_i2c_config (peripheral, flags);break ;default :debug ("%s: invalid peripheral %d" , __func__, peripheral);
Signature · 1 line
1.7.9.5
PATCH 2/4 EXYNOS4: Add pinmux support for I2C
Hello Jeong,
Quoted 8 lines · Jeong Hyeon Kim
From: Jeong-Hyeon Kim<[email protected]>
This patch adds pinmux support for I2C channels
Signed-off-by Jeong-Hyeon Kim<[email protected]>--- arch/arm/cpu/armv7/exynos/pinmux.c | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
similiar patch is applied to u-boot-i2c, see:
http://git.denx.de/?p=u-boot/u-boot-i2c.git;a=commitdiff;h=4d4628dcaa51b501bec148a9c5c55df3920350dc
and pull request is pending. Can you check, if the above patch fits your needs?
Thanks!
bye,
Heiko
Signature · 2 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
PATCH 2/4 EXYNOS4: Add pinmux support for I2C
Dear Heiko,
Thanks for your concern.
I didn't know the patch.
It can be replaced my patch.
Thank you,
JHKIM
2012? 12? 12? 17:16, Heiko Schocher ? ?:
Quoted 25 lines
Hello Jeong,
Quoted 9 lines · Jeong Hyeon Kim
From: Jeong-Hyeon Kim<[email protected]>
This patch adds pinmux support for I2C channels
Signed-off-by Jeong-Hyeon Kim<[email protected]>---
arch/arm/cpu/armv7/exynos/pinmux.c| 51
++++++++++++++++++++++++++++++++++++1 file changed, 51 insertions(+)similiar patch is applied to u-boot-i2c, see:
http://git.denx.de/?p=u-boot/u-boot-i2c.git;a=commitdiff;h=4d4628dcaa51b501bec148a9c5c55df3920350dc
and pull request is pending. Can you check, if the above patch fits your needs?
Thanks!
bye,
Heiko
PATCH 3/4 EXYNOS4: Add support for Exynos4x12 SoCs
In reply to Jeong Hyeon KimFrom: Jeong-Hyeon Kim <[email protected]>
This patch adds the support for Exynos4212/4412.
Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar. Address of a few registers are different in CMU part like MPLL.
Signed-off-by Jeong-Hyeon Kim <[email protected]>
--- arch/arm/cpu/armv7/exynos/clock.c | 7 +- arch/arm/include/asm/arch-exynos/clock.h | 240 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 1 + 3 files changed, 247 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/exynos/clock.c +6 -1
@@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg) r =readl (&clk->apll_con0);break ;case MPLL : - r =readl (&clk->mpll_con0); +if (proid_is_exynos4412 ()) { +struct exynos4412_clock *clk4412 = + (struct exynos4412_clock *)samsung_get_base_clock (); + r =readl (&clk4412->mpll_con0); + }else + r =readl (&clk->mpll_con0);break ;case EPLL : r =readl (&clk->epll_con0);
arch/arm/include/asm/arch-exynos/clock.h +240 -0
246 lines not on this page · raw message
arch/arm/include/asm/arch-exynos/cpu.h +1 -0
@@ -152,6 +152,7 @@ static inline int proid_is_##type(void) \ } IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250)#define SAMSUNG_BASE (device, base) \
Signature · 1 line
1.7.9.5
PATCH 3/4 EXYNOS4: Add support for Exynos4x12 SoCs
Dear Kim,
Quoted 7 lines · Jeong Hyeon Kim
From: Jeong-Hyeon Kim <[email protected]>
This patch adds the support for Exynos4212/4412.
Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar. Address of a few registers are different in CMU part like MPLL.
Quoted 7 lines
Signed-off-by Jeong-Hyeon Kim <[email protected]>--- arch/arm/cpu/armv7/exynos/clock.c | 7 +- arch/arm/include/asm/arch-exynos/clock.h | 240 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 1 + 3 files changed, 247 insertions(+), 1 deletion(-)
As i discussed with you these changes has been already posted.
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/148856
Kindly use them and resend yours patches.
arch/arm/cpu/armv7/exynos/clock.c
Quoted 4 lines
arch/arm/cpu/armv7/exynos/clock.c +0
-0
Please have a look patch at the link.
[PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
Quoted 280 lines
arch/arm/cpu/armv7/exynos/clock.c +6
-1@@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg) r =readl (&clk->apll_con0);break ;case MPLL : - r =readl (&clk->mpll_con0); +if (proid_is_exynos4412 ()) { +struct exynos4412_clock *clk4412 = + (struct exynos4412_clock *)samsung_get_base_clock (); + r =readl (&clk4412->mpll_con0); + }else + r =readl (&clk->mpll_con0);break ;case EPLL : r =readl (&clk->epll_con0);arch/arm/include/asm/arch-exynos/clock.h +240
-0@@ -251,6 +251,246 @@ struct exynos4_clock {unsigned int div_iem_l1; }; +struct exynos4412_clock { +unsigned char res1[0x4200 ]; +unsigned int src_leftbus; +unsigned char res2[0x1fc ]; +unsigned int mux_stat_leftbus; +unsigned char res3[0xfc ]; +unsigned int div_leftbus; +unsigned char res4[0xfc ]; +unsigned int div_stat_leftbus; +unsigned char res5[0x1fc ]; +unsigned int gate_ip_leftbus; +unsigned char res6[0x12c ]; +unsigned int gate_ip_image; +unsigned char res7[0xcc ]; +unsigned int clkout_cmu_leftbus; +unsigned int clkout_cmu_leftbus_div_stat; +unsigned char res8[0x37f8 ]; +unsigned int src_rightbus; +unsigned char res9[0x1fc ]; +unsigned int mux_stat_rightbus; +unsigned char res10[0xfc ]; +unsigned int div_rightbus; +unsigned char res11[0xfc ]; +unsigned int div_stat_rightbus; +unsigned char res12[0x1fc ]; +unsigned int gate_ip_rightbus; +unsigned char res13[0x15c ]; +unsigned int gate_ip_perir; +unsigned char res14[0x9c ]; +unsigned int clkout_cmu_rightbus; +unsigned int clkout_cmu_rightbus_div_stat; +unsigned char res15[0x3608 ]; +unsigned int epll_lock; +unsigned char res16[0xc ]; +unsigned int vpll_lock; +unsigned char res17[0xec ]; +unsigned int epll_con0; +unsigned int epll_con1; +unsigned int epll_con2; +unsigned char res18[0x4 ]; +unsigned int vpll_con0; +unsigned int vpll_con1; +unsigned int vpll_con2; +unsigned char res19[0xe4 ]; +unsigned int src_top0; +unsigned int src_top1; +unsigned char res20[0x8 ]; +unsigned int src_cam0; +unsigned int src_tv; +unsigned int src_mfc; +unsigned int src_g3d; +unsigned char res21[0x4 ]; +unsigned int src_lcd0; +unsigned int src_isp; +unsigned int src_maudio; +unsigned int src_fsys; +unsigned char res22[0xc ]; +unsigned int src_peril0; +unsigned int src_peril1; +unsigned int src_cam1; +unsigned char res23[0xc4 ]; +unsigned int src_mask_cam0; +unsigned int src_mask_tv; +unsigned char res24[0xc ]; +unsigned int src_mask_lcd; +unsigned int src_mask_isp; +unsigned int src_mask_maudio; +unsigned int src_mask_fsys; +unsigned char res25[0xc ]; +unsigned int src_mask_peril0; +unsigned int src_mask_peril1; +unsigned char res26[0xb8 ]; +unsigned int mux_stat_top; +unsigned int mux_stat_top1; +unsigned char res27[0x10 ]; +unsigned int mux_stat_mfc; +unsigned int mux_stat_g3d; +unsigned char res28[0x28 ]; +unsigned int mux_stat_cam1; +unsigned char res29[0xb4 ]; +unsigned int div_top; +unsigned char res30[0xc ]; +unsigned int div_cam0; +unsigned int div_tv; +unsigned int div_mfc; +unsigned int div_g3d; +unsigned char res31[0x4 ]; +unsigned int div_lcd; +unsigned int div_isp; +unsigned int div_maudio; +unsigned int div_fsys0; +unsigned int div_fsys1; +unsigned int div_fsys2; +unsigned int div_fsys3; +unsigned int div_peril0; +unsigned int div_peril1; +unsigned int div_peril2; +unsigned int div_peril3; +unsigned int div_peril4; +unsigned int div_peril5; +unsigned int div_cam1; +unsigned char res32[0x14 ]; +unsigned int div2_ratio; +unsigned char res33[0x8c ]; +unsigned int div_stat_top; +unsigned char res34[0xc ]; +unsigned int div_stat_cam0; +unsigned int div_stat_tv; +unsigned int div_stat_mfc; +unsigned int div_stat_g3d; +unsigned char res35[0x4 ]; +unsigned int div_stat_lcd; +unsigned int div_stat_isp; +unsigned int div_stat_maudio; +unsigned int div_stat_fsys0; +unsigned int div_stat_fsys1; +unsigned int div_stat_fsys2; +unsigned int div_stat_fsys3; +unsigned int div_stat_peril0; +unsigned int div_stat_peril1; +unsigned int div_stat_peril2; +unsigned int div_stat_peril3; +unsigned int div_stat_peril4; +unsigned int div_stat_peril5; +unsigned int div_stat_cam1; +unsigned char res36[0x14 ]; +unsigned int div2_stat; +unsigned char res37[0xc0 ]; +unsigned int gate_bus_fsys1; +unsigned char res38[0x1d8 ]; +unsigned int gate_ip_cam; +unsigned int gate_ip_tv; +unsigned int gate_ip_mfc; +unsigned int gate_ip_g3d; +unsigned char res39[0x4 ]; +unsigned int gate_ip_lcd; +unsigned int gate_ip_isp; +unsigned char res40[0x4 ]; +unsigned int gate_ip_fsys; +unsigned char res41[0x8 ]; +unsigned int gate_ip_gps; +unsigned int gate_ip_peril; +unsigned char res42[0x1c ]; +unsigned int gate_block; +unsigned char res43[0x8c ]; +unsigned int clkout_cmu_top; +unsigned int clkout_cmu_top_div_stat; +unsigned char res44[0x3600 ]; +unsigned int mpll_lock; +unsigned char res45[0xfc ]; +unsigned int mpll_con0; +unsigned int mpll_con1; +unsigned char res46[0xf0 ]; +unsigned int src_dmc; +unsigned char res47[0xfc ]; +unsigned int src_mask_dmc; +unsigned char res48[0xfc ]; +unsigned int mux_stat_dmc; +unsigned char res49[0xfc ]; +unsigned int div_dmc0; +unsigned int div_dmc1; +unsigned char res50[0xf8 ]; +unsigned int div_stat_dmc0; +unsigned int div_stat_dmc1; +unsigned char res51[0x2f8 ]; +unsigned int gate_ip_dmc; +unsigned int gate_ip_dmc1; +unsigned char res52[0xf8 ]; +unsigned int clkout_cmu_dmc; +unsigned int clkout_cmu_dmc_div_stat; +unsigned char res53[0x5f8 ]; +unsigned int dcgidx_map0; +unsigned int dcgidx_map1; +unsigned int dcgidx_map2; +unsigned char res54[0x14 ]; +unsigned int dcgperf_map0; +unsigned int dcgperf_map1; +unsigned char res55[0x18 ]; +unsigned int dvcidx_map; +unsigned char res56[0x1c ]; +unsigned int freq_cpu; +unsigned int freq_dpm; +unsigned char res57[0x18 ]; +unsigned int dvsemclk_en; +unsigned int maxperf; +unsigned char res58[0xc ]; +unsigned int dmc_puause_ctrl; +unsigned int ddrphy_lock_ctrl; +unsigned int c2c_state; +unsigned char res59[0x2f60 ]; +unsigned int apll_lock; +unsigned char res60[0xfc ]; +unsigned int apll_con0; +unsigned int apll_con1; +unsigned char res61[0xf8 ]; +unsigned int src_cpu; +unsigned char res62[0x1fc ]; +unsigned int mux_stat_cpu; +unsigned char res63[0xfc ]; +unsigned int div_cpu0; +unsigned int div_cpu1; +unsigned char res64[0xf8 ]; +unsigned int div_stat_cpu0; +unsigned int div_stat_cpu1; +unsigned char res65[0x2f8 ]; +unsigned int gate_ip_cpu; +unsigned char res66[0xfc ]; +unsigned int clkout_cmu_cpu; +unsigned int clkout_cmu_cpu_div_stat; +unsigned char res67[0x5f8 ]; +unsigned int armclk_stopctrl; +unsigned int atclk_stopctrl; +unsigned char res68[0x18 ]; +unsigned int pwr_ctrl; +unsigned int pwr_ctrl2; +unsigned char res69[0x3d8 ]; +unsigned int l2_status; +unsigned char res70[0xc ]; +unsigned int cpu_status; +unsigned char res71[0xc ]; +unsigned int ptm_status; +unsigned char res72[0x2edc ]; +unsigned int clk_div_isp0; +unsigned int clk_div_isp1; +unsigned char res73[0xf8 ]; +unsigned int clk_div_stat_isp0; +unsigned int clk_div_stat_isp1; +unsigned char res74[0x3f8 ]; +unsigned int gate_ip_isp0; +unsigned int gate_ip_isp1; +unsigned char res75[0x1f8 ]; +unsigned int clkout_cmu_isp; +unsigned int clkout_cmu_isp_stat; +unsigned char res76[0xf8 ]; +unsigned int clkout_cmu_spare0; +unsigned int clkout_cmu_spare1; +unsigned int clkout_cmu_spare2; +unsigned int clkout_cmu_spare3; +}; +struct exynos5_clock {unsigned int apll_lock;unsigned char res1[0xfc ];arch/arm/include/asm/arch-exynos/cpu.h +1
-1@@ -152,6 +152,7 @@ static inline int proid_is_##type(void) \ } IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250)#define SAMSUNG_BASE (device, base) \ --1.7.9.5
Signature · 2 lines
with warm regards, Chander Kashyap
PATCH 3/4 EXYNOS4: Add support for Exynos4x12 SoCs
Quoted 20 lines · Chander Kashyap
Dear Kim,
Quoted 7 lines · Jeong Hyeon Kim
From: Jeong-Hyeon Kim <[email protected]>
This patch adds the support for Exynos4212/4412.
Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar. Address of a few registers are different in CMU part like MPLL.
Quoted 7 lines
Signed-off-by Jeong-Hyeon Kim <[email protected]>--- arch/arm/cpu/armv7/exynos/clock.c | 7 +- arch/arm/include/asm/arch-exynos/clock.h | 240 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 1 + 3 files changed, 247 insertions(+), 1 deletion(-)As i discussed with you these changes has been already posted.
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/148856
Kindly use them and resend yours patches.
Quoted 6 lines
arch/arm/cpu/armv7/exynos/clock.c
Quoted 4 lines
arch/arm/cpu/armv7/exynos/clock.c +0
-0Please have a look patch at the link.
[PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/143640
Quoted 286 lines
Quoted 278 lines
arch/arm/cpu/armv7/exynos/clock.c +6
-1@@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg) r =readl (&clk->apll_con0);break ;case MPLL : - r =readl (&clk->mpll_con0); +if (proid_is_exynos4412 ()) { +struct exynos4412_clock *clk4412 = + (struct exynos4412_clock *)samsung_get_base_clock (); + r =readl (&clk4412->mpll_con0); + }else + r =readl (&clk->mpll_con0);break ;case EPLL : r =readl (&clk->epll_con0);arch/arm/include/asm/arch-exynos/clock.h +240
-0@@ -251,6 +251,246 @@ struct exynos4_clock {unsigned int div_iem_l1; }; +struct exynos4412_clock { +unsigned char res1[0x4200 ]; +unsigned int src_leftbus; +unsigned char res2[0x1fc ]; +unsigned int mux_stat_leftbus; +unsigned char res3[0xfc ]; +unsigned int div_leftbus; +unsigned char res4[0xfc ]; +unsigned int div_stat_leftbus; +unsigned char res5[0x1fc ]; +unsigned int gate_ip_leftbus; +unsigned char res6[0x12c ]; +unsigned int gate_ip_image; +unsigned char res7[0xcc ]; +unsigned int clkout_cmu_leftbus; +unsigned int clkout_cmu_leftbus_div_stat; +unsigned char res8[0x37f8 ]; +unsigned int src_rightbus; +unsigned char res9[0x1fc ]; +unsigned int mux_stat_rightbus; +unsigned char res10[0xfc ]; +unsigned int div_rightbus; +unsigned char res11[0xfc ]; +unsigned int div_stat_rightbus; +unsigned char res12[0x1fc ]; +unsigned int gate_ip_rightbus; +unsigned char res13[0x15c ]; +unsigned int gate_ip_perir; +unsigned char res14[0x9c ]; +unsigned int clkout_cmu_rightbus; +unsigned int clkout_cmu_rightbus_div_stat; +unsigned char res15[0x3608 ]; +unsigned int epll_lock; +unsigned char res16[0xc ]; +unsigned int vpll_lock; +unsigned char res17[0xec ]; +unsigned int epll_con0; +unsigned int epll_con1; +unsigned int epll_con2; +unsigned char res18[0x4 ]; +unsigned int vpll_con0; +unsigned int vpll_con1; +unsigned int vpll_con2; +unsigned char res19[0xe4 ]; +unsigned int src_top0; +unsigned int src_top1; +unsigned char res20[0x8 ]; +unsigned int src_cam0; +unsigned int src_tv; +unsigned int src_mfc; +unsigned int src_g3d; +unsigned char res21[0x4 ]; +unsigned int src_lcd0; +unsigned int src_isp; +unsigned int src_maudio; +unsigned int src_fsys; +unsigned char res22[0xc ]; +unsigned int src_peril0; +unsigned int src_peril1; +unsigned int src_cam1; +unsigned char res23[0xc4 ]; +unsigned int src_mask_cam0; +unsigned int src_mask_tv; +unsigned char res24[0xc ]; +unsigned int src_mask_lcd; +unsigned int src_mask_isp; +unsigned int src_mask_maudio; +unsigned int src_mask_fsys; +unsigned char res25[0xc ]; +unsigned int src_mask_peril0; +unsigned int src_mask_peril1; +unsigned char res26[0xb8 ]; +unsigned int mux_stat_top; +unsigned int mux_stat_top1; +unsigned char res27[0x10 ]; +unsigned int mux_stat_mfc; +unsigned int mux_stat_g3d; +unsigned char res28[0x28 ]; +unsigned int mux_stat_cam1; +unsigned char res29[0xb4 ]; +unsigned int div_top; +unsigned char res30[0xc ]; +unsigned int div_cam0; +unsigned int div_tv; +unsigned int div_mfc; +unsigned int div_g3d; +unsigned char res31[0x4 ]; +unsigned int div_lcd; +unsigned int div_isp; +unsigned int div_maudio; +unsigned int div_fsys0; +unsigned int div_fsys1; +unsigned int div_fsys2; +unsigned int div_fsys3; +unsigned int div_peril0; +unsigned int div_peril1; +unsigned int div_peril2; +unsigned int div_peril3; +unsigned int div_peril4; +unsigned int div_peril5; +unsigned int div_cam1; +unsigned char res32[0x14 ]; +unsigned int div2_ratio; +unsigned char res33[0x8c ]; +unsigned int div_stat_top; +unsigned char res34[0xc ]; +unsigned int div_stat_cam0; +unsigned int div_stat_tv; +unsigned int div_stat_mfc; +unsigned int div_stat_g3d; +unsigned char res35[0x4 ]; +unsigned int div_stat_lcd; +unsigned int div_stat_isp; +unsigned int div_stat_maudio; +unsigned int div_stat_fsys0; +unsigned int div_stat_fsys1; +unsigned int div_stat_fsys2; +unsigned int div_stat_fsys3; +unsigned int div_stat_peril0; +unsigned int div_stat_peril1; +unsigned int div_stat_peril2; +unsigned int div_stat_peril3; +unsigned int div_stat_peril4; +unsigned int div_stat_peril5; +unsigned int div_stat_cam1; +unsigned char res36[0x14 ]; +unsigned int div2_stat; +unsigned char res37[0xc0 ]; +unsigned int gate_bus_fsys1; +unsigned char res38[0x1d8 ]; +unsigned int gate_ip_cam; +unsigned int gate_ip_tv; +unsigned int gate_ip_mfc; +unsigned int gate_ip_g3d; +unsigned char res39[0x4 ]; +unsigned int gate_ip_lcd; +unsigned int gate_ip_isp; +unsigned char res40[0x4 ]; +unsigned int gate_ip_fsys; +unsigned char res41[0x8 ]; +unsigned int gate_ip_gps; +unsigned int gate_ip_peril; +unsigned char res42[0x1c ]; +unsigned int gate_block; +unsigned char res43[0x8c ]; +unsigned int clkout_cmu_top; +unsigned int clkout_cmu_top_div_stat; +unsigned char res44[0x3600 ]; +unsigned int mpll_lock; +unsigned char res45[0xfc ]; +unsigned int mpll_con0; +unsigned int mpll_con1; +unsigned char res46[0xf0 ]; +unsigned int src_dmc; +unsigned char res47[0xfc ]; +unsigned int src_mask_dmc; +unsigned char res48[0xfc ]; +unsigned int mux_stat_dmc; +unsigned char res49[0xfc ]; +unsigned int div_dmc0; +unsigned int div_dmc1; +unsigned char res50[0xf8 ]; +unsigned int div_stat_dmc0; +unsigned int div_stat_dmc1; +unsigned char res51[0x2f8 ]; +unsigned int gate_ip_dmc; +unsigned int gate_ip_dmc1; +unsigned char res52[0xf8 ]; +unsigned int clkout_cmu_dmc; +unsigned int clkout_cmu_dmc_div_stat; +unsigned char res53[0x5f8 ]; +unsigned int dcgidx_map0; +unsigned int dcgidx_map1; +unsigned int dcgidx_map2; +unsigned char res54[0x14 ]; +unsigned int dcgperf_map0; +unsigned int dcgperf_map1; +unsigned char res55[0x18 ]; +unsigned int dvcidx_map; +unsigned char res56[0x1c ]; +unsigned int freq_cpu; +unsigned int freq_dpm; +unsigned char res57[0x18 ]; +unsigned int dvsemclk_en; +unsigned int maxperf; +unsigned char res58[0xc ]; +unsigned int dmc_puause_ctrl; +unsigned int ddrphy_lock_ctrl; +unsigned int c2c_state; +unsigned char res59[0x2f60 ]; +unsigned int apll_lock; +unsigned char res60[0xfc ]; +unsigned int apll_con0; +unsigned int apll_con1; +unsigned char res61[0xf8 ]; +unsigned int src_cpu; +unsigned char res62[0x1fc ]; +unsigned int mux_stat_cpu; +unsigned char res63[0xfc ]; +unsigned int div_cpu0; +unsigned int div_cpu1; +unsigned char res64[0xf8 ]; +unsigned int div_stat_cpu0; +unsigned int div_stat_cpu1; +unsigned char res65[0x2f8 ]; +unsigned int gate_ip_cpu; +unsigned char res66[0xfc ]; +unsigned int clkout_cmu_cpu; +unsigned int clkout_cmu_cpu_div_stat; +unsigned char res67[0x5f8 ]; +unsigned int armclk_stopctrl; +unsigned int atclk_stopctrl; +unsigned char res68[0x18 ]; +unsigned int pwr_ctrl; +unsigned int pwr_ctrl2; +unsigned char res69[0x3d8 ]; +unsigned int l2_status; +unsigned char res70[0xc ]; +unsigned int cpu_status; +unsigned char res71[0xc ]; +unsigned int ptm_status; +unsigned char res72[0x2edc ]; +unsigned int clk_div_isp0; +unsigned int clk_div_isp1; +unsigned char res73[0xf8 ]; +unsigned int clk_div_stat_isp0; +unsigned int clk_div_stat_isp1; +unsigned char res74[0x3f8 ]; +unsigned int gate_ip_isp0; +unsigned int gate_ip_isp1; +unsigned char res75[0x1f8 ]; +unsigned int clkout_cmu_isp; +unsigned int clkout_cmu_isp_stat; +unsigned char res76[0xf8 ]; +unsigned int clkout_cmu_spare0; +unsigned int clkout_cmu_spare1; +unsigned int clkout_cmu_spare2; +unsigned int clkout_cmu_spare3; +}; +struct exynos5_clock {unsigned int apll_lock;unsigned char res1[0xfc ];arch/arm/include/asm/arch-exynos/cpu.h +1
-1@@ -152,6 +152,7 @@ static inline int proid_is_##type(void) \ } IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250)#define SAMSUNG_BASE (device, base) \ --Quoted 2 lines
1.7.9.5
--
with warm regards,
Chander Kashyap
Signature · 2 lines
with warm regards, Chander Kashyap
PATCH 3/4 EXYNOS4: Add support for Exynos4x12 SoCs
Dear Chander,
2012? 12? 13? 15:19, Chander Kashyap ? ?:
Quoted 21 lines · Chander Kashyap
Quoted 20 lines
Dear Kim,
Quoted 7 lines · Jeong Hyeon Kim
From: Jeong-Hyeon Kim <[email protected]>
This patch adds the support for Exynos4212/4412.
Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar. Address of a few registers are different in CMU part like MPLL.
Quoted 7 lines
Signed-off-by Jeong-Hyeon Kim <[email protected]>--- arch/arm/cpu/armv7/exynos/clock.c | 7 +- arch/arm/include/asm/arch-exynos/clock.h | 240 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 1 + 3 files changed, 247 insertions(+), 1 deletion(-)As i discussed with you these changes has been already posted.
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/148856
Kindly use them and resend yours patches.
Quoted 7 lines
Quoted 6 lines
arch/arm/cpu/armv7/exynos/clock.c
Quoted 4 lines
arch/arm/cpu/armv7/exynos/clock.c +0
-0Please have a look patch at the link.
[PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequencyhttp://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/143640
I applied it and your resend patches at 7, Dec. to latest u-boot-samsung tree.
http://patchwork.ozlabs.org/patch/204445/
It made compile error as below. /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In function 'samsung_get_base_i2s':
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208: error:
'EXYNOS4X12_I2S_BASE' undeclared (first use in this function) /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208: error:
(Each undeclared identifier is reported only once /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208: error:
for each function it appears in.) /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In function 'samsung_get_base_spi':
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:226: error:
'EXYNOS4X12_SPI_BASE' undeclared (first use in this function) /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In function 'samsung_get_base_spi_isp':
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:227: error:
'EXYNOS4X12_SPI_ISP_BASE' undeclared (first use in this function)
Please resend patches after fix it.
Quoted 288 lines
Quoted 286 lines
Quoted 279 lines
arch/arm/cpu/armv7/exynos/clock.c +6
-1@@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg) r =readl (&clk->apll_con0);break ;case MPLL : - r =readl (&clk->mpll_con0); +if (proid_is_exynos4412 ()) { +struct exynos4412_clock *clk4412 = + (struct exynos4412_clock *)samsung_get_base_clock (); + r =readl (&clk4412->mpll_con0); + }else + r =readl (&clk->mpll_con0);break ;case EPLL : r =readl (&clk->epll_con0);arch/arm/include/asm/arch-exynos/clock.h +240
-0@@ -251,6 +251,246 @@ struct exynos4_clock {unsigned int div_iem_l1; }; +struct exynos4412_clock { +unsigned char res1[0x4200 ]; +unsigned int src_leftbus; +unsigned char res2[0x1fc ]; +unsigned int mux_stat_leftbus; +unsigned char res3[0xfc ]; +unsigned int div_leftbus; +unsigned char res4[0xfc ]; +unsigned int div_stat_leftbus; +unsigned char res5[0x1fc ]; +unsigned int gate_ip_leftbus; +unsigned char res6[0x12c ]; +unsigned int gate_ip_image; +unsigned char res7[0xcc ]; +unsigned int clkout_cmu_leftbus; +unsigned int clkout_cmu_leftbus_div_stat; +unsigned char res8[0x37f8 ]; +unsigned int src_rightbus; +unsigned char res9[0x1fc ]; +unsigned int mux_stat_rightbus; +unsigned char res10[0xfc ]; +unsigned int div_rightbus; +unsigned char res11[0xfc ]; +unsigned int div_stat_rightbus; +unsigned char res12[0x1fc ]; +unsigned int gate_ip_rightbus; +unsigned char res13[0x15c ]; +unsigned int gate_ip_perir; +unsigned char res14[0x9c ]; +unsigned int clkout_cmu_rightbus; +unsigned int clkout_cmu_rightbus_div_stat; +unsigned char res15[0x3608 ]; +unsigned int epll_lock; +unsigned char res16[0xc ]; +unsigned int vpll_lock; +unsigned char res17[0xec ]; +unsigned int epll_con0; +unsigned int epll_con1; +unsigned int epll_con2; +unsigned char res18[0x4 ]; +unsigned int vpll_con0; +unsigned int vpll_con1; +unsigned int vpll_con2; +unsigned char res19[0xe4 ]; +unsigned int src_top0; +unsigned int src_top1; +unsigned char res20[0x8 ]; +unsigned int src_cam0; +unsigned int src_tv; +unsigned int src_mfc; +unsigned int src_g3d; +unsigned char res21[0x4 ]; +unsigned int src_lcd0; +unsigned int src_isp; +unsigned int src_maudio; +unsigned int src_fsys; +unsigned char res22[0xc ]; +unsigned int src_peril0; +unsigned int src_peril1; +unsigned int src_cam1; +unsigned char res23[0xc4 ]; +unsigned int src_mask_cam0; +unsigned int src_mask_tv; +unsigned char res24[0xc ]; +unsigned int src_mask_lcd; +unsigned int src_mask_isp; +unsigned int src_mask_maudio; +unsigned int src_mask_fsys; +unsigned char res25[0xc ]; +unsigned int src_mask_peril0; +unsigned int src_mask_peril1; +unsigned char res26[0xb8 ]; +unsigned int mux_stat_top; +unsigned int mux_stat_top1; +unsigned char res27[0x10 ]; +unsigned int mux_stat_mfc; +unsigned int mux_stat_g3d; +unsigned char res28[0x28 ]; +unsigned int mux_stat_cam1; +unsigned char res29[0xb4 ]; +unsigned int div_top; +unsigned char res30[0xc ]; +unsigned int div_cam0; +unsigned int div_tv; +unsigned int div_mfc; +unsigned int div_g3d; +unsigned char res31[0x4 ]; +unsigned int div_lcd; +unsigned int div_isp; +unsigned int div_maudio; +unsigned int div_fsys0; +unsigned int div_fsys1; +unsigned int div_fsys2; +unsigned int div_fsys3; +unsigned int div_peril0; +unsigned int div_peril1; +unsigned int div_peril2; +unsigned int div_peril3; +unsigned int div_peril4; +unsigned int div_peril5; +unsigned int div_cam1; +unsigned char res32[0x14 ]; +unsigned int div2_ratio; +unsigned char res33[0x8c ]; +unsigned int div_stat_top; +unsigned char res34[0xc ]; +unsigned int div_stat_cam0; +unsigned int div_stat_tv; +unsigned int div_stat_mfc; +unsigned int div_stat_g3d; +unsigned char res35[0x4 ]; +unsigned int div_stat_lcd; +unsigned int div_stat_isp; +unsigned int div_stat_maudio; +unsigned int div_stat_fsys0; +unsigned int div_stat_fsys1; +unsigned int div_stat_fsys2; +unsigned int div_stat_fsys3; +unsigned int div_stat_peril0; +unsigned int div_stat_peril1; +unsigned int div_stat_peril2; +unsigned int div_stat_peril3; +unsigned int div_stat_peril4; +unsigned int div_stat_peril5; +unsigned int div_stat_cam1; +unsigned char res36[0x14 ]; +unsigned int div2_stat; +unsigned char res37[0xc0 ]; +unsigned int gate_bus_fsys1; +unsigned char res38[0x1d8 ]; +unsigned int gate_ip_cam; +unsigned int gate_ip_tv; +unsigned int gate_ip_mfc; +unsigned int gate_ip_g3d; +unsigned char res39[0x4 ]; +unsigned int gate_ip_lcd; +unsigned int gate_ip_isp; +unsigned char res40[0x4 ]; +unsigned int gate_ip_fsys; +unsigned char res41[0x8 ]; +unsigned int gate_ip_gps; +unsigned int gate_ip_peril; +unsigned char res42[0x1c ]; +unsigned int gate_block; +unsigned char res43[0x8c ]; +unsigned int clkout_cmu_top; +unsigned int clkout_cmu_top_div_stat; +unsigned char res44[0x3600 ]; +unsigned int mpll_lock; +unsigned char res45[0xfc ]; +unsigned int mpll_con0; +unsigned int mpll_con1; +unsigned char res46[0xf0 ]; +unsigned int src_dmc; +unsigned char res47[0xfc ]; +unsigned int src_mask_dmc; +unsigned char res48[0xfc ]; +unsigned int mux_stat_dmc; +unsigned char res49[0xfc ]; +unsigned int div_dmc0; +unsigned int div_dmc1; +unsigned char res50[0xf8 ]; +unsigned int div_stat_dmc0; +unsigned int div_stat_dmc1; +unsigned char res51[0x2f8 ]; +unsigned int gate_ip_dmc; +unsigned int gate_ip_dmc1; +unsigned char res52[0xf8 ]; +unsigned int clkout_cmu_dmc; +unsigned int clkout_cmu_dmc_div_stat; +unsigned char res53[0x5f8 ]; +unsigned int dcgidx_map0; +unsigned int dcgidx_map1; +unsigned int dcgidx_map2; +unsigned char res54[0x14 ]; +unsigned int dcgperf_map0; +unsigned int dcgperf_map1; +unsigned char res55[0x18 ]; +unsigned int dvcidx_map; +unsigned char res56[0x1c ]; +unsigned int freq_cpu; +unsigned int freq_dpm; +unsigned char res57[0x18 ]; +unsigned int dvsemclk_en; +unsigned int maxperf; +unsigned char res58[0xc ]; +unsigned int dmc_puause_ctrl; +unsigned int ddrphy_lock_ctrl; +unsigned int c2c_state; +unsigned char res59[0x2f60 ]; +unsigned int apll_lock; +unsigned char res60[0xfc ]; +unsigned int apll_con0; +unsigned int apll_con1; +unsigned char res61[0xf8 ]; +unsigned int src_cpu; +unsigned char res62[0x1fc ]; +unsigned int mux_stat_cpu; +unsigned char res63[0xfc ]; +unsigned int div_cpu0; +unsigned int div_cpu1; +unsigned char res64[0xf8 ]; +unsigned int div_stat_cpu0; +unsigned int div_stat_cpu1; +unsigned char res65[0x2f8 ]; +unsigned int gate_ip_cpu; +unsigned char res66[0xfc ]; +unsigned int clkout_cmu_cpu; +unsigned int clkout_cmu_cpu_div_stat; +unsigned char res67[0x5f8 ]; +unsigned int armclk_stopctrl; +unsigned int atclk_stopctrl; +unsigned char res68[0x18 ]; +unsigned int pwr_ctrl; +unsigned int pwr_ctrl2; +unsigned char res69[0x3d8 ]; +unsigned int l2_status; +unsigned char res70[0xc ]; +unsigned int cpu_status; +unsigned char res71[0xc ]; +unsigned int ptm_status; +unsigned char res72[0x2edc ]; +unsigned int clk_div_isp0; +unsigned int clk_div_isp1; +unsigned char res73[0xf8 ]; +unsigned int clk_div_stat_isp0; +unsigned int clk_div_stat_isp1; +unsigned char res74[0x3f8 ]; +unsigned int gate_ip_isp0; +unsigned int gate_ip_isp1; +unsigned char res75[0x1f8 ]; +unsigned int clkout_cmu_isp; +unsigned int clkout_cmu_isp_stat; +unsigned char res76[0xf8 ]; +unsigned int clkout_cmu_spare0; +unsigned int clkout_cmu_spare1; +unsigned int clkout_cmu_spare2; +unsigned int clkout_cmu_spare3; +}; +struct exynos5_clock {unsigned int apll_lock;unsigned char res1[0xfc ];arch/arm/include/asm/arch-exynos/cpu.h +1
-1@@ -152,6 +152,7 @@ static inline int proid_is_##type(void) \ } IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250)#define SAMSUNG_BASE (device, base) \ --Quoted 2 lines
1.7.9.5
--
with warm regards,
Chander Kashyap
PATCH 3/4 EXYNOS4: Add support for Exynos4x12 SoCs
Dear Kim,
Quoted 54 lines · ???
Dear Chander,
2012? 12? 13? 15:19, Chander Kashyap ? ?:
On 13 December 2012 11:49, Chander Kashyap <[email protected]> wrote:
Dear Kim,
On 12 December 2012 13:24, Jeong Hyeon Kim <[email protected]> wrote:
From: Jeong-Hyeon Kim <[email protected]>
This patch adds the support for Exynos4212/4412.
Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar. Address of a few registers are different in CMU part like MPLL.
Signed-off-by Jeong-Hyeon Kim <[email protected]>--- arch/arm/cpu/armv7/exynos/clock.c | 7 +- arch/arm/include/asm/arch-exynos/clock.h | 240 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 1 + 3 files changed, 247 insertions(+), 1 deletion(-)As i discussed with you these changes has been already posted.
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/148856
Kindly use them and resend yours patches.arch/arm/cpu/armv7/exynos/clock.c +0
-0Please have a look patch at the link.
[PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequencyhttp://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/143640
I applied it and your resend patches at 7, Dec. to latest u-boot-samsung tree.
http://patchwork.ozlabs.org/patch/204445/It made compile error as below. /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In function '
samsung_get_base_i2s':
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208:
error: 'EXYNOS4X12_I2S_BASE' undeclared (first use in this function) /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208:
error: (Each undeclared identifier is reported only once /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208:
error: for each function it appears in.)
Quoted 8 lines
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In function '
samsung_get_base_spi':
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:226:
error: 'EXYNOS4X12_SPI_BASE' undeclared (first use in this function) /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In function 'samsung_get_base_spi_isp':
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:227:
error: 'EXYNOS4X12_SPI_ISP_BASE' undeclared (first use in this function)
You need apply my patches. Then add these base addresses in cpu.h and create a patch. Then add yours board specific patches.
Quoted 297 lines
Please resend patches after fix it.
arch/arm/cpu/armv7/exynos/clock.c +6
-1@@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg) r =readl (&clk->apll_con0);break ;case MPLL : - r =readl (&clk->mpll_con0); +if (proid_is_exynos4412 ()) { +struct exynos4412_clock *clk4412 = + (struct exynos4412_clock *)samsung_get_base_clock (); + r =readl (&clk4412->mpll_con0); + }else + r =readl (&clk->mpll_con0);break ;case EPLL :r = readl(&clk->epll_con0);arch/arm/include/asm/arch-exynos/clock.h +240
-0@@ -251,6 +251,246 @@ struct exynos4_clock {unsigned int div_iem_l1; }; +struct exynos4412_clock { +unsigned char res1[0x4200 ]; +unsigned int src_leftbus; +unsigned char res2[0x1fc ]; +unsigned int mux_stat_leftbus; +unsigned char res3[0xfc ]; +unsigned int div_leftbus; +unsigned char res4[0xfc ]; +unsigned int div_stat_leftbus; +unsigned char res5[0x1fc ]; +unsigned int gate_ip_leftbus; +unsigned char res6[0x12c ]; +unsigned int gate_ip_image; +unsigned char res7[0xcc ]; +unsigned int clkout_cmu_leftbus; +unsigned int clkout_cmu_leftbus_div_stat; +unsigned char res8[0x37f8 ]; +unsigned int src_rightbus; +unsigned char res9[0x1fc ]; +unsigned int mux_stat_rightbus; +unsigned char res10[0xfc ]; +unsigned int div_rightbus; +unsigned char res11[0xfc ]; +unsigned int div_stat_rightbus; +unsigned char res12[0x1fc ]; +unsigned int gate_ip_rightbus; +unsigned char res13[0x15c ]; +unsigned int gate_ip_perir; +unsigned char res14[0x9c ]; +unsigned int clkout_cmu_rightbus; +unsigned int clkout_cmu_rightbus_div_stat; +unsigned char res15[0x3608 ]; +unsigned int epll_lock; +unsigned char res16[0xc ]; +unsigned int vpll_lock; +unsigned char res17[0xec ]; +unsigned int epll_con0; +unsigned int epll_con1; +unsigned int epll_con2; +unsigned char res18[0x4 ]; +unsigned int vpll_con0; +unsigned int vpll_con1; +unsigned int vpll_con2; +unsigned char res19[0xe4 ]; +unsigned int src_top0; +unsigned int src_top1; +unsigned char res20[0x8 ]; +unsigned int src_cam0; +unsigned int src_tv; +unsigned int src_mfc; +unsigned int src_g3d; +unsigned char res21[0x4 ]; +unsigned int src_lcd0; +unsigned int src_isp; +unsigned int src_maudio; +unsigned int src_fsys; +unsigned char res22[0xc ]; +unsigned int src_peril0; +unsigned int src_peril1; +unsigned int src_cam1; +unsigned char res23[0xc4 ]; +unsigned int src_mask_cam0; +unsigned int src_mask_tv; +unsigned char res24[0xc ]; +unsigned int src_mask_lcd; +unsigned int src_mask_isp; +unsigned int src_mask_maudio; +unsigned int src_mask_fsys; +unsigned char res25[0xc ]; +unsigned int src_mask_peril0; +unsigned int src_mask_peril1; +unsigned char res26[0xb8 ]; +unsigned int mux_stat_top; +unsigned int mux_stat_top1; +unsigned char res27[0x10 ]; +unsigned int mux_stat_mfc; +unsigned int mux_stat_g3d; +unsigned char res28[0x28 ]; +unsigned int mux_stat_cam1; +unsigned char res29[0xb4 ]; +unsigned int div_top; +unsigned char res30[0xc ]; +unsigned int div_cam0; +unsigned int div_tv; +unsigned int div_mfc; +unsigned int div_g3d; +unsigned char res31[0x4 ]; +unsigned int div_lcd; +unsigned int div_isp; +unsigned int div_maudio; +unsigned int div_fsys0; +unsigned int div_fsys1; +unsigned int div_fsys2; +unsigned int div_fsys3; +unsigned int div_peril0; +unsigned int div_peril1; +unsigned int div_peril2; +unsigned int div_peril3; +unsigned int div_peril4; +unsigned int div_peril5; +unsigned int div_cam1; +unsigned char res32[0x14 ]; +unsigned int div2_ratio; +unsigned char res33[0x8c ]; +unsigned int div_stat_top; +unsigned char res34[0xc ]; +unsigned int div_stat_cam0; +unsigned int div_stat_tv; +unsigned int div_stat_mfc; +unsigned int div_stat_g3d; +unsigned char res35[0x4 ]; +unsigned int div_stat_lcd; +unsigned int div_stat_isp; +unsigned int div_stat_maudio; +unsigned int div_stat_fsys0; +unsigned int div_stat_fsys1; +unsigned int div_stat_fsys2; +unsigned int div_stat_fsys3; +unsigned int div_stat_peril0; +unsigned int div_stat_peril1; +unsigned int div_stat_peril2; +unsigned int div_stat_peril3; +unsigned int div_stat_peril4; +unsigned int div_stat_peril5; +unsigned int div_stat_cam1; +unsigned char res36[0x14 ]; +unsigned int div2_stat; +unsigned char res37[0xc0 ]; +unsigned int gate_bus_fsys1; +unsigned char res38[0x1d8 ]; +unsigned int gate_ip_cam; +unsigned int gate_ip_tv; +unsigned int gate_ip_mfc; +unsigned int gate_ip_g3d; +unsigned char res39[0x4 ]; +unsigned int gate_ip_lcd; +unsigned int gate_ip_isp; +unsigned char res40[0x4 ]; +unsigned int gate_ip_fsys; +unsigned char res41[0x8 ]; +unsigned int gate_ip_gps; +unsigned int gate_ip_peril; +unsigned char res42[0x1c ]; +unsigned int gate_block; +unsigned char res43[0x8c ]; +unsigned int clkout_cmu_top; +unsigned int clkout_cmu_top_div_stat; +unsigned char res44[0x3600 ]; +unsigned int mpll_lock; +unsigned char res45[0xfc ]; +unsigned int mpll_con0; +unsigned int mpll_con1; +unsigned char res46[0xf0 ]; +unsigned int src_dmc; +unsigned char res47[0xfc ]; +unsigned int src_mask_dmc; +unsigned char res48[0xfc ]; +unsigned int mux_stat_dmc; +unsigned char res49[0xfc ]; +unsigned int div_dmc0; +unsigned int div_dmc1; +unsigned char res50[0xf8 ]; +unsigned int div_stat_dmc0; +unsigned int div_stat_dmc1; +unsigned char res51[0x2f8 ]; +unsigned int gate_ip_dmc; +unsigned int gate_ip_dmc1; +unsigned char res52[0xf8 ]; +unsigned int clkout_cmu_dmc; +unsigned int clkout_cmu_dmc_div_stat; +unsigned char res53[0x5f8 ]; +unsigned int dcgidx_map0; +unsigned int dcgidx_map1; +unsigned int dcgidx_map2; +unsigned char res54[0x14 ]; +unsigned int dcgperf_map0; +unsigned int dcgperf_map1; +unsigned char res55[0x18 ]; +unsigned int dvcidx_map; +unsigned char res56[0x1c ]; +unsigned int freq_cpu; +unsigned int freq_dpm; +unsigned char res57[0x18 ]; +unsigned int dvsemclk_en; +unsigned int maxperf; +unsigned char res58[0xc ]; +unsigned int dmc_puause_ctrl; +unsigned int ddrphy_lock_ctrl; +unsigned int c2c_state; +unsigned char res59[0x2f60 ]; +unsigned int apll_lock; +unsigned char res60[0xfc ]; +unsigned int apll_con0; +unsigned int apll_con1; +unsigned char res61[0xf8 ]; +unsigned int src_cpu; +unsigned char res62[0x1fc ]; +unsigned int mux_stat_cpu; +unsigned char res63[0xfc ]; +unsigned int div_cpu0; +unsigned int div_cpu1; +unsigned char res64[0xf8 ]; +unsigned int div_stat_cpu0; +unsigned int div_stat_cpu1; +unsigned char res65[0x2f8 ]; +unsigned int gate_ip_cpu; +unsigned char res66[0xfc ]; +unsigned int clkout_cmu_cpu; +unsigned int clkout_cmu_cpu_div_stat; +unsigned char res67[0x5f8 ]; +unsigned int armclk_stopctrl; +unsigned int atclk_stopctrl; +unsigned char res68[0x18 ]; +unsigned int pwr_ctrl; +unsigned int pwr_ctrl2; +unsigned char res69[0x3d8 ]; +unsigned int l2_status; +unsigned char res70[0xc ]; +unsigned int cpu_status; +unsigned char res71[0xc ]; +unsigned int ptm_status; +unsigned char res72[0x2edc ]; +unsigned int clk_div_isp0; +unsigned int clk_div_isp1; +unsigned char res73[0xf8 ]; +unsigned int clk_div_stat_isp0; +unsigned int clk_div_stat_isp1; +unsigned char res74[0x3f8 ]; +unsigned int gate_ip_isp0; +unsigned int gate_ip_isp1; +unsigned char res75[0x1f8 ]; +unsigned int clkout_cmu_isp; +unsigned int clkout_cmu_isp_stat; +unsigned char res76[0xf8 ]; +unsigned int clkout_cmu_spare0; +unsigned int clkout_cmu_spare1; +unsigned int clkout_cmu_spare2; +unsigned int clkout_cmu_spare3; +}; +struct exynos5_clock {unsigned int apll_lock;unsigned char res1[0xfc ];arch/arm/include/asm/arch-exynos/cpu.h +1
-0@@ -152,6 +152,7 @@ static inline int proid_is_##type(void) \ } IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos4412, 0x4412)IS_EXYNOS_TYPE (exynos5250,0x5250 )#define
SAMSUNG_BASE(device, base)\
--
1.7.9.5--
with warm regards,
Chander Kashyap
Signature · 2 lines
with warm regards, Chander Kashyap
PATCH 4/4 EXYNOS4: Add ORIGEN_QUAD board support
In reply to Jeong Hyeon KimFrom: Jeong-Hyeon Kim <[email protected]>
ORIGEN_QUAD board is based on Samsung's Exynos4412 SoC.
Signed-off-by Jeong-Hyeon Kim <[email protected]>
--- Makefile | 2 +- board/samsung/origen_quad/Makefile | 59 ++++++ board/samsung/origen_quad/boot.c | 72 +++++++ board/samsung/origen_quad/clock.c | 103 ++++++++++ board/samsung/origen_quad/dmc.c | 163 ++++++++++++++++ board/samsung/origen_quad/lowlevel_init.S | 151 +++++++++++++++ board/samsung/origen_quad/origen_quad.c | 163 ++++++++++++++++ board/samsung/origen_quad/setup.h | 300 +++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/origen_quad.h | 179 +++++++++++++++++ tools/Makefile | 2 + 11 files changed, 1194 insertions(+), 1 deletion(-) create mode 100644 board/samsung/origen_quad/Makefile create mode 100644 board/samsung/origen_quad/boot.c create mode 100644 board/samsung/origen_quad/clock.c create mode 100644 board/samsung/origen_quad/dmc.c create mode 100644 board/samsung/origen_quad/lowlevel_init.S create mode 100644 board/samsung/origen_quad/origen_quad.c create mode 100644 board/samsung/origen_quad/setup.h create mode 100644 include/configs/origen_quad.h
Makefile +1 -1
@@ -823,7 +823,7 @@ clean: $(obj)tools/gdb/{astest,gdbcont,gdbsend} \ $(obj)tools/gen_eth_addr $(obj)tools/img2srec \ $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \ - $(obj)tools/mk{smdk5250,}spl \ + $(obj)tools/mk{$(SOC),$(BOARD),}spl \ $(obj)tools/mxsboot \ $(obj)tools/ncb $(obj)tools/ubsha1 \ $(obj)tools/kernel-doc/docproc
board/samsung/origen_quad/Makefile new file +59 -0
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board/samsung/origen_quad/boot.c new file +72 -0
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board/samsung/origen_quad/clock.c new file +103 -0
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board/samsung/origen_quad/dmc.c new file +163 -0
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board/samsung/origen_quad/lowlevel_init.S new file +151 -0
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board/samsung/origen_quad/origen_quad.c new file +163 -0
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board/samsung/origen_quad/setup.h new file +300 -0
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boards.cfg +1 -0
@@ -284,6 +284,7 @@ s5pc210_universal arm armv7 universal_c210 samsung smdk5250 arm armv7 smdk5250 samsung exynos smdkv310 arm armv7 smdkv310 samsung exynos trats arm armv7 trats samsung exynos +origen_quad arm armv7 origen_quad samsung exynos harmony arm armv7:arm720t harmony nvidia tegra20 seaboard arm armv7:arm720t seaboard nvidia tegra20 ventana arm armv7:arm720t ventana nvidia tegra20
include/configs/origen_quad.h new file +179 -0
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tools/Makefile +2 -0
@@ -68,6 +68,7 @@ BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) BIN_FILES-y += mkenvimage$(SFX) BIN_FILES-y += mkimage$(SFX) +BIN_FILES-$(CONFIG_EXYNOS4) += mk$(BOARD)spl$(SFX) BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX) BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
@@ -97,6 +98,7 @@ NOPED_OBJ_FILES-y += imximage.o NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkenvimage.o NOPED_OBJ_FILES-y += mkimage.o +OBJ_FILES-$(CONFIG_EXYNOS4) += mkexynosspl.o OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o OBJ_FILES-$(CONFIG_MX28) += mxsboot.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
Signature · 1 line
1.7.9.5