ARM: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs
PATCH 1/1 ARM: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs
flush_cache_louis flushes the D-side caches to the point of unification inner-shareable. On uniprocessor CPUs, this is defined as zero and therefore no flushing will take place. Rather than invent a new interface for UP systems, instead use our SMP_ON_UP patching code to read the LoUU from the CLIDR instead.
--- arch/arm/mm/cache-v7.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
arch/arm/mm/cache-v7.S +4 -2
@@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all) ENTRY(v7_flush_dcache_louis) dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr - ands r3, r0, #0xe00000 @ extract LoUIS from clidr - mov r3, r3, lsr #20 @ r3 = LoUIS * 2 + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr + ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 + ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 moveq pc, lr @ return if level == 0 mov r10, #0 @ r10 (starting level) = 0 b flush_levels @ start flushing cache levels
Signature · 1 line
1.8.0
PATCH 1/1 ARM: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs
Quoted 9 lines · Will Deacon
flush_cache_louisflushes the D-side caches to the point of unification inner-shareable. On uniprocessor CPUs, this is defined as zero and therefore no flushing will take place. Rather than invent a new interface for UP systems, instead use ourSMP_ON_UPpatching code to read the LoUU from the CLIDR instead.Cc Lorenzo Pieralisi <[email protected]>Signed-off-by Will Deacon <[email protected]>
This should be a candidate for the stable tree.
Nicolas
PATCH 1/1 ARM: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs
Quoted 8 lines · Nicolas Pitre
Quoted 6 lines · Will Deacon
flush_cache_louisflushes the D-side caches to the point of unification inner-shareable. On uniprocessor CPUs, this is defined as zero and therefore no flushing will take place. Rather than invent a new interface for UP systems, instead use ourSMP_ON_UPpatching code to read the LoUU from the CLIDR instead.
Quoted 5 lines
Quoted 3 lines
Cc Lorenzo Pieralisi <[email protected]>Signed-off-by Will Deacon <[email protected]>This should be a candidate for the stable tree.
Yup, the same also goes for the other fix I posted yesterday (RealView EB).
Cheers,
Will
PATCH 1/1 ARM: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs
In reply to Will DeaconQuoted 10 lines · Will Deacon
flush_cache_louisflushes the D-side caches to the point of unification inner-shareable. On uniprocessor CPUs, this is defined as zero and therefore no flushing will take place. Rather than invent a new interface for UP systems, instead use ourSMP_ON_UPpatching code to read the LoUU from the CLIDR instead.Cc Lorenzo Pieralisi <[email protected]>Signed-off-by Will Deacon <[email protected]>---
Looks reasonable idea.
Quoted 21 lines
arch/arm/mm/cache-v7.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)arch/arm/mm/cache-v7.S +4
-2@@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all) ENTRY(v7_flush_dcache_louis) dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr - ands r3, r0, #0xe00000 @ extract LoUIS from clidr - mov r3, r3, lsr #20 @ r3 = LoUIS * 2 + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr + ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 + ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 moveq pc, lr @ return if level == 0 mov r10, #0 @ r10 (starting level) = 0 b flush_levels @ start flushing cache levels