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ARM: tegra: clean up the CPUINIT section

PATCH New Joseph Lo 2 participants 3 messages Jan 4, 2013

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Arm (32-bit) Arm sub-architectures Tegra architecture support
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Joseph Lo

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#0 lore raw

PATCH 1/2 ARM: tegra: clean up the CPUINIT section

There are some redundant codes in the CPUINIT section that was caused by some codes not be organized well in "headsmp.S". Currently all the codes in "headsmp.S" were put into CPUINIT section. But actually it doesn't need to be loacted in CPUINIT section. There is no fuction access them in CPUINIT section and we will relocate them to IRAM.

These codes also caused some unnecessary functions that access these codes been put into CPUINIT section too. This patch clean it up and put them into normal text section.

Signed-off-by Joseph Lo <[email protected]>
---
 arch/arm/mach-tegra/cpuidle-tegra30.c | 6 +++---
 arch/arm/mach-tegra/headsmp.S         | 2 --
 arch/arm/mach-tegra/pm.c              | 4 ++--
 3 files changed, 5 insertions(+), 7 deletions(-)
arch/arm/mach-tegra/cpuidle-tegra30.c +3 -3
index 5e8cbf5..82530bd 100644
@@ -121,9 +121,9 @@ static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 }
 #endif
 
-static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
-				      struct cpuidle_driver *drv,
-				      int index)
+static int tegra30_idle_lp2(struct cpuidle_device *dev,
+			    struct cpuidle_driver *drv,
+			    int index)
 {
 	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
 	bool entered_lp2 = false;
arch/arm/mach-tegra/headsmp.S +0 -2
index 4a317fa..23f487d 100644
@@ -16,8 +16,6 @@
 #define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
 
         .section ".text.head", "ax"
-	__CPUINIT
-
 /*
  * Tegra specific entry point for secondary CPUs.
  *   The secondary kernel init calls v7_flush_dcache_all before it enables
arch/arm/mach-tegra/pm.c +2 -2
index 1b11707..498d70b 100644
@@ -148,7 +148,7 @@ static void suspend_cpu_complex(void)
 	save_cpu_arch_register();
 }
 
-void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id)
+void tegra_clear_cpu_in_lp2(int phy_cpu_id)
 {
 	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
 

@@ -160,7 +160,7 @@ void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id)
 	spin_unlock(&tegra_lp2_lock);
 }
 
-bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)
+bool tegra_set_cpu_in_lp2(int phy_cpu_id)
 {
 	bool last_cpu = false;
 	cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
Signature · 1 line
1.8.0.3
author
#1 lore raw

PATCH 2/2 ARM: tegra: make device can run on UP

The reset handler code is used for either UP or SMP. To make Tegra device can compile for UP. It needs to be moved to another file that is not SMP only. This is because the reset handler also be needed by CPU idle "powered-down" mode. So we also need to put the reset handler init function in non-SMP only and init them always.

And currently the implementation of the reset handler to know which CPU is OK to bring up was identital with "cpu_present_mask". But the "cpu_present_mask" did not initialize yet when the reset handler init function was moved to init early function. We use the "cpu_possible_mask" to replace "cpu_present_mask". Then it can work on both UP and SMP case.

Signed-off-by Joseph Lo <[email protected]>
---
 arch/arm/mach-tegra/Makefile                       |   2 +-
 arch/arm/mach-tegra/common.c                       |   3 +
 arch/arm/mach-tegra/headsmp.S                      | 262 ---------------------
 arch/arm/mach-tegra/platsmp.c                      |   1 -
 arch/arm/mach-tegra/{headsmp.S => reset-handler.S} |  26 +-
 arch/arm/mach-tegra/reset.c                        |   2 +-
 6 files changed, 21 insertions(+), 275 deletions(-)
 copy arch/arm/mach-tegra/{headsmp.S => reset-handler.S} (90%)
arch/arm/mach-tegra/Makefile +1 -1
index bd5d312..660ee03 100644
@@ -8,6 +8,7 @@ obj-y					+= flowctrl.o
 obj-y					+= powergate.o
 obj-y					+= apbio.o
 obj-y					+= pm.o
+obj-y					+= reset.o reset-handler.o
 obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
 obj-$(CONFIG_CPU_IDLE)			+= sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o

@@ -26,7 +27,6 @@ ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= cpuidle-tegra30.o
 endif
 obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
-obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
arch/arm/mach-tegra/common.c +3 -0
index d54cfc5..3efe80b 100644
@@ -37,6 +37,7 @@
 #include "apbio.h"
 #include "sleep.h"
 #include "pm.h"
+#include "reset.h"
 
 /*
  * Storage for debug-macro.S's state.

@@ -137,6 +138,7 @@ static void __init tegra_init_cache(void)
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 void __init tegra20_init_early(void)
 {
+	tegra_cpu_reset_handler_init();
 	tegra_apb_io_init();
 	tegra_init_fuse();
 	tegra2_init_clocks();

@@ -150,6 +152,7 @@ void __init tegra20_init_early(void)
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 void __init tegra30_init_early(void)
 {
+	tegra_cpu_reset_handler_init();
 	tegra_apb_io_init();
 	tegra_init_fuse();
 	tegra30_init_clocks();
arch/arm/mach-tegra/headsmp.S +0 -262

274 lines not on this page · raw message

arch/arm/mach-tegra/platsmp.c +0 -1
index 5882da0f..60daf9f 100644
@@ -202,7 +202,6 @@ static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
 	/* Always mark the boot CPU (CPU0) as initialized. */
 	cpumask_set_cpu(0, &tegra_cpu_init_mask);
 
-	tegra_cpu_reset_handler_init();
 	scu_enable(scu_base);
 }
arch/arm/mach-tegra/reset-handler.S renamed from arch/arm/mach-tegra/headsmp.S +16 -10
similarity index 90%
copy from arch/arm/mach-tegra/headsmp.S
copy to arch/arm/mach-tegra/reset-handler.S
index 23f487d..1b34075 100644
@@ -1,3 +1,19 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
 #include <linux/linkage.h>
 #include <linux/init.h>
 

@@ -15,7 +31,6 @@
 
 #define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
 
-        .section ".text.head", "ax"
 /*
  * Tegra specific entry point for secondary CPUs.
  *   The secondary kernel init calls v7_flush_dcache_all before it enables

@@ -59,15 +74,6 @@ ENTRY(v7_invalidate_l1)
         mov     pc, lr
 ENDPROC(v7_invalidate_l1)
 
-
-ENTRY(tegra_secondary_startup)
-        bl      v7_invalidate_l1
-	/* Enable coresight */
-	mov32	r0, 0xC5ACCE55
-	mcr	p14, 0, r0, c7, c12, 6
-        b       secondary_startup
-ENDPROC(tegra_secondary_startup)
-
 #ifdef CONFIG_PM_SLEEP
 /*
  *	tegra_resume
arch/arm/mach-tegra/reset.c +1 -1
index 3fd89ec..1ac434e 100644
@@ -75,7 +75,7 @@ void __init tegra_cpu_reset_handler_init(void)
 
 #ifdef CONFIG_SMP
 	__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
-		*((u32 *)cpu_present_mask);
+		*((u32 *)cpu_possible_mask);
 	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
 		virt_to_phys((void *)tegra_secondary_startup);
 #endif
Signature · 1 line
1.8.0.3
Applied
#2 lore raw

PATCH 1/2 ARM: tegra: clean up the CPUINIT section

In reply to Joseph Lo
Quoted 9 lines · Joseph Lo

There are some redundant codes in the CPUINIT section that was caused by some codes not be organized well in "headsmp.S". Currently all the codes in "headsmp.S" were put into CPUINIT section. But actually it doesn't need to be loacted in CPUINIT section. There is no fuction access them in CPUINIT section and we will relocate them to IRAM.

These codes also caused some unnecessary functions that access these codes been put into CPUINIT section too. This patch clean it up and put them into normal text section.

Applied to Tegra's for-3.9/soc branch.