Migrate Tegra to common clock framework

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Tested on Tegra30 (Cardhu) and Tegra20 (Ventana).

Changes from v2:
Removed APB MISC node.
Fixed some issues reported by Joseph Lo.
Added function to read chip id revision register.

Changes from v1:
Rebased on linux-next for 20121224.

Prashant Gaikwad (8):
ARM: tegra: Add function to read chipid
clk: tegra: Add tegra specific clocks
arm: tegra: Move tegra_cpu_car.h to linux/clk/tegra.h
ARM: Tegra: Define Tegra30 CAR binding
clk: tegra: add clock support for tegra20
clk: tegra: add clock support for tegra30
arm: tegra: Migrate to new clock code
arm: tegra: Remove legacy clock code

Stephen Warren (1):
ARM: tegra: Define Tegra20 CAR binding

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Quoted 7 lines · Prashant Gaikwad

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

I think there are bugs here. I applied all your clock patches on top of Tegra's for-next (see list below), and found that the following don't work on Springbank:

* HDMI display
* Audio playback
* WiFi

drivers/spi/spi-tegra20-sflash.c +1 -1

index 02feaa5..e5dce91 100644
@@ -525,7 +525,7 @@ static int tegra_sflash_probe(struct platform_device *pdev)
                goto exit_free_master;
        }
 
-       tsd->clk = devm_clk_get(&pdev->dev, "spi");
+       tsd->clk = devm_clk_get(&pdev->dev, NULL);
        if (IS_ERR(tsd->clk)) {
                dev_err(&pdev->dev, "can not get clock\n");
                ret = PTR_ERR(tsd->clk);

drivers/spi/spi-tegra20-slink.c +0 -0

index fa208a5..e255e7a 100644

drivers/clk/tegra/clk-tegra30.c +0 -0

index a52b80c..661b9e1 100644

Quoted 12 lines · Stephen Warren

Quoted 7 lines · Prashant Gaikwad

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

I think there are bugs here. I applied all your clock patches on top of Tegra's for-next (see list below), and found that the following don't work on Springbank:

Quoted 3 lines

* HDMI display
* Audio playback
* WiFi

(BTW, I stopped Cc'ing linux-kernel@, but added linux-tegra@ instead...)

Prashant, some updated testing results based off the "dev/ccf" branch you sent me on our internal git server:

The following work, on both Tegra20/30 unless otherwise specified:

* MMC/SD, I2C, audio, HDMI display (Tegra20 only; on Springbank), USB (Tegra20 only; not implemented on Tegra30).

I didn't test the following yet:

* LCD display on Tegra20.

The following are broken:

1)

SPI on either chip. This is because the SPI drivers call clk_get() with a specific clock name, and the DT patches you created don't have a clk-names property for any of the SPI nodes, hence this fails. However, since there's only a single clock to the SPI controllers, I think the drivers should be fixed not to request a specific clock name. The following makes SPI work on TrimSlice (Tegra20) and Cardhu (Tegra30):

Quoted 21 lines

drivers/spi/spi-tegra20-sflash.c +1 -1

index 02feaa5..e5dce91 100644
@@ -525,7 +525,7 @@ static int tegra_sflash_probe(struct platform_device *pdev)
                 goto exit_free_master;
         }
 
-       tsd->clk = devm_clk_get(&pdev->dev, "spi");
+       tsd->clk = devm_clk_get(&pdev->dev, NULL);
         if (IS_ERR(tsd->clk)) {
                 dev_err(&pdev->dev, "can not get clock\n");
                 ret = PTR_ERR(tsd->clk);

drivers/spi/spi-tegra20-slink.c +0 -0

index fa208a5..e255e7a 100644
@@ -1191,7 +1191,7 @@ static int tegra_slink_probe(struct platform_device *pdev)
                 goto exit_free_master;
         }
 

drivers/spi/spi-tegra20-slink.c static int tegra_slink_probe(struct platform_device *pdev) · line 1197

Quoted 5 lines

drivers/spi/spi-tegra20-slink.c +1 -1

-       tspi->clk = devm_clk_get(&pdev->dev, "slink");
+       tspi->clk = devm_clk_get(&pdev->dev, NULL);
         if (IS_ERR(tspi->clk)) {
                 dev_err(&pdev->dev, "can not get clock\n");
                 ret = PTR_ERR(tspi->clk);

I think you should include that in your series before the patches which add clocks into the DT.

2)

HDMI and LCD display are both broken on Cardhu/Tegra30.

I found that the DT lists the HDMI clock's parent as pll_d2_out0, yet the clock driver lists pll_d2 as a valid parent. I think the following patch fixes this correctly?

Quoted 5 lines

drivers/clk/tegra/clk-tegra30.c +0 -0

index a52b80c..661b9e1 100644

drivers/clk/tegra/clk-tegra30.c static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m", · line 1392

Quoted 10 lines

drivers/clk/tegra/clk-tegra30.c +2 -2

@@ -1385,8 +1385,8 @@ static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
  static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a" };
  static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d", "pll_c", "clk_m" };
  static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
-static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d",
-                                            "pll_a", "pll_c", "pll_d2",
+static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
+                                            "pll_a", "pll_c", "pll_d2_out0",
                                              "clk_m" };
  static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
                                                         "clk_32k", "pll_p",

(are there any other similar problems in the code?)

After that, if I comment out:

late_initcall(clk_disable_unused);

... then either HDMI or LCD output on Cardhu work OK (or rather in HDMI's case, as well as can be expected due incorrect memory controller programming and hence display underflow at the moment). I haven't had a chance to investigate why that initcall is causing problems (the problem being a HW hang during boot in the HDMI case, and simply no visible output in the LCD case, but the system otherwise works OK).

For reference, the patches to enable LCD/HDMI on Cardhu can be found in:

git://nv-tegra.nvidia.com/user/swarren/linux-2.6 linux-next_common

3)

WiFi doesn't work on either chip (Springbank or Cardhu, but I expect Ventana has the same issue). I haven't been able to investigate why yet.

4)

I noticed that the PCIe driver (on Trimslice/Tegra20) was complaining about clk_get() failing or similar. I haven't been able to investigate why yet.

For reference, all of these problems are all introduced by your commit "arm: tegra: Migrate to new clock code"; everything works immediately before that.

Let me know if you find any solutions to these; I guess just update your branch. Otherwise, I'll keep investigating tomorrow.

Quoted 20 lines · Stephen Warren

Quoted 8 lines · Stephen Warren

Quoted 7 lines · Prashant Gaikwad

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Quoted 7 lines

I think there are bugs here. I applied all your clock patches on top of Tegra's for-next (see list below), and found that the following don't work on Springbank:

* HDMI display
* Audio playback
* WiFi

(BTW, I stopped Cc'ing linux-kernel@, but added linux-tegra@ instead...)

Prashant, some updated testing results based off the "dev/ccf" branch you sent me on our internal git server:

I have updated the internal branch with all the above mentioned fixes.

Quoted 21 lines · Prashant Gaikwad

Quoted 20 lines · Stephen Warren

Quoted 8 lines · Stephen Warren

Quoted 7 lines · Prashant Gaikwad

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Quoted 7 lines

I think there are bugs here. I applied all your clock patches on top of Tegra's for-next (see list below), and found that the following don't work on Springbank:

* HDMI display
* Audio playback
* WiFi

(BTW, I stopped Cc'ing linux-kernel@, but added linux-tegra@ instead...)

Prashant, some updated testing results based off the "dev/ccf" branch you sent me on our internal git server:

...

Quoted 1 line

I have updated the internal branch with all the above mentioned fixes.

The remaining item is the display issue on Tegra30, which I'll go look at now.

Quoted 22 lines · Stephen Warren

Quoted 21 lines · Prashant Gaikwad

Quoted 20 lines · Stephen Warren

Quoted 8 lines · Stephen Warren

Quoted 7 lines · Prashant Gaikwad

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Quoted 7 lines

I think there are bugs here. I applied all your clock patches on top of Tegra's for-next (see list below), and found that the following don't work on Springbank:

* HDMI display
* Audio playback
* WiFi

(BTW, I stopped Cc'ing linux-kernel@, but added linux-tegra@ instead...)

Prashant, some updated testing results based off the "dev/ccf" branch you sent me on our internal git server:

Quoted 2 lines

...

Quoted 1 line

I have updated the internal branch with all the above mentioned fixes.

...

Quoted 2 lines

The remaining item is the display issue on Tegra30, which I'll go look at now.

The USB3 clock, which isn't used by any drivers on Tegra30, and hence was disabled at boot, was set up incorrectly and ended up mapping to the disp1 clock, and hence turned off the display. The following fixes it:

Quoted 6 lines

drivers/clk/tegra/clk-tegra30.c +0 -0

index f2f526e..0bac07c 100644
@@ -1541,7 +1541,7 @@ static void __init tegra30_periph_clk_init(void)
 

drivers/clk/tegra/clk-tegra30.c static void __init tegra30_periph_clk_init(void) · line 1546

Quoted 6 lines

drivers/clk/tegra/clk-tegra30.c +1 -1

  	/* usb3 */
  	clk = tegra_clk_periph_gate("usb3", "clk_m", 0, clk_base, 0, 59,
-				    &periph_l_regs, periph_clk_enb_refcnt);
+				    &periph_h_regs, periph_clk_enb_refcnt);
  	clk_register_clkdev(clk, NULL, "tegra-ehci.2");
  	clks[usb3] = clk;

I wonder if there are any other similar issues?

Quoted 29 lines · Stephen Warren

Quoted 27 lines · Stephen Warren

Quoted 24 lines · Prashant Gaikwad

Quoted 23 lines · Stephen Warren

Quoted 9 lines · Stephen Warren

Quoted 8 lines · Prashant Gaikwad

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Quoted 8 lines

I think there are bugs here. I applied all your clock patches on top of
Tegra's for-next (see list below), and found that the following don't work on Springbank:

* HDMI display
* Audio playback
* WiFi

(BTW, I stopped Cc'ing linux-kernel@, but added linux-tegra@ instead...)

Prashant, some updated testing results based off the "dev/ccf" branch you sent me on our internal git server:

...

Quoted 1 line

I have updated the internal branch with all the above mentioned fixes.

...

Quoted 5 lines

Quoted 2 lines

The remaining item is the display issue on Tegra30, which I'll go look at now.

The USB3 clock, which isn't used by any drivers on Tegra30, and hence was disabled at boot, was set up incorrectly and ended up mapping to the disp1 clock, and hence turned off the display. The following fixes it:

Stephen, thanks for the fix!! I have included this and PLLE fix; updated internal branch.

Quoted 32 lines · Prashant Gaikwad

Quoted 31 lines · Stephen Warren

Quoted 27 lines · Stephen Warren

Quoted 24 lines · Prashant Gaikwad

Quoted 23 lines · Stephen Warren

Quoted 9 lines · Stephen Warren

Quoted 8 lines · Prashant Gaikwad

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Quoted 8 lines

I think there are bugs here. I applied all your clock patches on top of
Tegra's for-next (see list below), and found that the following don't work on Springbank:

* HDMI display
* Audio playback
* WiFi

(BTW, I stopped Cc'ing linux-kernel@, but added linux-tegra@ instead...)

Prashant, some updated testing results based off the "dev/ccf" branch you sent me on our internal git server:

...

Quoted 1 line

I have updated the internal branch with all the above mentioned fixes.

...

Quoted 2 lines

The remaining item is the display issue on Tegra30, which I'll go look at now.

Quoted 6 lines

Quoted 3 lines

The USB3 clock, which isn't used by any drivers on Tegra30, and hence was disabled at boot, was set up incorrectly and ended up mapping to the disp1 clock, and hence turned off the display. The following fixes it:

Stephen, thanks for the fix!! I have included this and PLLE fix; updated internal branch.

Almost everything works great now.

Quoted 31 lines · Stephen Warren

Quoted 30 lines · Prashant Gaikwad

Quoted 29 lines · Stephen Warren

Quoted 27 lines · Stephen Warren

Quoted 24 lines · Prashant Gaikwad

Quoted 23 lines · Stephen Warren

Quoted 9 lines · Stephen Warren

Quoted 8 lines · Prashant Gaikwad

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Quoted 8 lines

I think there are bugs here. I applied all your clock patches on top of
Tegra's for-next (see list below), and found that the following don't work on Springbank:

* HDMI display
* Audio playback
* WiFi

(BTW, I stopped Cc'ing linux-kernel@, but added linux-tegra@ instead...)

Prashant, some updated testing results based off the "dev/ccf" branch you sent me on our internal git server:

...

Quoted 1 line

I have updated the internal branch with all the above mentioned fixes.

...

Quoted 8 lines

Quoted 7 lines

Quoted 5 lines

Quoted 2 lines

The remaining item is the display issue on Tegra30, which I'll go look at now.

The USB3 clock, which isn't used by any drivers on Tegra30, and hence was disabled at boot, was set up incorrectly and ended up mapping to the disp1 clock, and hence turned off the display. The following fixes it:

Stephen, thanks for the fix!! I have included this and PLLE fix; updated internal branch.

Almost everything works great now.

I noticed a couple more issues.

First, the clock rate rounding behaviour changes with your patch series for at least the I2C clocks.

With I2C, you specify how fast you want the bus to go. The bus shouldn't run any faster than that since the rate matches the max specification for the attached devices. So the clock framework should pick the smallest divider that yields a clock that doesn't exceed the request from clk_set_rate(). However, the new code seems to pick the smallest divider that yields at least the requested clock. I can certainly see that other clocks (say memory, CPU, or other internal performance-related clocks) might want to round the other way though.

The I2C driver sets its module clock to 8 times the desired bus rate. This yields a request of:

desired bus rate: 100 KHz
desired clock rate: 800 KHz
actual clock rate before your change: 800 KHz
actual clock rate after your change: 800 KHz
-> OK

desired bus rate: 400 KHz
desired clock rate: 3.2 MHz
actual clock rate before your change: 3 MHz (so 375 KHz bus rate, OK) actual clock rate after your change: 4 MHZ (so 500 KHz bus rate, BAD)

desired bus rate: 80 KHz (Toshiba AC100's nvec/I2C slave driver) desired clock rate: 640 KHz
actual clock rate before your change: ~632 KHz (so ~79 KHz bus rate, OK) actual clock rate after your change: ~706 KHz (so ~88 KHz bus rate, BAD)

Can this be fixed?

Second, the Toshiba AC100 uses an alternative driver for the I2C HW, since it operates in I2C slave mode. So, the DT node for that driver needs to include the clocks properties so the driver can get the clocks through DT:

arch/arm/boot/dts/tegra20-paz00.dts line 285

Quoted 13 lines

arch/arm/boot/dts/tegra20-paz00.dts +2 -0

index edef66c..6495425 100644
@@ -278,6 +278,8 @@
                 clock-frequency = <50000>;
                 request-gpios = <&gpio 170 0>; /* gpio PV2 */
                 slave-addr = <138>;
+               clocks = <&tegra_car 67>, <&tegra_car 124>;
+               clock-names = "div-clk", "fast-clk";
         };
 
         i2c at 7000d000 {

Your changes don't actually cause the driver to break though, since it abuses clk_get_sys() to retrieve clocks under a different driver name, which matches what the clock driver provides. However, I think you should also include the following patch at the end of your series to fix this up, so the clock looking happens through device tree:

Quoted 8 lines

drivers/staging/nvec/nvec.c +0 -0

index d8826ed..6d44076 100644
@@ -770,7 +770,7 @@ static int tegra_nvec_probe(struct platform_device *pdev)
                 return -ENODEV;
         }
 

drivers/staging/nvec/nvec.c static int tegra_nvec_probe(struct platform_device *pdev) · line 776

Quoted 5 lines

drivers/staging/nvec/nvec.c +1 -1

-       i2c_clk = clk_get_sys("tegra-i2c.2", "div-clk");
+       i2c_clk = clk_get(&pdev->dev, "div-clk");
         if (IS_ERR(i2c_clk)) {
                 dev_err(nvec->dev, "failed to get controller clock\n");
                 return -ENODEV;

Thanks.

Quoted 1 line · Stephen Warren

On 01/09/2013 10:34 AM, Stephen Warren wrote:

Quoted 41 lines

Second, the Toshiba AC100 uses an alternative driver for the I2C HW, since it operates in I2C slave mode. So, the DT node for that driver needs to include the clocks properties so the driver can get the clocks

through DT:

Quoted 13 lines

(quoted diff) +0 -0

b/arch/arm/boot/dts/tegra20-paz00.dts index edef66c..6495425 100644

arch/arm/boot/dts/tegra20-paz00.dts +2 -0

@@ -278,6 +278,8 @@
 
                 clock-frequency = <50000>;
                 request-gpios = <&gpio 170 0>; /* gpio PV2 */
                 slave-addr = <138>;
 
+               clocks = <&tegra_car 67>, <&tegra_car 124>;
+               clock-names = "div-clk", "fast-clk";
 

Quoted 3 lines

         };
         
         i2c at 7000d000 {

Your changes don't actually cause the driver to break though, since it abuses clk_get_sys() to retrieve clocks under a different driver name, which matches what the clock driver provides. However, I think you should also include the following patch at the end of your series to fix

this up, so the clock looking happens through device tree:

Quoted 13 lines

drivers/staging/nvec/nvec.c +1 -1

index d8826ed..6d44076 100644
@@ -770,7 +770,7 @@ static int tegra_nvec_probe(struct platform_device
 *pdev)>> 
                 return -ENODEV;
 
         }
 
-       i2c_clk = clk_get_sys("tegra-i2c.2", "div-clk");
+       i2c_clk = clk_get(&pdev->dev, "div-clk");
 

Quoted 4 lines

Quoted 4 lines

         if (IS_ERR(i2c_clk)) {
         
                 dev_err(nvec->dev, "failed to get controller clock\n");
                 return -ENODEV;

Included in the latest patches sent.

Quoted 2 lines · On Friday 11 January 2013 13:40:03 Prashant Gaikwad wrote:

Quoted 1 line · Stephen Warren

On 01/09/2013 10:34 AM, Stephen Warren wrote:

Quoted 19 lines

Quoted 19 lines

Your changes don't actually cause the driver to break though, since it abuses clk_get_sys() to retrieve clocks under a different driver name, which matches what the clock driver provides. However, I think you should also include the following patch at the end of your series to fix this up, so the clock looking happens through device tree:

Quoted 13 lines

drivers/staging/nvec/nvec.c +1 -1

index d8826ed..6d44076 100644
@@ -770,7 +770,7 @@ static int tegra_nvec_probe(struct platform_device
 *pdev)>> 
                 return -ENODEV;
 
         }
 
-       i2c_clk = clk_get_sys("tegra-i2c.2", "div-clk");
+       i2c_clk = clk_get(&pdev->dev, "div-clk");
 

Quoted 6 lines

Quoted 4 lines

Quoted 4 lines

         if (IS_ERR(i2c_clk)) {
         
                 dev_err(nvec->dev, "failed to get controller clock\n");
                 return -ENODEV;

Included in the latest patches sent.

em, not yet in V4.

Maybe you can also adjust the TODO (2nd entry) file now that this issue is fixed.

Quoted 3 lines · Marc Dietrich

Quoted 2 lines · On Friday 11 January 2013 13:40:03 Prashant Gaikwad wrote:

Quoted 1 line · Stephen Warren

On 01/09/2013 10:34 AM, Stephen Warren wrote:

...

Quoted 28 lines

Quoted 27 lines

Quoted 17 lines

Your changes don't actually cause the driver to break though, since it abuses clk_get_sys() to retrieve clocks under a different driver name, which matches what the clock driver provides. However, I think you should also include the following patch at the end of your series to fix

this up, so the clock looking happens through device tree:

Quoted 11 lines

drivers/staging/nvec/nvec.c +0 -0

index d8826ed..6d44076 100644
@@ -770,7 +770,7 @@ static int tegra_nvec_probe(struct platform_device
 *pdev)>>
 
                 return -ENODEV;
 
         }
 

Quoted 8 lines

Quoted 8 lines

drivers/staging/nvec/nvec.c +1 -1

-       i2c_clk = clk_get_sys("tegra-i2c.2", "div-clk");
+       i2c_clk = clk_get(&pdev->dev, "div-clk");

         if (IS_ERR(i2c_clk)) {
         
                 dev_err(nvec->dev, "failed to get controller
                 clock\n");
                 return -ENODEV;

Included in the latest patches sent.

Quoted 1 line

em, not yet in V4.

It's in V2 of the other series Prashant posted which sits on top of the CCF rework series.

Quoted 2 lines

Maybe you can also adjust the TODO (2nd entry) file now that this issue is fixed.

I'll try to remember to repost an updated version of the patch which does that...

Quoted 30 lines · Prashant Gaikwad

Quoted 29 lines · Stephen Warren

Quoted 27 lines · Stephen Warren

Quoted 24 lines · Prashant Gaikwad

Quoted 23 lines · Stephen Warren

Quoted 9 lines · Stephen Warren

Quoted 8 lines · Prashant Gaikwad

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Quoted 8 lines

I think there are bugs here. I applied all your clock patches on top of
Tegra's for-next (see list below), and found that the following don't work on Springbank:

* HDMI display
* Audio playback
* WiFi

(BTW, I stopped Cc'ing linux-kernel@, but added linux-tegra@ instead...)

Prashant, some updated testing results based off the "dev/ccf" branch you sent me on our internal git server:

...

Quoted 1 line

I have updated the internal branch with all the above mentioned fixes.

...

Quoted 7 lines

Quoted 5 lines

Quoted 2 lines

The remaining item is the display issue on Tegra30, which I'll go look at now.

The USB3 clock, which isn't used by any drivers on Tegra30, and hence was disabled at boot, was set up incorrectly and ended up mapping to the disp1 clock, and hence turned off the display. The following fixes it:

Stephen, thanks for the fix!! I have included this and PLLE fix; updated internal branch.

Almost everything works great now.

However, I don't see any fix for the PLLE issue in the code; if there is one it certainly doesn't work. Applying my previous hack makes it work.

FYI, the branch I tested with is at
git://nv-tegra.nvidia.com/user/swarren/linux-2.6 test-ccf-rework-2

It's rebased onto the latest Tegra for-next.