clk: exynos4: migrate to common clock framework
Subsystems (6)
v5 cover clk: exynos4: migrate to common clock framework
Changes since v4:
- Rebased to linux-3.8-rc1.
Changes since v3:
- Includes changes suggested by Tomasz Figa <[email protected]>
This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms.
This patch series depends on this series:
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg14471.html and this patch
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg14472.html
Thomas Abraham (12):
clk: samsung: add common clock framework helper functions for Samsung platforms
clk: samsung: add pll clock registration helper functions
clk: exynos4: register clocks using common clock framework
ARM: Exynos: Rework timer initialization sequence
ARM: Exynos4: Migrate clock support to common clock framework
ARM: dts: add exynos4 clock controller nodes
ARM: dts: add xxti and xusbxti fixed rate clock nodes for exynos4 based platforms
ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed
ARM: dts: add clock provider information for all controllers in Exynos4 SoC
ARM: Exynos4: remove auxdata table from machine file
ARM: Exynos: use fin_pll clock as the tick clock source for mct
ARM: Exynos: add support for mct clock setup
.../devicetree/bindings/clock/exynos4-clock.txt | 215 +++++++ arch/arm/boot/dts/exynos4.dtsi | 50 ++ arch/arm/boot/dts/exynos4210-origen.dts | 12 + arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 + arch/arm/boot/dts/exynos4210.dtsi | 6 + arch/arm/boot/dts/exynos4412-origen.dts | 12 + arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 + arch/arm/boot/dts/exynos4x12.dtsi | 6 + arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/Makefile | 3 - arch/arm/mach-exynos/clock-exynos4.h | 35 - arch/arm/mach-exynos/clock-exynos4210.c | 188 ------ arch/arm/mach-exynos/clock-exynos4212.c | 192 ------ arch/arm/mach-exynos/common.c | 57 ++- arch/arm/mach-exynos/common.h | 21 +- arch/arm/mach-exynos/mach-armlex4210.c | 3 +- arch/arm/mach-exynos/mach-exynos4-dt.c | 72 +-- arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +- arch/arm/mach-exynos/mach-nuri.c | 5 +- arch/arm/mach-exynos/mach-origen.c | 5 +- arch/arm/mach-exynos/mach-smdk4x12.c | 5 +- arch/arm/mach-exynos/mach-smdkv310.c | 7 +- arch/arm/mach-exynos/mach-universal_c210.c | 3 +- arch/arm/mach-exynos/mct.c | 32 +- arch/arm/plat-samsung/Kconfig | 4 +- drivers/clk/Makefile | 1 + drivers/clk/samsung/Makefile | 6 + drivers/clk/samsung/clk-exynos4.c | 655 ++++++++++++++++++++ drivers/clk/samsung/clk-pll.c | 400 ++++++++++++ drivers/clk/samsung/clk-pll.h | 38 ++ drivers/clk/samsung/clk.c | 180 ++++++ drivers/clk/samsung/clk.h | 216 +++++++ 32 files changed, 1919 insertions(+), 537 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt delete mode 100644 arch/arm/mach-exynos/clock-exynos4.h delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c create mode 100644 drivers/clk/samsung/Makefile create mode 100644 drivers/clk/samsung/clk-exynos4.c create mode 100644 drivers/clk/samsung/clk-pll.c create mode 100644 drivers/clk/samsung/clk-pll.h create mode 100644 drivers/clk/samsung/clk.c create mode 100644 drivers/clk/samsung/clk.h
Signature · 1 line
1.7.5.4
PATCH v5 1/12 clk: samsung: add common clock framework helper functions for Samsung platforms
All Samsung platforms include different types of clock including fixed-rate, mux, divider and gate clock types. There are typically hundreds of such clocks on each of the Samsung platforms. To enable Samsung platforms to register these clocks using the common clock framework, a bunch of utility functions are introduced here which simplify the clock registration process. The clocks are usually statically instantiated and registered with common clock framework.
--- drivers/clk/Makefile | 1 + drivers/clk/samsung/Makefile | 5 + drivers/clk/samsung/clk.c | 180 +++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk.h | 216 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 402 insertions(+), 0 deletions(-) create mode 100644 drivers/clk/samsung/Makefile create mode 100644 drivers/clk/samsung/clk.c create mode 100644 drivers/clk/samsung/clk.h
drivers/clk/Makefile +1 -0
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o +obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ # Chip specific obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
drivers/clk/samsung/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +# +# Samsung Clock specific Makefile +# + +obj-$(CONFIG_COMMON_CLK) += clk.o
drivers/clk/samsung/clk.c new file +180 -0
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drivers/clk/samsung/clk.h new file +216 -0
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Signature · 1 line
1.7.5.4
PATCH v5 2/12 clk: samsung: add pll clock registration helper functions
In reply to Thomas AbrahamThere are several types of pll clocks used in Samsung SoC's and these pll clocks can be represented as Samsung specific pll clock types and registered with the common clock framework. Add support for pll35xx, pll36xx, pll45xx and pll46xx clock types and helper functions to register them.
--- drivers/clk/samsung/Makefile | 2 +- drivers/clk/samsung/clk-pll.c | 400 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 38 ++++ 3 files changed, 439 insertions(+), 1 deletions(-) create mode 100644 drivers/clk/samsung/clk-pll.c create mode 100644 drivers/clk/samsung/clk-pll.h
drivers/clk/samsung/Makefile +1 -1
@@ -2,4 +2,4 @@ # Samsung Clock specific Makefile # -obj-$(CONFIG_COMMON_CLK) += clk.o +obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
drivers/clk/samsung/clk-pll.c new file +400 -0
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drivers/clk/samsung/clk-pll.h new file +38 -0
@@ -0,0 +1,38 @@ +/* +* Copyright (c) 2012 Samsung Electronics Co., Ltd. +* Copyright (c) 2012 Linaro Ltd. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* Common Clock Framework support for all Samsung platforms +*/ + +#ifndef __SAMSUNG_CLK_PLL_H +#define __SAMSUNG_CLK_PLL_H + +enum pll45xx_type { + pll_4500, + pll_4502, + pll_4508 +}; + +enum pll46xx_type { + pll_4600, + pll_4650, + pll_4650c, +}; + +extern struct clk *__init samsung_clk_register_pll35xx (const char *name, +const char *pname,const void __iomem *con_reg); +extern struct clk *__init samsung_clk_register_pll36xx (const char *name, +const char *pname,const void __iomem *con_reg); +extern struct clk *__init samsung_clk_register_pll45xx (const char *name, +const char *pname,const void __iomem *con_reg, +enum pll45xx_type type); +extern struct clk *__init samsung_clk_register_pll46xx (const char *name, +const char *pname,const void __iomem *con_reg, +enum pll46xx_type type); + +#endif /* __SAMSUNG_CLK_PLL_H */
Signature · 1 line
1.7.5.4
PATCH v5 3/12 clk: exynos4: register clocks using common clock framework
In reply to Thomas AbrahamThe Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported.
--- .../devicetree/bindings/clock/exynos4-clock.txt | 215 +++++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos4.c | 655 ++++++++++++++++++++ 3 files changed, 871 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos4.c
Documentation/devicetree/bindings/clock/exynos4-clock.txt new file +215 -0
@@ -0,0 +1,215 @@ +* Samsung Exynos4 Clock Controller + +The Exynos4 clock controller generates and supplies clock to various controllers +within the Exynos4 SoC. The clock binding described here is applicable to all +SoC's in the Exynos4 family. + +Required Properties: + +- comptible: should be one of the following. + - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. + - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. Some of the clocks are available only on a particular +Exynos4 SoC and this is specified where applicable. + + + [Core Clocks] + + Clock ID SoC (if specific) + ----------------------------------------------- + + xxti 1 + xusbxti 2 + fin_pll 3 + fout_apll 4 + fout_mpll 5 + fout_epll 6 + fout_vpll 7 + sclk_apll 8 + sclk_mpll 9 + sclk_epll 10 + sclk_vpll 11 + arm_clk 12 + aclk200 13 + aclk100 14 + aclk160 15 + aclk133 16 + + + [Clock Gate for Special Clocks] + + Clock ID SoC (if specific) + ----------------------------------------------- + + sclk_fimc0 128 + sclk_fimc1 129 + sclk_fimc2 130 + sclk_fimc3 131 + sclk_cam0 132 + sclk_cam1 133 + sclk_csis0 134 + sclk_csis1 135 + sclk_hdmi 136 + sclk_mixer 137 + sclk_dac 138 + sclk_pixel 139 + sclk_fimd0 140 + sclk_mdnie0 141 Exynos4412 + sclk_mdnie_pwm0 12 142 Exynos4412 + sclk_mipi0 143 + sclk_audio0 144 + sclk_mmc0 145 + sclk_mmc1 146 + sclk_mmc2 147 + sclk_mmc3 148 + sclk_mmc4 149 + sclk_sata 150 Exynos4210 + sclk_uart0 151 + sclk_uart1 152 + sclk_uart2 153 + sclk_uart3 154 + sclk_uart4 155 + sclk_audio1 156 + sclk_audio2 157 + sclk_spdif 158 + sclk_spi0 159 + sclk_spi1 160 + sclk_spi2 161 + sclk_slimbus 162 + sclk_fimd1 163 Exynos4210 + sclk_mipi1 164 Exynos4210 + sclk_pcm1 165 + sclk_pcm2 166 + sclk_i2s1 167 + sclk_i2s2 168 + sclk_mipihsi 169 Exynos4412 + + + [Peripheral Clock Gates] + + Clock ID SoC (if specific) + ----------------------------------------------- + + fimc0 256 + fimc1 257 + fimc2 258 + fimc3 259 + csis0 260 + csis1 261 + jpeg 262 + smmu_fimc0 263 + smmu_fimc1 264 + smmu_fimc2 265 + smmu_fimc3 266 + smmu_jpeg 267 + vp 268 + mixer 269 + tvenc 270 Exynos4210 + hdmi 271 + smmu_tv 272 + mfc 273 + smmu_mfcl 274 + smmu_mfcr 275 + g3d 276 + g2d 277 Exynos4210 + rotator 278 Exynos4210 + mdma 279 Exynos4210 + smmu_g2d 280 Exynos4210 + smmu_rotator 281 Exynos4210 + smmu_mdma 282 Exynos4210 + fimd0 283 + mie0 284 + mdnie0 285 Exynos4412 + dsim0 286 + smmu_fimd0 287 + fimd1 288 Exynos4210 + mie1 289 Exynos4210 + dsim1 290 Exynos4210 + smmu_fimd1 291 Exynos4210 + pdma0 292 + pdma1 293 + pcie_phy 294 + sata_phy 295 Exynos4210 + tsi 296 + sdmmc0 297 + sdmmc1 298 + sdmmc2 299 + sdmmc3 300 + sdmmc4 301 + sata 302 Exynos4210 + sromc 303 + usb_host 304 + usb_device 305 + pcie 306 + onenand 307 + nfcon 308 + smmu_pcie 309 + gps 310 + smmu_gps 311 + uart0 312 + uart1 313 + uart2 314 + uart3 315 + uart4 316 + i2c0 317 + i2c1 318 + i2c2 319 + i2c3 320 + i2c4 321 + i2c5 322 + i2c6 323 + i2c7 324 + i2c_hdmi 325 + tsadc 326 + spi0 327 + spi1 328 + spi2 329 + i2s1 330 + i2s2 331 + pcm0 332 + i2s0 333 + pcm1 334 + pcm2 335 + pwm 336 + slimbus 337 + spdif 338 + ac97 339 + modemif 340 + chipid 341 + sysreg 342 + hdmi_cec 343 + mct 344 + wdt 345 + rtc 346 + keyif 347 + audss 348 + mipi_hsi 349 Exynos4210 + mdma2 350 Exynos4210 + +Example 1: An example of a clock controller node is listed below. + + clock: clock-controller at 0x10030000 { + compatible = "samsung,exynos4210-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the clock + controller. Refer to the standard clock bindings for information + about 'clocks' and 'clock-names' property. + + serial at 13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 54 0>; + clocks = <&clock 314>, <&clock 153>; + clock-names = "uart", "clk_uart_baud0"; + };
drivers/clk/samsung/Makefile +1 -0
@@ -3,3 +3,4 @@ # obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o +obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
drivers/clk/samsung/clk-exynos4.c new file +655 -0
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Signature · 1 line
1.7.5.4
PATCH v5 4/12 ARM: Exynos: Rework timer initialization sequence
In reply to Thomas AbrahamA seperate timer initialization function for all exynos based platforms is created. This new initialization function will help to identify the type of timer used and call their corresponding initialization function. Since the clock initialization should be completed prior to the mct timer initialization, the clock initialization can be initiated from this new timer initialization function.
--- arch/arm/mach-exynos/common.c | 27 +++++++++++++++++++++++++++ arch/arm/mach-exynos/common.h | 3 ++- arch/arm/mach-exynos/mach-armlex4210.c | 2 +- arch/arm/mach-exynos/mach-exynos4-dt.c | 2 +- arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +- arch/arm/mach-exynos/mach-nuri.c | 2 +- arch/arm/mach-exynos/mach-origen.c | 2 +- arch/arm/mach-exynos/mach-smdk4x12.c | 4 ++-- arch/arm/mach-exynos/mach-smdkv310.c | 4 ++-- arch/arm/mach-exynos/mct.c | 13 +------------ 10 files changed, 39 insertions(+), 22 deletions(-)
arch/arm/mach-exynos/common.c +27 -0
@@ -24,6 +24,8 @@#include <linux/irqdomain.h> #include <linux/of_address.h> +#include <asm/mach/time.h> +#include <asm/arch_timer.h> #include <asm/proc-fns.h> #include <asm/exception.h> #include <asm/hardware/cache-l2x0.h>
@@ -462,6 +464,31 @@ static void __init exynos5_init_clocks(int xtal)exynos5_setup_clocks (); } +void __init exynos_timer_init (void ) +{ +/* +* Temporary support for Exynos4 based non-dt platforms. This should +* go away soon. +*/ +if (!of_have_populated_dt () && (soc_is_exynos4210 () || +soc_is_exynos4212 () ||soc_is_exynos4412 ())) { +exynos_mct_init (); +return ; + } + +/* quick check to see if this machine uses arch timer */ +if (of_machine_is_compatible ("samsung,exynos5440" )) { +if (arch_timer_of_register ()) +panic ("%s: could not initialize timer\n" , __func__); + }else { +exynos_mct_init (); + } +} + +struct sys_timer exynos_timer = { + .init = exynos_timer_init, +}; +#define COMBINER_ENABLE_SET 0x0#define COMBINER_ENABLE_CLEAR 0x4#define COMBINER_INT_STATUS 0xC
arch/arm/mach-exynos/common.h +2 -1
@@ -12,7 +12,7 @@#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H#define __ARCH_ARM_MACH_EXYNOS_COMMON_H -extern struct sys_timer exynos4_timer; +extern struct sys_timer exynos_timer;struct map_desc ;void exynos_init_io (struct map_desc *mach_desc,int size);
@@ -21,6 +21,7 @@ void exynos5_init_irq(void);void exynos4_restart (char mode,const char *cmd);void exynos5_restart (char mode,const char *cmd);void exynos_init_late (void ); +extern void exynos_mct_init (void );void exynos_firmware_init (void );
arch/arm/mach-exynos/mach-armlex4210.c +1 -1
@@ -204,6 +204,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210") .handle_irq = gic_handle_irq, .init_machine = armlex4210_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .timer = &exynos_timer, .restart = exynos4_restart,MACHINE_END
arch/arm/mach-exynos/mach-exynos4-dt.c +1 -1
@@ -111,7 +111,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") .init_early = exynos_firmware_init, .init_machine = exynos4_dt_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .timer = &exynos_timer, .dt_compat = exynos4_dt_compat, .restart = exynos4_restart,MACHINE_END
arch/arm/mach-exynos/mach-exynos5-dt.c +1 -1
@@ -182,7 +182,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") .handle_irq = gic_handle_irq, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .timer = &exynos_timer, .dt_compat = exynos5_dt_compat, .restart = exynos5_restart, .reserve = exynos5_reserve,
arch/arm/mach-exynos/mach-nuri.c +1 -1
@@ -1382,7 +1382,7 @@ MACHINE_START(NURI, "NURI") .handle_irq = gic_handle_irq, .init_machine = nuri_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .timer = &exynos_timer, .reserve = &nuri_reserve, .restart = exynos4_restart,MACHINE_END
arch/arm/mach-exynos/mach-origen.c +1 -1
@@ -817,7 +817,7 @@ MACHINE_START(ORIGEN, "ORIGEN") .handle_irq = gic_handle_irq, .init_machine = origen_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .timer = &exynos_timer, .reserve = &origen_reserve, .restart = exynos4_restart,MACHINE_END
arch/arm/mach-exynos/mach-smdk4x12.c +2 -2
@@ -378,7 +378,7 @@ MACHINE_START(SMDK4212, "SMDK4212") .map_io = smdk4x12_map_io, .handle_irq = gic_handle_irq, .init_machine = smdk4x12_machine_init, - .timer = &exynos4_timer, + .timer = &exynos_timer, .restart = exynos4_restart, .reserve = &smdk4x12_reserve,MACHINE_END
@@ -393,7 +393,7 @@ MACHINE_START(SMDK4412, "SMDK4412") .handle_irq = gic_handle_irq, .init_machine = smdk4x12_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .timer = &exynos_timer, .restart = exynos4_restart, .reserve = &smdk4x12_reserve,MACHINE_END
arch/arm/mach-exynos/mach-smdkv310.c +2 -2
@@ -425,7 +425,7 @@ MACHINE_START(SMDKV310, "SMDKV310") .map_io = smdkv310_map_io, .handle_irq = gic_handle_irq, .init_machine = smdkv310_machine_init, - .timer = &exynos4_timer, + .timer = &exynos_timer, .reserve = &smdkv310_reserve, .restart = exynos4_restart,MACHINE_END
@@ -439,7 +439,7 @@ MACHINE_START(SMDKC210, "SMDKC210") .handle_irq = gic_handle_irq, .init_machine = smdkv310_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .timer = &exynos_timer, .reserve = &smdkv310_reserve, .restart = exynos4_restart,MACHINE_END
arch/arm/mach-exynos/mct.c +1 -12
@@ -23,7 +23,6 @@#include <linux/of_irq.h> #include <linux/of_address.h> -#include <asm/arch_timer.h> #include <asm/hardware/gic.h> #include <asm/localtimer.h>
@@ -31,7 +30,6 @@#include <mach/map.h> #include <mach/irqs.h> -#include <asm/mach/time.h> #define EXYNOS4_MCTREG (x) (x)#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
@@ -513,16 +511,11 @@ static void __init exynos4_timer_resources(struct device_node *np)#endif /* CONFIG_LOCAL_TIMERS */ } -static void __init exynos_timer_init (void ) +void __init exynos_mct_init (void ) {struct device_node *np;u32 nr_irqs, i; -if (soc_is_exynos5440 ()) { -arch_timer_of_register (); -return ; - } - np =of_find_compatible_node (NULL ,NULL ,"samsung,exynos4210-mct" );if (np) { if (of_machine_is_compatible("samsung,exynos4210") ||
@@ -551,7 +544,3 @@ static void __init exynos_timer_init(void)exynos4_clocksource_init ();exynos4_clockevent_init (); } - -struct sys_timer exynos4_timer = { - .init = exynos_timer_init, -};
Signature · 1 line
1.7.5.4
PATCH v5 5/12 ARM: Exynos4: Migrate clock support to common clock framework
In reply to Thomas AbrahamRemove Samsung specific clock support in Exynos4 and migrate to use common clock framework.
--- arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/Makefile | 3 - arch/arm/mach-exynos/clock-exynos4.h | 35 ----- arch/arm/mach-exynos/clock-exynos4210.c | 188 --------------------------- arch/arm/mach-exynos/clock-exynos4212.c | 192 ---------------------------- arch/arm/mach-exynos/common.c | 27 +--- arch/arm/mach-exynos/common.h | 17 +++ arch/arm/mach-exynos/mach-armlex4210.c | 1 - arch/arm/mach-exynos/mach-exynos4-dt.c | 1 - arch/arm/mach-exynos/mach-nuri.c | 1 - arch/arm/mach-exynos/mach-origen.c | 1 - arch/arm/mach-exynos/mach-smdk4x12.c | 1 - arch/arm/mach-exynos/mach-smdkv310.c | 1 - arch/arm/mach-exynos/mach-universal_c210.c | 1 - arch/arm/plat-samsung/Kconfig | 4 +- 15 files changed, 27 insertions(+), 447 deletions(-) delete mode 100644 arch/arm/mach-exynos/clock-exynos4.h delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c
arch/arm/mach-exynos/Kconfig +1 -0
@@ -15,6 +15,7 @@ config ARCH_EXYNOS4 bool "SAMSUNG EXYNOS4" default y select HAVE_SMP + select COMMON_CLK select MIGHT_HAVE_CACHE_L2X0 help Samsung EXYNOS4 SoCs based systems
arch/arm/mach-exynos/Makefile +0 -3
@@ -13,9 +13,6 @@ obj- := # Core obj-$(CONFIG_ARCH_EXYNOS) += common.o -obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o -obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o -obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o obj-$(CONFIG_PM) += pm.o
arch/arm/mach-exynos/clock-exynos4.h deleted +0 -35
@@ -1,35 +0,0 @@ -/* -* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. -* http://www.samsung.com -* -* Header file for exynos4 clock support -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H __FILE__ - -#include <linux/clk.h> - -extern struct clksrc_clk exynos4_clk_aclk_133; -extern struct clksrc_clk exynos4_clk_mout_mpll; - -extern struct clksrc_sources exynos4_clkset_mout_corebus; -extern struct clksrc_sources exynos4_clkset_group; - -extern struct clk *exynos4_clkset_aclk_top_list[]; -extern struct clk *exynos4_clkset_group_list[]; - -extern struct clksrc_sources exynos4_clkset_mout_g2d0; -extern struct clksrc_sources exynos4_clkset_mout_g2d1; - -extern int exynos4_clksrc_mask_fsys_ctrl (struct clk *clk,int enable); -extern int exynos4_clk_ip_fsys_ctrl (struct clk *clk,int enable); -extern int exynos4_clk_ip_lcd1_ctrl (struct clk *clk,int enable); -extern int exynos4_clk_ip_image_ctrl (struct clk *clk,int enable); -extern int exynos4_clk_ip_dmc_ctrl (struct clk *clk,int enable); - -#endif /* __ASM_ARCH_CLOCK_H */
arch/arm/mach-exynos/clock-exynos4210.c deleted +0 -188
188 lines not on this page · raw message
arch/arm/mach-exynos/clock-exynos4212.c deleted +0 -192
192 lines not on this page · raw message
arch/arm/mach-exynos/common.c +7 -20
@@ -67,7 +67,6 @@ static const char name_exynos5440[] = "EXYNOS5440";static void exynos4_map_io (void );static void exynos5_map_io (void );static void exynos5440_map_io (void ); -static void exynos4_init_clocks (int xtal);static void exynos5_init_clocks (int xtal);static void exynos4_init_uarts (struct s3c2410_uartcfg *cfg,int no);static int exynos_init (void );
@@ -77,7 +76,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = EXYNOS4210_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, - .init_clocks = exynos4_init_clocks, .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4210,
@@ -85,7 +83,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = EXYNOS4212_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, - .init_clocks = exynos4_init_clocks, .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4212,
@@ -93,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = EXYNOS4412_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, - .init_clocks = exynos4_init_clocks, .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4412,
@@ -432,22 +428,6 @@ static void __init exynos5_map_io(void)iotable_init (exynos5250_iodesc,ARRAY_SIZE (exynos5250_iodesc)); } -static void __init exynos4_init_clocks (int xtal) -{ -printk (KERN_DEBUG "%s: initializing clocks\n" , __func__); - -s3c24xx_register_baseclocks (xtal); -s5p_register_clocks (xtal); - -if (soc_is_exynos4210 ()) -exynos4210_register_clocks (); -else if (soc_is_exynos4212 () ||soc_is_exynos4412 ()) -exynos4212_register_clocks (); - -exynos4_register_clocks (); -exynos4_setup_clocks (); -} -static void __init exynos5440_map_io (void ) {iotable_init (exynos5440_iodesc0,ARRAY_SIZE (exynos5440_iodesc0));
@@ -455,6 +435,7 @@ static void __init exynos5440_map_io(void)static void __init exynos5_init_clocks (int xtal) { +#ifndef CONFIG_COMMON_CLK printk (KERN_DEBUG "%s: initializing clocks\n" , __func__);s3c24xx_register_baseclocks (xtal);
@@ -462,6 +443,7 @@ static void __init exynos5_init_clocks(int xtal)exynos5_register_clocks ();exynos5_setup_clocks (); +#endif }void __init exynos_timer_init (void )
@@ -472,6 +454,7 @@ void __init exynos_timer_init(void)*/ if (!of_have_populated_dt () && (soc_is_exynos4210 () ||soc_is_exynos4212 () ||soc_is_exynos4412 ())) { +exynos4_clk_init ();exynos_mct_init ();return ; }
@@ -481,6 +464,10 @@ void __init exynos_timer_init(void)if (arch_timer_of_register ())panic ("%s: could not initialize timer\n" , __func__); }else { +if (of_machine_is_compatible ("samsung,exynos4210" ) || +of_machine_is_compatible ("samsung,exynos4212" ) || +of_machine_is_compatible ("samsung,exynos4412" )) +exynos4_clk_init ();exynos_mct_init (); } }
arch/arm/mach-exynos/common.h +17 -0
@@ -23,6 +23,23 @@ void exynos5_restart(char mode, const char *cmd);void exynos_init_late (void );extern void exynos_mct_init (void ); +#ifdef CONFIG_COMMON_CLK +extern void exynos4_clk_init (void ); +extern void exynos4_clk_register_fixed_ext (unsigned long ,unsigned long ); +#else +/* todo: remove these after adding common clock support for exynos5 platforms */ +static inline void exynos4_clk_init (void ) +{ +return ; +} + +static inline void exynos4_clk_register_fixed_ext (unsigned long xxti_f, +unsigned long xusbxti) +{ +return ; +} +#endif +void exynos_firmware_init (void );#ifdef CONFIG_PM_GENERIC_DOMAINS
arch/arm/mach-exynos/mach-armlex4210.c +0 -1
@@ -178,7 +178,6 @@ static void __init armlex4210_smsc911x_init(void)static void __init armlex4210_map_io (void ) {exynos_init_io (NULL ,0 ); -s3c24xx_init_clocks (24000000 );s3c24xx_init_uarts (armlex4210_uartcfgs,ARRAY_SIZE (armlex4210_uartcfgs)); }
arch/arm/mach-exynos/mach-exynos4-dt.c +0 -1
@@ -86,7 +86,6 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {static void __init exynos4_dt_map_io (void ) {exynos_init_io (NULL ,0 ); -s3c24xx_init_clocks (24000000 ); }static void __init exynos4_dt_machine_init (void )
arch/arm/mach-exynos/mach-nuri.c +0 -1
@@ -1331,7 +1331,6 @@ static struct platform_device *nuri_devices[] __initdata = {static void __init nuri_map_io (void ) {exynos_init_io (NULL ,0 ); -s3c24xx_init_clocks (clk_xusbxti.rate);s3c24xx_init_uarts (nuri_uartcfgs,ARRAY_SIZE (nuri_uartcfgs)); }
arch/arm/mach-exynos/mach-origen.c +0 -1
@@ -755,7 +755,6 @@ static void s5p_tv_setup(void)static void __init origen_map_io (void ) {exynos_init_io (NULL ,0 ); -s3c24xx_init_clocks (clk_xusbxti.rate);s3c24xx_init_uarts (origen_uartcfgs,ARRAY_SIZE (origen_uartcfgs)); }
arch/arm/mach-exynos/mach-smdk4x12.c +0 -1
@@ -323,7 +323,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {static void __init smdk4x12_map_io (void ) {exynos_init_io (NULL ,0 ); -s3c24xx_init_clocks (clk_xusbxti.rate);s3c24xx_init_uarts (smdk4x12_uartcfgs,ARRAY_SIZE (smdk4x12_uartcfgs)); }
arch/arm/mach-exynos/mach-smdkv310.c +0 -1
@@ -372,7 +372,6 @@ static void s5p_tv_setup(void)static void __init smdkv310_map_io (void ) {exynos_init_io (NULL ,0 ); -s3c24xx_init_clocks (clk_xusbxti.rate);s3c24xx_init_uarts (smdkv310_uartcfgs,ARRAY_SIZE (smdkv310_uartcfgs)); }
arch/arm/mach-exynos/mach-universal_c210.c +0 -1
@@ -1093,7 +1093,6 @@ static struct platform_device *universal_devices[] __initdata = {static void __init universal_map_io (void ) {exynos_init_io (NULL ,0 ); -s3c24xx_init_clocks (clk_xusbxti.rate);s3c24xx_init_uarts (universal_uartcfgs,ARRAY_SIZE (universal_uartcfgs));s5p_set_timer_source (S5P_PWM2 ,S5P_PWM4 ); }
arch/arm/plat-samsung/Kconfig +2 -2
@@ -25,7 +25,7 @@ config PLAT_S5P select PLAT_SAMSUNG select S3C_GPIO_TRACK select S5P_GPIO_DRVSTR - select SAMSUNG_CLKSRC + select SAMSUNG_CLKSRC if !COMMON_CLK select SAMSUNG_GPIOLIB_4BIT select SAMSUNG_IRQ_VIC_TIMER help
@@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC used by newer systems such as the S3C64XX. config S5P_CLOCK - def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) + def_bool ((ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) && !COMMON_CLK) help Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
Signature · 1 line
1.7.5.4
PATCH v5 6/12 ARM: dts: add exynos4 clock controller nodes
In reply to Thomas AbrahamAdd clock controller nodes for Exynos4210 and Exynos4x12 SoC's.
--- arch/arm/boot/dts/exynos4210.dtsi | 6 ++++++ arch/arm/boot/dts/exynos4x12.dtsi | 6 ++++++ 2 files changed, 12 insertions(+), 0 deletions(-)
arch/arm/boot/dts/exynos4210.dtsi +6 -0
@@ -55,6 +55,12 @@ samsung,mct-nr-local-irqs = <4>; }; + clock: clock-controller at 0x10030000 { + compatible = "samsung,exynos4210-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&combiner>;
arch/arm/boot/dts/exynos4x12.dtsi +6 -0
@@ -36,6 +36,12 @@ <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>; }; + clock: clock-controller at 0x10030000 { + compatible = "samsung,exynos4412-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + pinctrl_0: pinctrl at 11400000 { compatible = "samsung,pinctrl-exynos4x12"; reg = <0x11400000 0x1000>;
Signature · 1 line
1.7.5.4
PATCH v5 7/12 ARM: dts: add xxti and xusbxti fixed rate clock nodes for exynos4 based platforms
In reply to Thomas AbrahamThe clock frequency of xxti and xusbxti clocks is dependent on the frequency of the on-board oscillator that is used to generate these clocks. So allow the frequency of these clocks to be specfied from device tree.
--- arch/arm/boot/dts/exynos4210-origen.dts | 12 ++++++++++++ arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 ++++++++++++ arch/arm/boot/dts/exynos4412-origen.dts | 12 ++++++++++++ arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 ++++++++++++ 4 files changed, 48 insertions(+), 0 deletions(-)
arch/arm/boot/dts/exynos4210-origen.dts +12 -0
@@ -121,4 +121,16 @@ linux,default-trigger = "heartbeat"; }; }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti", "fixed-clock"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; };
arch/arm/boot/dts/exynos4210-smdkv310.dts +12 -0
@@ -189,4 +189,16 @@ }; }; }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti", "fixed-clock"; + clock-frequency = <12000000>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; };
arch/arm/boot/dts/exynos4412-origen.dts +12 -0
@@ -42,4 +42,16 @@ serial at 13830000 { status = "okay"; }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti", "fixed-clock"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; };
arch/arm/boot/dts/exynos4412-smdk4412.dts +12 -0
@@ -42,4 +42,16 @@ serial at 13830000 { status = "okay"; }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti", "fixed-clock"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; };
Signature · 1 line
1.7.5.4
PATCH v5 8/12 ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed
In reply to Thomas AbrahamThe clock speed of xxti and xusbxti clocks depends on the oscillator used on the board to generate these clocks. For non-dt platforms, allow the board support for those platforms to set the clock frequency of xxti and xusbxti clocks.
--- arch/arm/mach-exynos/common.c | 3 +++ arch/arm/mach-exynos/common.h | 1 + arch/arm/mach-exynos/mach-nuri.c | 2 ++ arch/arm/mach-exynos/mach-origen.c | 2 ++ arch/arm/mach-exynos/mach-smdkv310.c | 2 ++ arch/arm/mach-exynos/mach-universal_c210.c | 2 ++ 6 files changed, 12 insertions(+), 0 deletions(-)
arch/arm/mach-exynos/common.c +3 -0
@@ -71,6 +71,8 @@ static void exynos5_init_clocks(int xtal);static void exynos4_init_uarts (struct s3c2410_uartcfg *cfg,int no);static int exynos_init (void ); +unsigned long xxti_f =0 , xusbxti_f =0 ; +static struct cpu_table cpu_ids[]__initdata = { { .idcode =EXYNOS4210_CPU_ID ,
@@ -455,6 +457,7 @@ void __init exynos_timer_init(void)if (!of_have_populated_dt () && (soc_is_exynos4210 () ||soc_is_exynos4212 () ||soc_is_exynos4412 ())) {exynos4_clk_init (); +exynos4_clk_register_fixed_ext (xxti_f, xusbxti_f);exynos_mct_init ();return ; }
arch/arm/mach-exynos/common.h +1 -0
@@ -24,6 +24,7 @@ void exynos_init_late(void);extern void exynos_mct_init (void );#ifdef CONFIG_COMMON_CLK +extern unsigned long xxti_f, xusbxti_f;extern void exynos4_clk_init (void );extern void exynos4_clk_register_fixed_ext (unsigned long ,unsigned long );#else
arch/arm/mach-exynos/mach-nuri.c +2 -0
@@ -1332,6 +1332,8 @@ static void __init nuri_map_io(void) {exynos_init_io (NULL ,0 );s3c24xx_init_uarts (nuri_uartcfgs,ARRAY_SIZE (nuri_uartcfgs)); + xxti_f =0 ; + xusbxti_f =24000000 ; }static void __init nuri_reserve (void )
arch/arm/mach-exynos/mach-origen.c +2 -0
@@ -756,6 +756,8 @@ static void __init origen_map_io(void) {exynos_init_io (NULL ,0 );s3c24xx_init_uarts (origen_uartcfgs,ARRAY_SIZE (origen_uartcfgs)); + xxti_f =0 ; + xusbxti_f =24000000 ; }static void __init origen_power_init (void )
arch/arm/mach-exynos/mach-smdkv310.c +2 -0
@@ -373,6 +373,8 @@ static void __init smdkv310_map_io(void) {exynos_init_io (NULL ,0 );s3c24xx_init_uarts (smdkv310_uartcfgs,ARRAY_SIZE (smdkv310_uartcfgs)); + xxti_f =12000000 ; + xusbxti_f =24000000 ; }static void __init smdkv310_reserve (void )
arch/arm/mach-exynos/mach-universal_c210.c +2 -0
@@ -1095,6 +1095,8 @@ static void __init universal_map_io(void)exynos_init_io (NULL ,0 );s3c24xx_init_uarts (universal_uartcfgs,ARRAY_SIZE (universal_uartcfgs));s5p_set_timer_source (S5P_PWM2 ,S5P_PWM4 ); + xxti_f =0 ; + xusbxti_f =24000000 ; }static void s5p_tv_setup (void )
Signature · 1 line
1.7.5.4
PATCH v5 9/12 ARM: dts: add clock provider information for all controllers in Exynos4 SoC
In reply to Thomas AbrahamFor all supported peripheral controllers on Exynos4, add clock lookup information.
--- arch/arm/boot/dts/exynos4.dtsi | 50 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 50 insertions(+), 0 deletions(-)
arch/arm/boot/dts/exynos4.dtsi +50 -0
@@ -86,6 +86,8 @@ compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; interrupts = <0 43 0>; + clocks = <&clock 345>; + clock-names = "watchdog"; status = "disabled"; };
@@ -93,6 +95,8 @@ compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <0 44 0>, <0 45 0>; + clocks = <&clock 346>; + clock-names = "rtc"; status = "disabled"; };
@@ -100,6 +104,8 @@ compatible = "samsung,s5pv210-keypad"; reg = <0x100A0000 0x100>; interrupts = <0 109 0>; + clocks = <&clock 347>; + clock-names = "keypad"; status = "disabled"; };
@@ -107,6 +113,8 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12510000 0x100>; interrupts = <0 73 0>; + clocks = <&clock 297>, <&clock 145>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; };
@@ -114,6 +122,8 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12520000 0x100>; interrupts = <0 74 0>; + clocks = <&clock 298>, <&clock 146>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; };
@@ -121,6 +131,8 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12530000 0x100>; interrupts = <0 75 0>; + clocks = <&clock 299>, <&clock 147>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; };
@@ -128,6 +140,8 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12540000 0x100>; interrupts = <0 76 0>; + clocks = <&clock 300>, <&clock 148>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; };
@@ -135,6 +149,8 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; interrupts = <0 52 0>; + clocks = <&clock 312>, <&clock 151>; + clock-names = "uart", "clk_uart_baud0"; status = "disabled"; };
@@ -142,6 +158,8 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13810000 0x100>; interrupts = <0 53 0>; + clocks = <&clock 313>, <&clock 152>; + clock-names = "uart", "clk_uart_baud0"; status = "disabled"; };
@@ -149,6 +167,8 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; interrupts = <0 54 0>; + clocks = <&clock 314>, <&clock 153>; + clock-names = "uart", "clk_uart_baud0"; status = "disabled"; };
@@ -156,6 +176,8 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13830000 0x100>; interrupts = <0 55 0>; + clocks = <&clock 315>, <&clock 154>; + clock-names = "uart", "clk_uart_baud0"; status = "disabled"; };
@@ -165,6 +187,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13860000 0x100>; interrupts = <0 58 0>; + clocks = <&clock 317>; + clock-names = "i2c"; status = "disabled"; };
@@ -174,6 +198,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13870000 0x100>; interrupts = <0 59 0>; + clocks = <&clock 318>; + clock-names = "i2c"; status = "disabled"; };
@@ -183,6 +209,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13880000 0x100>; interrupts = <0 60 0>; + clocks = <&clock 319>; + clock-names = "i2c"; status = "disabled"; };
@@ -192,6 +220,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13890000 0x100>; interrupts = <0 61 0>; + clocks = <&clock 320>; + clock-names = "i2c"; status = "disabled"; };
@@ -201,6 +231,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138A0000 0x100>; interrupts = <0 62 0>; + clocks = <&clock 321>; + clock-names = "i2c"; status = "disabled"; };
@@ -210,6 +242,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138B0000 0x100>; interrupts = <0 63 0>; + clocks = <&clock 322>; + clock-names = "i2c"; status = "disabled"; };
@@ -219,6 +253,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138C0000 0x100>; interrupts = <0 64 0>; + clocks = <&clock 323>; + clock-names = "i2c"; status = "disabled"; };
@@ -228,6 +264,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138D0000 0x100>; interrupts = <0 65 0>; + clocks = <&clock 324>; + clock-names = "i2c"; status = "disabled"; };
@@ -239,6 +277,8 @@ rx-dma-channel = <&pdma0 6>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; + clocks = <&clock 327>, <&clock 159>; + clock-names = "spi", "spi_busclk0"; status = "disabled"; };
@@ -250,6 +290,8 @@ rx-dma-channel = <&pdma1 6>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; + clocks = <&clock 328>, <&clock 160>; + clock-names = "spi", "spi_busclk0"; status = "disabled"; };
@@ -261,6 +303,8 @@ rx-dma-channel = <&pdma0 8>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; + clocks = <&clock 329>, <&clock 161>; + clock-names = "spi", "spi_busclk0"; status = "disabled"; };
@@ -275,18 +319,24 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = <0 35 0>; + clocks = <&clock 292>; + clock-names = "apb_pclk"; }; pdma1: pdma at 12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = <0 36 0>; + clocks = <&clock 293>; + clock-names = "apb_pclk"; }; mdma1: mdma at 12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = <0 34 0>; + clocks = <&clock 279>; + clock-names = "apb_pclk"; }; }; };
Signature · 1 line
1.7.5.4
PATCH v5 10/12 ARM: Exynos4: remove auxdata table from machine file
In reply to Thomas AbrahamWith support for device tree based clock lookup now available, remove the auxdata table from exynos4 dt-enabled machine file.
--- arch/arm/mach-exynos/mach-exynos4-dt.c | 69 +------------------------------- 1 files changed, 2 insertions(+), 67 deletions(-)
arch/arm/mach-exynos/mach-exynos4-dt.c +2 -67
@@ -11,78 +11,14 @@* published by the Free Software Foundation. */ +#include <linux/kernel.h> #include <linux/of_platform.h> -#include <linux/serial_core.h> #include <asm/mach/arch.h> #include <asm/hardware/gic.h> -#include <mach/map.h> - -#include <plat/cpu.h> -#include <plat/regs-serial.h> #include "common.h" -/* -* The following lookup table is used to override device names when devices -* are registered from device tree. This is temporarily added to enable -* device tree support addition for the Exynos4 architecture. -* -* For drivers that require platform data to be provided from the machine -* file, a platform data pointer can also be supplied along with the -* devices names. Usually, the platform data elements that cannot be parsed -* from the device tree by the drivers (example: function pointers) are -* supplied. But it should be noted that this is a temporary mechanism and -* at some point, the drivers should be capable of parsing all the platform -* data from the device tree. -*/ -static const struct of_dev_auxdata exynos4_auxdata_lookup[]__initconst = { -OF_DEV_AUXDATA ("samsung,exynos4210-uart" ,EXYNOS4_PA_UART0 , -"exynos4210-uart.0" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-uart" ,EXYNOS4_PA_UART1 , -"exynos4210-uart.1" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-uart" ,EXYNOS4_PA_UART2 , -"exynos4210-uart.2" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-uart" ,EXYNOS4_PA_UART3 , -"exynos4210-uart.3" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-sdhci" ,EXYNOS4_PA_HSMMC (0 ), -"exynos4-sdhci.0" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-sdhci" ,EXYNOS4_PA_HSMMC (1 ), -"exynos4-sdhci.1" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-sdhci" ,EXYNOS4_PA_HSMMC (2 ), -"exynos4-sdhci.2" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-sdhci" ,EXYNOS4_PA_HSMMC (3 ), -"exynos4-sdhci.3" ,NULL ), -OF_DEV_AUXDATA ("samsung,s3c2440-i2c" ,EXYNOS4_PA_IIC (0 ), -"s3c2440-i2c.0" ,NULL ), -OF_DEV_AUXDATA ("samsung,s3c2440-i2c" ,EXYNOS4_PA_IIC (1 ), -"s3c2440-i2c.1" ,NULL ), -OF_DEV_AUXDATA ("samsung,s3c2440-i2c" ,EXYNOS4_PA_IIC (2 ), -"s3c2440-i2c.2" ,NULL ), -OF_DEV_AUXDATA ("samsung,s3c2440-i2c" ,EXYNOS4_PA_IIC (3 ), -"s3c2440-i2c.3" ,NULL ), -OF_DEV_AUXDATA ("samsung,s3c2440-i2c" ,EXYNOS4_PA_IIC (4 ), -"s3c2440-i2c.4" ,NULL ), -OF_DEV_AUXDATA ("samsung,s3c2440-i2c" ,EXYNOS4_PA_IIC (5 ), -"s3c2440-i2c.5" ,NULL ), -OF_DEV_AUXDATA ("samsung,s3c2440-i2c" ,EXYNOS4_PA_IIC (6 ), -"s3c2440-i2c.6" ,NULL ), -OF_DEV_AUXDATA ("samsung,s3c2440-i2c" ,EXYNOS4_PA_IIC (7 ), -"s3c2440-i2c.7" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-spi" ,EXYNOS4_PA_SPI0 , -"exynos4210-spi.0" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-spi" ,EXYNOS4_PA_SPI1 , -"exynos4210-spi.1" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-spi" ,EXYNOS4_PA_SPI2 , -"exynos4210-spi.2" ,NULL ), -OF_DEV_AUXDATA ("arm,pl330" ,EXYNOS4_PA_PDMA0 ,"dma-pl330.0" ,NULL ), -OF_DEV_AUXDATA ("arm,pl330" ,EXYNOS4_PA_PDMA1 ,"dma-pl330.1" ,NULL ), -OF_DEV_AUXDATA ("arm,pl330" ,EXYNOS4_PA_MDMA1 ,"dma-pl330.2" ,NULL ), -OF_DEV_AUXDATA ("samsung,exynos4210-tmu" ,EXYNOS4_PA_TMU , -"exynos-tmu" ,NULL ), - {}, -}; -static void __init exynos4_dt_map_io (void ) {exynos_init_io (NULL ,0 );
@@ -90,8 +26,7 @@ static void __init exynos4_dt_map_io(void)static void __init exynos4_dt_machine_init (void ) { -of_platform_populate (NULL , of_default_bus_match_table, - exynos4_auxdata_lookup,NULL ); +of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL ); }static char const *exynos4_dt_compat[]__initdata = {
Signature · 1 line
1.7.5.4
PATCH v5 11/12 ARM: Exynos: use fin_pll clock as the tick clock source for mct
In reply to Thomas AbrahamWith the migration of Exynos4 clocks to use common clock framework, the old styled 'xtal' clock is not used anymore. Instead, the clock 'fin_pll' is used as the tick clock for mct controller.
--- arch/arm/mach-exynos/mct.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-)
arch/arm/mach-exynos/mct.c +13 -1
@@ -487,10 +487,22 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {static void __init exynos4_timer_resources (struct device_node *np) { +#ifdef CONFIG_COMMON_CLK +struct clk *tick_clk; + + tick_clk =clk_get (NULL ,"fin_pll" ); +if (IS_ERR (tick_clk)) +panic ("%s: unable to determine tick clock rate\n" , __func__); + clk_rate =clk_get_rate (tick_clk); +#else +/* +* todo: remove this legacy code after adding common clock support for +* exynos5250. +*/ struct clk *mct_clk; mct_clk =clk_get (NULL ,"xtal" ); - clk_rate =clk_get_rate (mct_clk); +#endif reg_base = np ?of_iomap (np,0 ) :S5P_VA_SYSTIMER ;if (!reg_base)
Signature · 1 line
1.7.5.4
PATCH v5 12/12 ARM: Exynos: add support for mct clock setup
In reply to Thomas AbrahamAdd support for mct clock lookup and setup to ensure that the mct clock is has been turned on.
--- arch/arm/mach-exynos/mct.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)
arch/arm/mach-exynos/mct.c +6 -1
@@ -488,7 +488,12 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {static void __init exynos4_timer_resources (struct device_node *np) {#ifdef CONFIG_COMMON_CLK -struct clk *tick_clk; +struct clk *mct_clk, *tick_clk; + + mct_clk =clk_get (NULL ,"mct" ); +if (IS_ERR (mct_clk)) +panic ("%s: unable to retrieve mct clock instance\n" , __func__); +clk_prepare_enable (mct_clk); tick_clk =clk_get (NULL ,"fin_pll" );if (IS_ERR (tick_clk))
Signature · 1 line
1.7.5.4
v5 cover clk: exynos4: migrate to common clock framework
In reply to Thomas AbrahamQuoted 11 lines · Thomas Abraham
Changes since v4:
- Rebased to linux-3.8-rc1.Changes since v3:
- Includes changes suggested by Tomasz Figa <[email protected]>This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms.
I'd prefer to see if exynos4 and 5 were kept common here, and both transitioned at the same time. Especially since there are no legacy boards for exynos5, it would mean you could have a very clean transition there. What's the plan to follow up with 5?
What are the plans to remove legacy board files on exynos4 at this time and switch them to DT-only? You could do it gradually like Stephen Warren did on Tegra, with hooks that call out to some of the legacy code, but configure the board through device tree and do away with the classic machine descriptors, etc.
-Olof
v5 cover clk: exynos4: migrate to common clock framework
Quoted 10 lines · Olof Johansson
Quoted 7 lines · Thomas Abraham
Changes since v4:
- Rebased to linux-3.8-rc1.Changes since v3:
- Includes changes suggested by Tomasz Figa <[email protected]>This patch series migrates the Samsung Exynos4 SoC clock code to adopt
the
Quoted 8 lines
Quoted 4 lines
common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms.
I'd prefer to see if exynos4 and 5 were kept common here, and both transitioned
at the same time. Especially since there are no legacy boards for exynos5,
it
Quoted 1 line
would mean you could have a very clean transition there. What's the plan
to
Quoted 2 lines
follow up with 5?
Yeah, I'm working on EXYNOS5250 common clk stuff and Thomas is working on EXYNOS5440. So I think, we can move on exynos4 and 5 both common clk at the same time. Note, EXYNOS5 common clk stuff will be submitted in the beginning of Jan.
Quoted 6 lines
What are the plans to remove legacy board files on exynos4 at this time and switch them to DT-only? You could do it gradually like Stephen Warren did on Tegra, with hooks that call out to some of the legacy code, but configure the board through device tree and do away with the classic machine descriptors, etc.
I had a plan to remove non-DT support on EXYNOS4 for v3.10, but if possible, I will try to do it for v3.9. If any updates, let you know.
Thanks.
Happy New Year!
- Kukjin
v5 cover clk: exynos4: migrate to common clock framework
Quoted 20 lines · Kukjin Kim
Quoted 10 lines · Olof Johansson
Quoted 7 lines · Thomas Abraham
Changes since v4:
- Rebased to linux-3.8-rc1.Changes since v3:
- Includes changes suggested by Tomasz Figa <[email protected]>This patch series migrates the Samsung Exynos4 SoC clock code to adopt
the
Quoted 8 lines
Quoted 4 lines
common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms.
I'd prefer to see if exynos4 and 5 were kept common here, and both transitioned
at the same time. Especially since there are no legacy boards for exynos5,it
Quoted 8 lines
Quoted 1 line
would mean you could have a very clean transition there. What's the plan
to
Quoted 2 lines
follow up with 5?
Yeah, I'm working on EXYNOS5250 common clk stuff and Thomas is working on EXYNOS5440. So I think, we can move on exynos4 and 5 both common clk at the same time. Note, EXYNOS5 common clk stuff will be submitted in the beginning of Jan.
As per the other reply, that sounds good -- it doesn't make sense to merge one without the other but it sounds like maybe they can both be ready in time for 3.9.
Quoted 8 lines
Quoted 6 lines
What are the plans to remove legacy board files on exynos4 at this time and switch them to DT-only? You could do it gradually like Stephen Warren did on Tegra, with hooks that call out to some of the legacy code, but configure the board through device tree and do away with the classic machine descriptors, etc.
I had a plan to remove non-DT support on EXYNOS4 for v3.10, but if possible, I will try to do it for v3.9. If any updates, let you know.
There's no hurry, 3.10 is ok as a target as long as it's taking place. The main reason for why I was asking was that there was still some legacy board file updates posted, and that I hadn't seen much patches lately that made it obvious that there was an effort in that direction. 3.10 sounds like a good target.
Quoted 1 line
Happy New Year!
Thanks, you too.
-Olof
v5 cover clk: exynos4: migrate to common clock framework
In reply to Olof JohanssonQuoted 13 lines · Olof Johansson
Quoted 11 lines · Thomas Abraham
Changes since v4:
- Rebased to linux-3.8-rc1.Changes since v3:
- Includes changes suggested by Tomasz Figa <[email protected]>This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms.
Quoted 4 lines
I'd prefer to see if exynos4 and 5 were kept common here, and both transitioned at the same time. Especially since there are no legacy boards for exynos5, it would mean you could have a very clean transition there. What's the plan to follow up with 5?
Ok. I have been looking into Exynos4 since Mr. Kim was already onto Exynos5 common clock. Sure, we could do a cleaner Exynos4/5 common clock series for v3.9. That would let both exynos4/5 to be built together which otherwise this patch series would not allow.
Quoted 6 lines
What are the plans to remove legacy board files on exynos4 at this time and switch them to DT-only? You could do it gradually like Stephen Warren did on Tegra, with hooks that call out to some of the legacy code, but configure the board through device tree and do away with the classic machine descriptors, etc.
I did try this sometime back for exynos4210 based origen board. But did not make much progress since certain portions require the older samsung gpiolib support and exynos4210 mainline device tree support has migrated to newer pinctrl framework. There is some work here to do and I will work with Mr. Kim on this.
Thanks,
Thomas.
Quoted 4 lines
-Olof
v5 cover clk: exynos4: migrate to common clock framework
Quoted 19 lines · Thomas Abraham
Quoted 13 lines · Olof Johansson
Quoted 11 lines · Thomas Abraham
Changes since v4:
- Rebased to linux-3.8-rc1.Changes since v3:
- Includes changes suggested by Tomasz Figa <[email protected]>This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms.
Quoted 4 lines
I'd prefer to see if exynos4 and 5 were kept common here, and both transitioned at the same time. Especially since there are no legacy boards for exynos5, it would mean you could have a very clean transition there. What's the plan to follow up with 5?
Quoted 4 lines
Ok. I have been looking into Exynos4 since Mr. Kim was already onto Exynos5 common clock. Sure, we could do a cleaner Exynos4/5 common clock series for v3.9. That would let both exynos4/5 to be built together which otherwise this patch series would not allow.
Great, that sounds good. Regressing exynos 4+5 builds would definitely be a bad thing. In other words, it makes sense to hold off merging the exynos4 pieces until the 5 counterparts are ready.
Quoted 11 lines
Quoted 5 lines
What are the plans to remove legacy board files on exynos4 at this time and switch them to DT-only? You could do it gradually like Stephen Warren did on Tegra, with hooks that call out to some of the legacy code, but configure the board through device tree and do away with the classic machine descriptors, etc.
I did try this sometime back for exynos4210 based origen board. But did not make much progress since certain portions require the older samsung gpiolib support and exynos4210 mainline device tree support has migrated to newer pinctrl framework. There is some work here to do and I will work with Mr. Kim on this.
Great, thanks.
-Olof
Sylwester Nawrocki
maintainerv5 cover clk: exynos4: migrate to common clock framework
In reply to Thomas AbrahamQuoted 66 lines · Thomas Abraham
Changes since v4:
- Rebased to linux-3.8-rc1.Changes since v3:
- Includes changes suggested by Tomasz Figa <[email protected]>This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms.
This patch series depends on this series:
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg14471.html and this patch
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg14472.htmlThomas Abraham (12):
clk: samsung: add common clock framework helper functions for Samsung platforms
clk: samsung: add pll clock registration helper functions
clk: exynos4: register clocks using common clock framework
ARM: Exynos: Rework timer initialization sequence
ARM: Exynos4: Migrate clock support to common clock framework
ARM: dts: add exynos4 clock controller nodes
ARM: dts: add xxti and xusbxti fixed rate clock nodes for exynos4 based platforms
ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed
ARM: dts: add clock provider information for all controllers in Exynos4 SoC
ARM: Exynos4: remove auxdata table from machine file
ARM: Exynos: usefin_pllclock as the tick clock source for mct
ARM: Exynos: add support for mct clock setup.../devicetree/bindings/clock/exynos4-clock.txt | 215 +++++++ arch/arm/boot/dts/exynos4.dtsi | 50 ++ arch/arm/boot/dts/exynos4210-origen.dts | 12 + arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 + arch/arm/boot/dts/exynos4210.dtsi | 6 + arch/arm/boot/dts/exynos4412-origen.dts | 12 + arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 + arch/arm/boot/dts/exynos4x12.dtsi | 6 + arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/Makefile | 3 - arch/arm/mach-exynos/clock-exynos4.h | 35 - arch/arm/mach-exynos/clock-exynos4210.c | 188 ------ arch/arm/mach-exynos/clock-exynos4212.c | 192 ------ arch/arm/mach-exynos/common.c | 57 ++- arch/arm/mach-exynos/common.h | 21 +- arch/arm/mach-exynos/mach-armlex4210.c | 3 +- arch/arm/mach-exynos/mach-exynos4-dt.c | 72 +-- arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +- arch/arm/mach-exynos/mach-nuri.c | 5 +- arch/arm/mach-exynos/mach-origen.c | 5 +- arch/arm/mach-exynos/mach-smdk4x12.c | 5 +- arch/arm/mach-exynos/mach-smdkv310.c | 7 +- arch/arm/mach-exynos/mach-universal_c210.c | 3 +- arch/arm/mach-exynos/mct.c | 32 +- arch/arm/plat-samsung/Kconfig | 4 +- drivers/clk/Makefile | 1 + drivers/clk/samsung/Makefile | 6 + drivers/clk/samsung/clk-exynos4.c | 655 ++++++++++++++++++++ drivers/clk/samsung/clk-pll.c | 400 ++++++++++++ drivers/clk/samsung/clk-pll.h | 38 ++ drivers/clk/samsung/clk.c | 180 ++++++ drivers/clk/samsung/clk.h | 216 +++++++ 32 files changed, 1919 insertions(+), 537 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt delete mode 100644 arch/arm/mach-exynos/clock-exynos4.h
Quoted 8 lines
delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c create mode 100644 drivers/clk/samsung/Makefile create mode 100644 drivers/clk/samsung/clk-exynos4.c create mode 100644 drivers/clk/samsung/clk-pll.c create mode 100644 drivers/clk/samsung/clk-pll.h create mode 100644 drivers/clk/samsung/clk.c create mode 100644 drivers/clk/samsung/clk.h
Thanks Thomas! The patch series generally looks good to me, I've tested it on an Exynos4412 based board. I have applied couple fixes that Tomasz Figa has sent you off the mailing list. And to make a MIPI-CSI2 camera working a small fixup patch as below.
I have just one remark, but this could possibly be done as a follow up patch. Namely it may make sense to rename various sclk_* clocks to just "sclk", so for instance we don't have "fimd", "sclk_fimd", "fimc", "sclk_fimc" but e.g. "bus" or "gate" and "sclk" for each device. Such naming might be better for handling devices at core subsystems level, e.g. Runtime PM or devfreq.
Please feel free to add:
I would be great to have this patch set merged for 3.9, so people can switch earlier to the common clock API, rather than modifying files that will be removed soon.
--
Regards,
Sylwester
Quoted 1 line
From
8382dcc93bf465e9a03f4f07426825f1a9be0ba1Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki <[email protected]>
Date: Fri, 18 Jan 2013 19:13:52 +0100
Subject: [PATCH] clk: samsung: Correct definition of sclk_cam gate clocks
sclk_cam0/1 clock gates are present on all exynos4 SoCs. Move definitions of these clocks to proper table to reflect that.
--- drivers/clk/samsung/clk-exynos4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/clk/samsung/clk-exynos4.c +2 -2
@@ -299,6 +299,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 0xc320, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),GATE_DA (sclk_csis1,"s5p-mipi-csis.1" ,"sclk_csis1" ,"div_csis1" ,0xc320 ,28 ,CLK_SET_RATE_PARENT ,0 ,"sclk_csis" ), +GATE (sclk_cam0,"sclk_cam0" ,"div_cam0" ,0xc820 ,4 ,CLK_SET_RATE_PARENT ,0 ), +GATE (sclk_cam1,"sclk_cam1" ,"div_cam1" ,0xc820 ,5 ,CLK_SET_RATE_PARENT ,0 ),GATE (sclk_hdmi,"sclk_hdmi" ,"mout_hdmi" ,0xc324 ,0 ,0 ,0 ),GATE (sclk_mixer,"sclk_mixer" ,"mout_mixer" ,0xc324 ,4 ,0 ,0 ), GATE(sclk_dac, "sclk_dac", "mout_dac", 0xc324, 8, 0, 0),
@@ -416,8 +418,6 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 0xc338, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),GATE (sclk_mipi1,"sclk_mipi1" ,"div_mipi_pre1" ,0xc338 ,12 ,CLK_SET_RATE_PARENT ,0 ),GATE (sclk_sata,"sclk_sata" ,"div_sata" ,0xc340 ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_cam0,"sclk_cam0" ,"div_cam0" ,0xc820 ,4 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_cam1,"sclk_cam1" ,"div_cam1" ,0xc820 ,5 ,CLK_SET_RATE_PARENT ,0 ),GATE (tvenc,"tvenc" ,"aclk160" ,0xc924 ,2 ,0 ,0 ),GATE (g2d,"g2d" ,"aclk200" ,0xc930 ,0 ,0 ,0 ), GATE(rotator, "rotator", "aclk200", 0xc930, 1, 0, 0),
Signature · 1 line
1.7.9.5
v5 cover clk: exynos4: migrate to common clock framework
Hi Thomas, Sylwester,
Quoted 92 lines · On Monday 21 of January 2013 15:29:16 Sylwester Nawrocki wrote:
Quoted 70 lines · Thomas Abraham
Changes since v4:
- Rebased to linux-3.8-rc1.Changes since v3:
- Includes changes suggested by Tomasz Figa <[email protected]>This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms.
This patch series depends on this series:
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg14471 .html and this patch
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg14472 .html>
Thomas Abraham (12):
clk: samsung: add common clock framework helper functions for Samsung platforms clk: samsung: add pll clock registration helper functions
clk: exynos4: register clocks using common clock framework
ARM: Exynos: Rework timer initialization sequence
ARM: Exynos4: Migrate clock support to common clock framework
ARM: dts: add exynos4 clock controller nodes
ARM: dts: add xxti and xusbxti fixed rate clock nodes for exynos4 based platforms ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed ARM: dts: add clock provider information for all controllers in Exynos4 SoC ARM: Exynos4: remove auxdata table from machine file
ARM: Exynos: usefin_pllclock as the tick clock source for mct
ARM: Exynos: add support for mct clock setup.../devicetree/bindings/clock/exynos4-clock.txt | 215 +++++++ arch/arm/boot/dts/exynos4.dtsi | 50 ++ arch/arm/boot/dts/exynos4210-origen.dts | 12 + arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 + arch/arm/boot/dts/exynos4210.dtsi | 6 + arch/arm/boot/dts/exynos4412-origen.dts | 12 + arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 + arch/arm/boot/dts/exynos4x12.dtsi | 6 + arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/Makefile | 3 - arch/arm/mach-exynos/clock-exynos4.h | 35 - arch/arm/mach-exynos/clock-exynos4210.c | 188 ------ arch/arm/mach-exynos/clock-exynos4212.c | 192 ------ arch/arm/mach-exynos/common.c | 57 ++- arch/arm/mach-exynos/common.h | 21 +- arch/arm/mach-exynos/mach-armlex4210.c | 3 +- arch/arm/mach-exynos/mach-exynos4-dt.c | 72 +-- arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +- arch/arm/mach-exynos/mach-nuri.c | 5 +- arch/arm/mach-exynos/mach-origen.c | 5 +- arch/arm/mach-exynos/mach-smdk4x12.c | 5 +- arch/arm/mach-exynos/mach-smdkv310.c | 7 +- arch/arm/mach-exynos/mach-universal_c210.c | 3 +- arch/arm/mach-exynos/mct.c | 32 +- arch/arm/plat-samsung/Kconfig | 4 +- drivers/clk/Makefile | 1 + drivers/clk/samsung/Makefile | 6 + drivers/clk/samsung/clk-exynos4.c | 655 ++++++++++++++++++++ drivers/clk/samsung/clk-pll.c | 400 ++++++++++++ drivers/clk/samsung/clk-pll.h | 38 ++ drivers/clk/samsung/clk.c | 180 ++++++ drivers/clk/samsung/clk.h | 216 +++++++ 32 files changed, 1919 insertions(+), 537 deletions(-) create mode 100644
Documentation/devicetree/bindings/clock/exynos4-clock.txtdelete mode 100644arch/arm/mach-exynos/clock-exynos4.hQuoted 8 lines
delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c create mode 100644 drivers/clk/samsung/Makefile create mode 100644 drivers/clk/samsung/clk-exynos4.c create mode 100644 drivers/clk/samsung/clk-pll.c create mode 100644 drivers/clk/samsung/clk-pll.h create mode 100644 drivers/clk/samsung/clk.c create mode 100644 drivers/clk/samsung/clk.hThanks Thomas! The patch series generally looks good to me, I've tested it on an Exynos4412 based board. I have applied couple fixes that Tomasz Figa has sent you off the mailing list. And to make a MIPI-CSI2 camera working a small fixup patch as below.
I have just one remark, but this could possibly be done as a follow up patch. Namely it may make sense to rename various sclk_* clocks to just "sclk", so for instance we don't have "fimd", "
sclk_fimd", "fimc", "sclk_fimc" but e.g. "bus" or "gate" and "sclk" for each device. Such naming might be better for handling devices at core subsystems level, e.g. Runtime PM or devfreq.
Quoted 4 lines
Please feel free to add:
Reviewed-by Sylwester Nawrocki <[email protected]>Tested-by Sylwester Nawrocki <[email protected]>
I fully agree with Sylwester. After adding mentioned fixup patches, feel free to add my Reviewed-by and Tested-by as well.
Quoted 4 lines
I would be great to have this patch set merged for 3.9, so people can switch earlier to the common clock API, rather than modifying files that will be removed soon.
Yes, it would be great to have this series merged earlier, because it's very important for further development of Device Tree support on Samsung platforms. Possibly for 3.9 it could be merged as an alternative to the legacy clock code and after enough testing legacy code could be dropped in next kernel release.
Best regards
Signature · 3 lines
Tomasz Figa Samsung Poland R&D Center SW Solution Development, Linux Platform
v5 cover clk: exynos4: migrate to common clock framework
Quoting Tomasz Figa (2013-01-21 08:22:39)
Quoted 108 lines
Hi Thomas, Sylwester,
Quoted 92 lines · On Monday 21 of January 2013 15:29:16 Sylwester Nawrocki wrote:
Quoted 70 lines · Thomas Abraham
Changes since v4:
- Rebased to linux-3.8-rc1.Changes since v3:
- Includes changes suggested by Tomasz Figa <[email protected]>This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms.
This patch series depends on this series:
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg14471 .html and this patch
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg14472 .html>
Thomas Abraham (12):
clk: samsung: add common clock framework helper functions for Samsung platforms clk: samsung: add pll clock registration helper functions
clk: exynos4: register clocks using common clock framework
ARM: Exynos: Rework timer initialization sequence
ARM: Exynos4: Migrate clock support to common clock framework
ARM: dts: add exynos4 clock controller nodes
ARM: dts: add xxti and xusbxti fixed rate clock nodes for exynos4 based platforms ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed ARM: dts: add clock provider information for all controllers in Exynos4 SoC ARM: Exynos4: remove auxdata table from machine file
ARM: Exynos: usefin_pllclock as the tick clock source for mct
ARM: Exynos: add support for mct clock setup.../devicetree/bindings/clock/exynos4-clock.txt | 215 +++++++ arch/arm/boot/dts/exynos4.dtsi | 50 ++ arch/arm/boot/dts/exynos4210-origen.dts | 12 + arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 + arch/arm/boot/dts/exynos4210.dtsi | 6 + arch/arm/boot/dts/exynos4412-origen.dts | 12 + arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 + arch/arm/boot/dts/exynos4x12.dtsi | 6 + arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/Makefile | 3 - arch/arm/mach-exynos/clock-exynos4.h | 35 - arch/arm/mach-exynos/clock-exynos4210.c | 188 ------ arch/arm/mach-exynos/clock-exynos4212.c | 192 ------ arch/arm/mach-exynos/common.c | 57 ++- arch/arm/mach-exynos/common.h | 21 +- arch/arm/mach-exynos/mach-armlex4210.c | 3 +- arch/arm/mach-exynos/mach-exynos4-dt.c | 72 +-- arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +- arch/arm/mach-exynos/mach-nuri.c | 5 +- arch/arm/mach-exynos/mach-origen.c | 5 +- arch/arm/mach-exynos/mach-smdk4x12.c | 5 +- arch/arm/mach-exynos/mach-smdkv310.c | 7 +- arch/arm/mach-exynos/mach-universal_c210.c | 3 +- arch/arm/mach-exynos/mct.c | 32 +- arch/arm/plat-samsung/Kconfig | 4 +- drivers/clk/Makefile | 1 + drivers/clk/samsung/Makefile | 6 + drivers/clk/samsung/clk-exynos4.c | 655 ++++++++++++++++++++ drivers/clk/samsung/clk-pll.c | 400 ++++++++++++ drivers/clk/samsung/clk-pll.h | 38 ++ drivers/clk/samsung/clk.c | 180 ++++++ drivers/clk/samsung/clk.h | 216 +++++++ 32 files changed, 1919 insertions(+), 537 deletions(-) create mode 100644
Documentation/devicetree/bindings/clock/exynos4-clock.txtdelete mode 100644arch/arm/mach-exynos/clock-exynos4.hQuoted 8 lines
delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c create mode 100644 drivers/clk/samsung/Makefile create mode 100644 drivers/clk/samsung/clk-exynos4.c create mode 100644 drivers/clk/samsung/clk-pll.c create mode 100644 drivers/clk/samsung/clk-pll.h create mode 100644 drivers/clk/samsung/clk.c create mode 100644 drivers/clk/samsung/clk.hThanks Thomas! The patch series generally looks good to me, I've tested it on an Exynos4412 based board. I have applied couple fixes that Tomasz Figa has sent you off the mailing list. And to make a MIPI-CSI2 camera working a small fixup patch as below.
I have just one remark, but this could possibly be done as a follow up patch. Namely it may make sense to rename various sclk_* clocks to just "sclk", so for instance we don't have "fimd", "
sclk_fimd", "fimc", "sclk_fimc" but e.g. "bus" or "gate" and "sclk" for each device. Such naming might be better for handling devices at core subsystems level, e.g. Runtime PM or devfreq.Quoted 4 lines
Please feel free to add:
Reviewed-by Sylwester Nawrocki <[email protected]>Tested-by Sylwester Nawrocki <[email protected]>I fully agree with Sylwester. After adding mentioned fixup patches, feel free to add my Reviewed-by and Tested-by as well.
Quoted 4 lines
I would be great to have this patch set merged for 3.9, so people can switch earlier to the common clock API, rather than modifying files that will be removed soon.
Quoted 6 lines
Yes, it would be great to have this series merged earlier, because it's very important for further development of Device Tree support on Samsung platforms. Possibly for 3.9 it could be merged as an alternative to the legacy clock code and after enough testing legacy code could be dropped in next kernel release.
I thought that the Exynos4 and Exynos5 ports to the common clk framework were going to be merged. Is that still the plan?
Regards,
Mike
Quoted 5 lines
Best regards
Signature · 3 lines
Tomasz Figa Samsung Poland R&D Center SW Solution Development, Linux Platform