EXYNOS5: Enable DWMMC, add FDT support for DWMMC and enable EMMC boot

Add required compatible information for DWMMC driver.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes since V1:
No change.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
No change.

Changes since V4:
No change.

 include/fdtdec.h | 1 +
 lib/fdtdec.c     | 1 +
 2 files changed, 2 insertions(+)

include/fdtdec.h +1 -0

index f77d195..fb4c33f 100644
@@ -79,6 +79,7 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS_EHCI,	/* Exynos EHCI controller */
 	COMPAT_SAMSUNG_EXYNOS_USB_PHY,	/* Exynos phy controller for usb2.0 */
 	COMPAT_MAXIM_MAX77686_PMIC,	/* MAX77686 PMIC */
+	COMPAT_SAMSUNG_EXYNOS5_DWMMC,	/* Exynos5 DWMMC controller */
 
 	COMPAT_COUNT,
 };

lib/fdtdec.c +1 -0

index 16921e1..1a4763e 100644
@@ -54,6 +54,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"),
 	COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
 	COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
+	COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)

This patch adds DWMMC device node data for exynos5. This patch also adds binding file for DWMMC device node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Added binding file for DWMMC device node at the location "doc/device-tree-bindings/exynos/dwmmc.txt".
2)Removed the propname 'index' from device node. 3)Prefixed the vendor name 'samsung' before propname in device node.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
No change.

Changes since V4:
1)Updated the doc/device-tree-bindings/exynos/dwmmc.txt with more information regarding the property 'samsung,timing'. 2)Replaced the name 'dwmmc' with 'mmc'.

 arch/arm/dts/exynos5250.dtsi              | 31 +++++++++++++++++++
 board/samsung/dts/exynos5250-smdk5250.dts | 22 ++++++++++++++
 doc/device-tree-bindings/exynos/dwmmc.txt | 49 +++++++++++++++++++++++++++++++
 3 files changed, 102 insertions(+)
 create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt

arch/arm/dts/exynos5250.dtsi +31 -0

index ed8c8dd..6c08eb7 100644
@@ -151,4 +151,35 @@
 		};
 	};
 
+	mmc at 12200000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12200000 0x1000>;
+		interrupts = <0 75 0>;
+	};
+
+	mmc at 12210000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12210000 0x1000>;
+		interrupts = <0 76 0>;
+	};
+
+	mmc at 12220000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12220000 0x1000>;
+		interrupts = <0 77 0>;
+	};
+
+	mmc at 12230000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12230000 0x1000>;
+		interrupts = <0 78 0>;
+	};
 };

board/samsung/dts/exynos5250-smdk5250.dts +22 -0

index cbfab6f..1d3e42b 100644
@@ -30,6 +30,10 @@
 		spi2 = "/spi at 12d40000";
 		spi3 = "/spi at 131a0000";
 		spi4 = "/spi at 131b0000";
+		mmc0 = "/mmc at 12200000";
+		mmc1 = "/mmc at 12210000";
+		mmc2 = "/mmc at 12220000";
+		mmc3 = "/mmc at 12230000";
 	};
 
 	sromc at 12250000 {

@@ -66,4 +70,22 @@
 			compatible = "maxim,max77686_pmic";
 		};
 	};
+
+	mmc at 12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+	};
+
+	mmc at 12210000 {
+		status = "disabled";
+	};
+
+	mmc at 12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+	};
+
+	mmc at 12230000 {
+		status = "disabled";
+	};
 };

doc/device-tree-bindings/exynos/dwmmc.txt new file +49 -0

new file mode 100644
index 0000000..0054ace
@@ -0,0 +1,49 @@
+* Exynos 5250 DWC_mobile_storage
+
+The Exynos 5250 provides DWC_mobile_storage interface which supports
+. Embedded Multimedia Cards (EMMC-version 4.5)
+. Secure Digital memory (SD mem-version 2.0)
+. Secure Digital I/O (SDIO-version 3.0)
+. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
+
+The Exynos 5250 DWC_mobile_storage provides four channels.
+SOC specific and Board specific properties are channel specific.
+
+Required SoC Specific Properties:
+
+- compatible: should be
+	- samsung,exynos5250-dwmmc: for exynos5250 platforms
+
+- reg: physical base address of the controller and length of memory mapped
+	region.
+
+- interrupts: The interrupt number to the cpu.
+
+Required Board Specific Properties:
+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- samsung,bus-width: The width of the bus used to interface the devices
+	supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
+	. Typically the bus width is 4 or 8.
+- samsung,timing: The timing values to be written into the
+	Drv/sample clock selection register of corresponding channel.
+	. It is comprised of 3 values corresponding to the 3 fileds
+	  'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register.
+	. SelClk_sample: Select sample clock among 8 shifted clocks.
+	. SelClk_drv: Select drv clock among 8 shifted clocks.
+	. DIVRATIO: Clock Divide ratio select.
+	. The above 3 values are used by the clock phase shifter.
+
+Example:
+
+mmc at 12200000 {
+	samsung,bus-width = <8>;
+	samsung,timing = <1 3 3>;
+}
+In the above example,
+	. The bus width is 8
+	. Timing is comprised of 3 values as explained below
+		1 - SelClk_sample
+		3 - SelClk_drv
+		3 - DIVRATIO

This patch adds DWMMC device node data for exynos5. This patch also adds binding file for DWMMC device node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Added binding file for DWMMC device node at the location "doc/device-tree-bindings/exynos/dwmmc.txt".
2)Removed the propname 'index' from device node. 3)Prefixed the vendor name 'samsung' before propname in device node.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
No change.

Changes since V4:
1)Updated the doc/device-tree-bindings/exynos/dwmmc.txt with more information regarding the property 'samsung,timing'. 2)Replaced the name 'dwmmc' with 'mmc'.

 arch/arm/dts/exynos5250.dtsi              | 31 +++++++++++++++++++
 board/samsung/dts/exynos5250-smdk5250.dts | 22 ++++++++++++++
 doc/device-tree-bindings/exynos/dwmmc.txt | 49 +++++++++++++++++++++++++++++++
 3 files changed, 102 insertions(+)
 create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt

arch/arm/dts/exynos5250.dtsi +31 -0

index ed8c8dd..6c08eb7 100644
@@ -151,4 +151,35 @@
                };
        };
 
+       mmc at 12200000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12200000 0x1000>;
+               interrupts = <0 75 0>;
+       };
+
+       mmc at 12210000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12210000 0x1000>;
+               interrupts = <0 76 0>;
+       };
+
+       mmc at 12220000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12220000 0x1000>;
+               interrupts = <0 77 0>;
+       };
+
+       mmc at 12230000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12230000 0x1000>;
+               interrupts = <0 78 0>;
+       };
 };

board/samsung/dts/exynos5250-smdk5250.dts +22 -0

index cbfab6f..1d3e42b 100644
@@ -30,6 +30,10 @@
                spi2 = "/spi at 12d40000";
                spi3 = "/spi at 131a0000";
                spi4 = "/spi at 131b0000";
+               mmc0 = "/mmc at 12200000";
+               mmc1 = "/mmc at 12210000";
+               mmc2 = "/mmc at 12220000";
+               mmc3 = "/mmc at 12230000";
        };
 
        sromc at 12250000 {

@@ -66,4 +70,22 @@
                        compatible = "maxim,max77686_pmic";
                };
        };
+
+       mmc at 12200000 {
+               samsung,bus-width = <8>;
+               samsung,timing = <1 3 3>;
+       };
+
+       mmc at 12210000 {
+               status = "disabled";
+       };
+
+       mmc at 12220000 {
+               samsung,bus-width = <4>;
+               samsung,timing = <1 2 3>;
+       };
+
+       mmc at 12230000 {
+               status = "disabled";
+       };
 };

doc/device-tree-bindings/exynos/dwmmc.txt new file +49 -1

new file mode 100644
index 0000000..0054ace
@@ -0,0 +1,49 @@
+* Exynos 5250 DWC_mobile_storage
+
+The Exynos 5250 provides DWC_mobile_storage interface which supports
+. Embedded Multimedia Cards (EMMC-version 4.5)
+. Secure Digital memory (SD mem-version 2.0)
+. Secure Digital I/O (SDIO-version 3.0)
+. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
+
+The Exynos 5250 DWC_mobile_storage provides four channels.
+SOC specific and Board specific properties are channel specific.
+
+Required SoC Specific Properties:
+
+- compatible: should be
+       - samsung,exynos5250-dwmmc: for exynos5250 platforms
+
+- reg: physical base address of the controller and length of memory mapped
+       region.
+
+- interrupts: The interrupt number to the cpu.
+
+Required Board Specific Properties:
+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- samsung,bus-width: The width of the bus used to interface the devices
+       supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
+       . Typically the bus width is 4 or 8.
+- samsung,timing: The timing values to be written into the
+       Drv/sample clock selection register of corresponding channel.
+       . It is comprised of 3 values corresponding to the 3 fileds
+         'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register.
+       . SelClk_sample: Select sample clock among 8 shifted clocks.
+       . SelClk_drv: Select drv clock among 8 shifted clocks.
+       . DIVRATIO: Clock Divide ratio select.
+       . The above 3 values are used by the clock phase shifter.
+
+Example:
+
+mmc at 12200000 {
+       samsung,bus-width = <8>;
+       samsung,timing = <1 3 3>;
+}
+In the above example,
+       . The bus width is 8
+       . Timing is comprised of 3 values as explained below
+               1 - SelClk_sample
+               3 - SelClk_drv
+               3 - DIVRATIO
--

1.8.0

Hi Amar,

Quoted 5 lines · Amar

This patch adds DWMMC device node data for exynos5. This patch also adds binding file for DWMMC device node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

Can I suggest in a later patch you add a removable flag, so we can mark devices which cannot be removed (and can be assumed to be present). I believe that there is some overhead involved in detecting an MMC (we have to try SD first, and fail).

Quoted 6 lines

---
Changes since V1:
1)Added binding file for DWMMC device node at the location "doc/device-tree-bindings/exynos/dwmmc.txt". 2)Removed the propname 'index' from device node. 3)Prefixed the vendor name 'samsung' before propname in device

node.

Quoted 7 lines

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
No change.

Quoted 8 lines

Changes since V4:
1)Updated the doc/device-tree-bindings/exynos/dwmmc.txt with more information regarding the property 'samsung,timing'. 2)Replaced the name 'dwmmc' with 'mmc'.

 arch/arm/dts/exynos5250.dtsi              | 31 +++++++++++++++++++
 board/samsung/dts/exynos5250-smdk5250.dts | 22 ++++++++++++++
 doc/device-tree-bindings/exynos/dwmmc.txt | 49

+++++++++++++++++++++++++++++++

Review

Quoted 44 lines

 3 files changed, 102 insertions(+)
 create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt

arch/arm/dts/exynos5250.dtsi +31 -0

index ed8c8dd..6c08eb7 100644
@@ -151,4 +151,35 @@
                };
        };
 
+       mmc at 12200000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12200000 0x1000>;
+               interrupts = <0 75 0>;
+       };
+
+       mmc at 12210000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12210000 0x1000>;
+               interrupts = <0 76 0>;
+       };
+
+       mmc at 12220000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12220000 0x1000>;
+               interrupts = <0 77 0>;
+       };
+
+       mmc at 12230000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12230000 0x1000>;
+               interrupts = <0 78 0>;
+       };
 };

(quoted diff) +0 -0

b/board/samsung/dts/exynos5250-smdk5250.dts

Review

Quoted 38 lines

index cbfab6f..1d3e42b 100644

board/samsung/dts/exynos5250-smdk5250.dts +22 -0

@@ -30,6 +30,10 @@
                spi2 = "/spi at 12d40000";
                spi3 = "/spi at 131a0000";
                spi4 = "/spi at 131b0000";
+               mmc0 = "/mmc at 12200000";
+               mmc1 = "/mmc at 12210000";
+               mmc2 = "/mmc at 12220000";
+               mmc3 = "/mmc at 12230000";
        };
 
        sromc at 12250000 {

@@ -66,4 +70,22 @@
                        compatible = "maxim,max77686_pmic";
                };
        };
+
+       mmc at 12200000 {
+               samsung,bus-width = <8>;
+               samsung,timing = <1 3 3>;
+       };
+
+       mmc at 12210000 {
+               status = "disabled";
+       };
+
+       mmc at 12220000 {
+               samsung,bus-width = <4>;
+               samsung,timing = <1 2 3>;
+       };
+
+       mmc at 12230000 {
+               status = "disabled";
+       };
 };

(quoted diff) +0 -0

b/doc/device-tree-bindings/exynos/dwmmc.txt

doc/device-tree-bindings/exynos/dwmmc.txt line 7

Quoted 12 lines

new file mode 100644
index 0000000..0054ace

doc/device-tree-bindings/exynos/dwmmc.txt new file +7 -0

@@ -0,0 +1,49 @@
+* Exynos 5250 DWC_mobile_storage
+
+The Exynos 5250 provides DWC_mobile_storage interface which supports
+. Embedded Multimedia Cards (EMMC-version 4.5)
+. Secure Digital memory (SD mem-version 2.0)
+. Secure Digital I/O (SDIO-version 3.0)
+. Consumer Electronics Advanced Transport Architecture (CE-ATA-version

1.1)

doc/device-tree-bindings/exynos/dwmmc.txt

Quoted 10 lines

doc/device-tree-bindings/exynos/dwmmc.txt new file +10 -0

+
+The Exynos 5250 DWC_mobile_storage provides four channels.
+SOC specific and Board specific properties are channel specific.
+
+Required SoC Specific Properties:
+
+- compatible: should be
+       - samsung,exynos5250-dwmmc: for exynos5250 platforms
+
+- reg: physical base address of the controller and length of memory

mapped

Quoted 5 lines

doc/device-tree-bindings/exynos/dwmmc.txt new file +5 -0

+       region.
+
+- interrupts: The interrupt number to the cpu.
+
+Required Board Specific Properties:

doc/device-tree-bindings/exynos/dwmmc.txt

Quoted 10 lines

doc/device-tree-bindings/exynos/dwmmc.txt new file +10 -0

+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- samsung,bus-width: The width of the bus used to interface the devices
+       supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
+       . Typically the bus width is 4 or 8.
+- samsung,timing: The timing values to be written into the
+       Drv/sample clock selection register of corresponding channel.
+       . It is comprised of 3 values corresponding to the 3 fileds
+         'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL

register.

Quoted 18 lines

doc/device-tree-bindings/exynos/dwmmc.txt new file +17 -1

+       . SelClk_sample: Select sample clock among 8 shifted clocks.
+       . SelClk_drv: Select drv clock among 8 shifted clocks.
+       . DIVRATIO: Clock Divide ratio select.
+       . The above 3 values are used by the clock phase shifter.
+
+Example:
+
+mmc at 12200000 {
+       samsung,bus-width = <8>;
+       samsung,timing = <1 3 3>;
+}
+In the above example,
+       . The bus width is 8
+       . Timing is comprised of 3 values as explained below
+               1 - SelClk_sample
+               3 - SelClk_drv
+               3 - DIVRATIO
--

Quoted 2 lines

1.8.0

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Hi Simon,

You mean to add "removable" flag in device node ?

Are you referring to the overhead involved during MMC boot, and a SD card is not present on the board ?
Can you please elaborate on the above.

Hi Amarendra,

Quoted 3 lines · Amarendra Reddy

Hi Simon,

You mean to add "removable" flag in device node ?

Yes

Quoted 1 line

Are you referring to the overhead involved during MMC boot, and a SD

card is

Quoted 2 lines

not present on the board ?
Can you please elaborate on the above.

From my investigation of the mmc code some months back I found that for the eMMC case we are probing for an SD card, and when that fails, trying eMMC. If we can specify which it is (which we can in the case of a soldered-down device) then we might save that wasted time.

Regards,
Simon

Quoted 43 lines

Thanks & Regards
Amarendra Reddy

Quoted 38 lines · Simon Glass

Hi Amar,

Quoted 5 lines · Amar

This patch adds DWMMC device node data for exynos5. This patch also adds binding file for DWMMC device node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

Can I suggest in a later patch you add a removable flag, so we can mark devices which cannot be removed (and can be assumed to be present). I believe that there is some overhead involved in detecting an MMC (we have to try SD first, and fail).

Quoted 21 lines

---
Changes since V1:
1)Added binding file for DWMMC device node at the location "doc/device-tree-bindings/exynos/dwmmc.txt". 2)Removed the propname 'index' from device node. 3)Prefixed the vendor name 'samsung' before propname in device
node.

Changes since V2:
1)Updation of commit message and resubmition of proper patch
set.

Changes since V3:
No change.

Changes since V4:
1)Updated the doc/device-tree-bindings/exynos/dwmmc.txt with
more
information regarding the property 'samsung,timing'. 2)Replaced the name 'dwmmc' with 'mmc'.

Quoted 8 lines

Quoted 8 lines

Review

Quoted 8 lines

 arch/arm/dts/exynos5250.dtsi              | 31 +++++++++++++++++++
 board/samsung/dts/exynos5250-smdk5250.dts | 22 ++++++++++++++
 doc/device-tree-bindings/exynos/dwmmc.txt | 49
+++++++++++++++++++++++++++++++
 3 files changed, 102 insertions(+)
 create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt

(quoted diff) +0 -0

b/arch/arm/dts/exynos5250.dtsi

Quoted 84 lines

Quoted 84 lines

Quoted 84 lines

index ed8c8dd..6c08eb7 100644

arch/arm/dts/exynos5250.dtsi +31 -0

@@ -151,4 +151,35 @@
                };
        };
 
+       mmc at 12200000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12200000 0x1000>;
+               interrupts = <0 75 0>;
+       };
+
+       mmc at 12210000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12210000 0x1000>;
+               interrupts = <0 76 0>;
+       };
+
+       mmc at 12220000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12220000 0x1000>;
+               interrupts = <0 77 0>;
+       };
+
+       mmc at 12230000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos5250-dwmmc";
+               reg = <0x12230000 0x1000>;
+               interrupts = <0 78 0>;
+       };
 };

board/samsung/dts/exynos5250-smdk5250.dts +22 -0

index cbfab6f..1d3e42b 100644
@@ -30,6 +30,10 @@
                spi2 = "/spi at 12d40000";
                spi3 = "/spi at 131a0000";
                spi4 = "/spi at 131b0000";
+               mmc0 = "/mmc at 12200000";
+               mmc1 = "/mmc at 12210000";
+               mmc2 = "/mmc at 12220000";
+               mmc3 = "/mmc at 12230000";
        };
 
        sromc at 12250000 {

@@ -66,4 +70,22 @@
                        compatible = "maxim,max77686_pmic";
                };
        };
+
+       mmc at 12200000 {
+               samsung,bus-width = <8>;
+               samsung,timing = <1 3 3>;
+       };
+
+       mmc at 12210000 {
+               status = "disabled";
+       };
+
+       mmc at 12220000 {
+               samsung,bus-width = <4>;
+               samsung,timing = <1 2 3>;
+       };
+
+       mmc at 12230000 {
+               status = "disabled";
+       };
 };

doc/device-tree-bindings/exynos/dwmmc.txt new file +0 -0

new file mode 100644
index 0000000..0054ace

Quoted 8 lines

Quoted 8 lines

doc/device-tree-bindings/exynos/dwmmc.txt line 7

Quoted 8 lines

doc/device-tree-bindings/exynos/dwmmc.txt new file +7 -0

@@ -0,0 +1,49 @@
+* Exynos 5250 DWC_mobile_storage
+
+The Exynos 5250 provides DWC_mobile_storage interface which supports
+. Embedded Multimedia Cards (EMMC-version 4.5)
+. Secure Digital memory (SD mem-version 2.0)
+. Secure Digital I/O (SDIO-version 3.0)
+. Consumer Electronics Advanced Transport Architecture

(CE-ATA-version

Quoted 13 lines

Quoted 13 lines

Quoted 13 lines

1.1)

doc/device-tree-bindings/exynos/dwmmc.txt new file +10 -0

+
+The Exynos 5250 DWC_mobile_storage provides four channels.
+SOC specific and Board specific properties are channel specific.
+
+Required SoC Specific Properties:
+
+- compatible: should be
+       - samsung,exynos5250-dwmmc: for exynos5250 platforms
+
+- reg: physical base address of the controller and length of memory

mapped
+ region.

Quoted 8 lines

Quoted 8 lines

doc/device-tree-bindings/exynos/dwmmc.txt

Quoted 8 lines

doc/device-tree-bindings/exynos/dwmmc.txt new file +8 -0

+
+- interrupts: The interrupt number to the cpu.
+
+Required Board Specific Properties:
+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- samsung,bus-width: The width of the bus used to interface the

devices

Quoted 33 lines

Quoted 31 lines

Quoted 25 lines

doc/device-tree-bindings/exynos/dwmmc.txt new file +6 -0

+       supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
+       . Typically the bus width is 4 or 8.
+- samsung,timing: The timing values to be written into the
+       Drv/sample clock selection register of corresponding channel.
+       . It is comprised of 3 values corresponding to the 3 fileds
+         'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL

register.

doc/device-tree-bindings/exynos/dwmmc.txt new file +17 -1

+       . SelClk_sample: Select sample clock among 8 shifted clocks.
+       . SelClk_drv: Select drv clock among 8 shifted clocks.
+       . DIVRATIO: Clock Divide ratio select.
+       . The above 3 values are used by the clock phase shifter.
+
+Example:
+
+mmc at 12200000 {
+       samsung,bus-width = <8>;
+       samsung,timing = <1 3 3>;
+}
+In the above example,
+       . The bus width is 8
+       . Timing is comprised of 3 values as explained below
+               1 - SelClk_sample
+               3 - SelClk_drv
+               3 - DIVRATIO
--

Quoted 2 lines

1.8.0

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This patch enumerates dwmci and set auto stop command during dwmci initialisation.
EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence Modified the fifo size computation to resolve EMMC read write issues.

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header file.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10).

Changes since V4:
1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1).

 drivers/mmc/dw_mmc.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

drivers/mmc/dw_mmc.c +0 -0

index 4070d4e..391ed93 100644

drivers/mmc/dw_mmc.c +16 -7

 	u32 retry = 10000;
 	u32 mask, ctrl;
+	ulong start = get_timer(0);
 
 	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
-		if (timeout == 0) {
+		if (get_timer(start) > timeout) {
 			printf("Timeout on data busy\n");
 			return TIMEOUT;
 		}
-		timeout--;
 	}
 
 	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

@@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	if (data)
 		dwmci_prepare_data(host, data);
 
-
 	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 
 	if (data)

@@ -314,7 +313,7 @@ static void dwmci_set_ios(struct mmc *mmc)
 static int dwmci_init(struct mmc *mmc)
 {
 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
-	u32 fifo_size, fifoth_val;
+	u32 fifo_size, fifoth_val, ier;
 
 	dwmci_writel(host, DWMCI_PWREN, 1);
 

@@ -323,6 +322,14 @@ static int dwmci_init(struct mmc *mmc)
 		return -1;
 	}
 
+	/* Enumerate at 400KHz */
+	dwmci_setup_bus(host, mmc->f_min);
+
+	/* Set auto stop command */
+	ier = dwmci_readl(host, DWMCI_CTRL);
+	ier |= DWMCI_CTRL_SEND_AS_CCSD;
+	dwmci_writel(host, DWMCI_CTRL, ier);
+
 	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 	dwmci_writel(host, DWMCI_INTMASK, 0);
 

@@ -332,11 +339,13 @@ static int dwmci_init(struct mmc *mmc)
 	dwmci_writel(host, DWMCI_BMOD, 1);
 
 	fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+	fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
 	if (host->fifoth_val)
 		fifoth_val = host->fifoth_val;
-	else
-		fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
-			TX_WMARK(fifo_size/2);
+	else {
+		fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+			TX_WMARK(fifo_size / 2);
+	}
 	dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
 
 	dwmci_writel(host, DWMCI_CLKENA, 0);

Hi Amar,

Quoted 10 lines · Amar

This patch enumerates dwmci and set auto stop command during dwmci initialisation.
EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence Modified the fifo size computation to resolve EMMC read write issues.

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header

file.

Quoted 10 lines

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10).

Changes since V4:
1)Updated the function dwmci_send_cmd() to use get_timer()

instead

drivers/mmc/dw_mmc.c static int dwmci_send_cmd(struct mmc *mmc, struct

Quoted 10 lines

of using mdelay(1).

 drivers/mmc/dw_mmc.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

drivers/mmc/dw_mmc.c +0 -0

index 4070d4e..391ed93 100644
@@ -129,13 +129,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct

mmc_cmd *cmd,

drivers/mmc/dw_mmc.c static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, · line 129

Quoted 1 line

drivers/mmc/dw_mmc.c +0 -0

      unsigned int timeout = 100000;

We can remove the timeout value.
If you remove this, it looks good to me.

Acked-by Jaehoon Chung <[email protected]>

Best Regards,
Jaehoon Chung

drivers/mmc/dw_mmc.c static int dwmci_send_cmd(struct mmc *mmc, struct

Quoted 15 lines

drivers/mmc/dw_mmc.c +2 -2

      u32 retry = 10000;
      u32 mask, ctrl;
+     ulong start = get_timer(0);
 
      while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
-             if (timeout == 0) {
+             if (get_timer(start) > timeout) {
                      printf("Timeout on data busy\n");
                      return TIMEOUT;
              }
-             timeout--;
      }
 
      dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

@@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct

mmc_cmd *cmd,

Quoted 39 lines

drivers/mmc/dw_mmc.c +10 -2

      if (data)
              dwmci_prepare_data(host, data);
 
-
      dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 
      if (data)

@@ -314,7 +313,7 @@ static void dwmci_set_ios(struct mmc *mmc)
 static int dwmci_init(struct mmc *mmc)
 {
      struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
-     u32 fifo_size, fifoth_val;
+     u32 fifo_size, fifoth_val, ier;
 
      dwmci_writel(host, DWMCI_PWREN, 1);
 

@@ -323,6 +322,14 @@ static int dwmci_init(struct mmc *mmc)
              return -1;
      }
 
+     /* Enumerate at 400KHz */
+     dwmci_setup_bus(host, mmc->f_min);
+
+     /* Set auto stop command */
+     ier = dwmci_readl(host, DWMCI_CTRL);
+     ier |= DWMCI_CTRL_SEND_AS_CCSD;
+     dwmci_writel(host, DWMCI_CTRL, ier);
+
      dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
      dwmci_writel(host, DWMCI_INTMASK, 0);
 

@@ -332,11 +339,13 @@ static int dwmci_init(struct mmc *mmc)
      dwmci_writel(host, DWMCI_BMOD, 1);
 
      fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+     fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
      if (host->fifoth_val)
              fifoth_val = host->fifoth_val;

drivers/mmc/dw_mmc.c static int dwmci_init(struct mmc *mmc) · line 351

Quoted 10 lines

drivers/mmc/dw_mmc.c +4 -3

-     else
-             fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
-                     TX_WMARK(fifo_size/2);
+     else {
+             fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+                     TX_WMARK(fifo_size / 2);
+     }
      dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
 
      dwmci_writel(host, DWMCI_CLKENA, 0);

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Hi Jaehoon,
The 'timeout' value cant be removed as it is being used.

Thanks & Regards
Amarendra

Quoted 107 lines · Jaehoon Chung

Hi Amar,

Quoted 10 lines · Amar

This patch enumerates dwmci and set auto stop command during dwmci initialisation.
EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence Modified the fifo size computation to resolve EMMC read write issues.

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header

file.

Quoted 10 lines

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10).

Changes since V4:
1)Updated the function dwmci_send_cmd() to use get_timer()

instead

drivers/mmc/dw_mmc.c static int dwmci_send_cmd(struct mmc *mmc, struct

Quoted 10 lines

of using mdelay(1).

 drivers/mmc/dw_mmc.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

drivers/mmc/dw_mmc.c +0 -0

index 4070d4e..391ed93 100644
@@ -129,13 +129,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct

mmc_cmd *cmd,

drivers/mmc/dw_mmc.c static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, · line 129

Quoted 1 line

drivers/mmc/dw_mmc.c +0 -0

      unsigned int timeout = 100000;

We can remove the timeout value.
If you remove this, it looks good to me.

Acked-by Jaehoon Chung <[email protected]>

Best Regards,
Jaehoon Chung

drivers/mmc/dw_mmc.c static int dwmci_send_cmd(struct mmc *mmc, struct

Quoted 15 lines

drivers/mmc/dw_mmc.c +2 -2

      u32 retry = 10000;
      u32 mask, ctrl;
+     ulong start = get_timer(0);
 
      while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
-             if (timeout == 0) {
+             if (get_timer(start) > timeout) {
                      printf("Timeout on data busy\n");
                      return TIMEOUT;
              }
-             timeout--;
      }
 
      dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

@@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct

mmc_cmd *cmd,

Quoted 47 lines

drivers/mmc/dw_mmc.c +14 -5

      if (data)
              dwmci_prepare_data(host, data);
 
-
      dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 
      if (data)

@@ -314,7 +313,7 @@ static void dwmci_set_ios(struct mmc *mmc)
 static int dwmci_init(struct mmc *mmc)
 {
      struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
-     u32 fifo_size, fifoth_val;
+     u32 fifo_size, fifoth_val, ier;
 
      dwmci_writel(host, DWMCI_PWREN, 1);
 

@@ -323,6 +322,14 @@ static int dwmci_init(struct mmc *mmc)
              return -1;
      }
 
+     /* Enumerate at 400KHz */
+     dwmci_setup_bus(host, mmc->f_min);
+
+     /* Set auto stop command */
+     ier = dwmci_readl(host, DWMCI_CTRL);
+     ier |= DWMCI_CTRL_SEND_AS_CCSD;
+     dwmci_writel(host, DWMCI_CTRL, ier);
+
      dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
      dwmci_writel(host, DWMCI_INTMASK, 0);
 

@@ -332,11 +339,13 @@ static int dwmci_init(struct mmc *mmc)
      dwmci_writel(host, DWMCI_BMOD, 1);
 
      fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+     fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
      if (host->fifoth_val)
              fifoth_val = host->fifoth_val;
-     else
-             fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
-                     TX_WMARK(fifo_size/2);
+     else {
+             fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+                     TX_WMARK(fifo_size / 2);
+     }
      dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
 

Quoted 8 lines

drivers/mmc/dw_mmc.c static int dwmci_init(struct mmc *mmc) · line 351

Quoted 2 lines

drivers/mmc/dw_mmc.c +0 -0

      dwmci_writel(host, DWMCI_CLKENA, 0);

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U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

This patch enumerates dwmci and set auto stop command during dwmci initialisation.
EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence Modified the fifo size computation to resolve EMMC read write issues.

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header file.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10).

Changes since V4:
1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1).

 drivers/mmc/dw_mmc.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

drivers/mmc/dw_mmc.c +8 -0

index 4070d4e..391ed93 100644
@@ -323,6 +322,14 @@ static int dwmci_init(struct mmc *mmc)
                return -1;
        }
 
+       /* Enumerate at 400KHz */
+       dwmci_setup_bus(host, mmc->f_min);
+
+       /* Set auto stop command */
+       ier = dwmci_readl(host, DWMCI_CTRL);
+       ier |= DWMCI_CTRL_SEND_AS_CCSD;
+       dwmci_writel(host, DWMCI_CTRL, ier);
+
        dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
        dwmci_writel(host, DWMCI_INTMASK, 0);
 

drivers/mmc/dw_mmc.c +4 -4

-       else
-               fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
-                       TX_WMARK(fifo_size/2);
+       else {
+               fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+                       TX_WMARK(fifo_size / 2);
+       }
        dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
 
        dwmci_writel(host, DWMCI_CLKENA, 0);
--

1.8.0

Quoted 7 lines · Amar

This patch enumerates dwmci and set auto stop command during dwmci initialisation.
EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence Modified the fifo size computation to resolve EMMC read write issues.

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

(nit below if you resend for other reason)

Quoted 3 lines

---
Changes since V1:
1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header

file.

Quoted 10 lines

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10).

Changes since V4:
1)Updated the function dwmci_send_cmd() to use get_timer()

instead

Quoted 28 lines

of using mdelay(1).

 drivers/mmc/dw_mmc.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

drivers/mmc/dw_mmc.c +8 -0

index 4070d4e..391ed93 100644
@@ -323,6 +322,14 @@ static int dwmci_init(struct mmc *mmc)
                return -1;
        }
 
+       /* Enumerate at 400KHz */
+       dwmci_setup_bus(host, mmc->f_min);
+
+       /* Set auto stop command */
+       ier = dwmci_readl(host, DWMCI_CTRL);
+       ier |= DWMCI_CTRL_SEND_AS_CCSD;
+       dwmci_writel(host, DWMCI_CTRL, ier);
+
        dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
        dwmci_writel(host, DWMCI_INTMASK, 0);
 

@@ -332,11 +339,13 @@ static int dwmci_init(struct mmc *mmc)
        dwmci_writel(host, DWMCI_BMOD, 1);
 

drivers/mmc/dw_mmc.c static int dwmci_init(struct mmc *mmc) · line 344

Quoted 4 lines

drivers/mmc/dw_mmc.c +1 -0

        fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+       fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
        if (host->fifoth_val)
                fifoth_val = host->fifoth_val;

should be {} around this I think.

Quoted 12 lines

drivers/mmc/dw_mmc.c +4 -4

-       else
-               fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
-                       TX_WMARK(fifo_size/2);
+       else {
+               fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+                       TX_WMARK(fifo_size / 2);
+       }
        dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
 
        dwmci_writel(host, DWMCI_CLKENA, 0);
--

Quoted 2 lines

1.8.0

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This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 2)Computation of FSYS block clock divisor (pre-ratio) is added.

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int bus_width)" with int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will use exynos_dwmmc_add_port() for every channel enabled in device node.
2)Changed the computation method of mmc clock divisor.
3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within the function.

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127 ++++++++++++++++++++++++++++---
 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -7

index 8acdf9b..3b147b8 100644
@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x)   ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-       unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-       return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);

drivers/mmc/exynos_dw_mmc.c +27 -7

index 72a31b7..1d09e56 100644
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define        DWMMC_MAX_CH_NUM                4
+#define        DWMMC_MAX_FREQ                  52000000
+#define        DWMMC_MIN_FREQ                  400000
+#define        DWMMC_MMC0_CLKSEL_VAL           0x03030001
+#define        DWMMC_MMC2_CLKSEL_VAL           0x03020001
 
+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-       u32 val;
-       val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-               DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
+       dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-       dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+       return get_mmc_clk(dev_index);
 }
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -     mmc channel number.
+ * regbase -   register base address of mmc channel specified in 'index'.
+ * bus_width - operating bus width of mmc channel specified in 'index'.
+ * clksel -    value to be written into CLKSEL register in case of FDT.
+ *             NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
 {

drivers/mmc/exynos_dw_mmc.c +4 -0

+               host->clksel_val = clksel;
+       else {
+               if (0 == index)
+                       host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;

drivers/mmc/exynos_dw_mmc.c +67 -2

+               return -1;
+       }
+       return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+       int index, bus_width;
+       int node_list[DWMMC_MAX_CH_NUM];
+       int err = 0, dev_id, flag, count, i;
+       u32 clksel_val, base, timing[3];
+
+       count = fdtdec_find_aliases_for_id(blob, "mmc",
+                               COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+                               DWMMC_MAX_CH_NUM);
+
+       for (i = 0; i < count; i++) {
+               int node = node_list[i];
+
+               if (node <= 0)
+                       continue;
 
-       add_dwmci(host, 52000000, 400000);
+               /* Extract device id for each mmc channel */
+               dev_id = pinmux_decode_periph_id(blob, node);
 
+               /* Get the bus width from the device node */
+               bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+               if (bus_width <= 0) {
+                       debug("DWMMC: Can't get bus-width\n");
+                       return -1;
+               }
+               if (8 == bus_width)
+                       flag = PINMUX_FLAG_8BIT_MODE;
+               else
+                       flag = PINMUX_FLAG_NONE;
+
+               /* config pinmux for each mmc channel */
+               err = exynos_pinmux_config(dev_id, flag);
+               if (err) {
+                       debug("DWMMC not configured\n");
+                       return err;
+               }
+
+               index = dev_id - PERIPH_ID_SDMMC0;
+
+               /* Get the base address from the device node */
+               base = fdtdec_get_addr(blob, node, "reg");
+               if (!base) {
+                       debug("DWMMC: Can't get base address\n");
+                       return -1;
+               }
+               /* Extract the timing info from the node */
+               err = fdtdec_get_int_array(blob, node, "samsung,timing",
+                                       timing, 3);
+               if (err) {
+                       debug("Can't get sdr-timings for divider\n");
+                       return -1;
+               }
+
+               clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+                               DWMCI_SET_DRV_CLK(timing[1]) |
+                               DWMCI_SET_DIV_RATIO(timing[2]));
+               /* Initialise each mmc channel */
+               err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
+               if (err)
+                       debug("dwmmc Channel-%d init failed\n", index);
+       }
        return 0;
 }
-
+#endif

include/dwmmc.h +3 -1

index c8b1d40..e142f3e 100644
@@ -123,6 +123,8 @@
 #define MSIZE(x)               ((x) << 28)
 #define RX_WMARK(x)            ((x) << 16)
 #define TX_WMARK(x)            (x)
+#define RX_WMARK_SHIFT         16
+#define RX_WMARK_MASK          (0xfff << RX_WMARK_SHIFT)
 
 #define DWMCI_IDMAC_OWN                (1 << 31)
 #define DWMCI_IDMAC_CH         (1 << 4)

@@ -144,6 +146,7 @@ struct dwmci_host {
        unsigned int bus_hz;
        int dev_index;
        int buswidth;
+       u32 clksel_val;
        u32 fifoth_val;
        struct mmc *mmc;
 
--

1.8.0

Hi,

Quoted 6 lines · Amar

This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

See below for nit/question.

Quoted 9 lines

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.

Quoted 6 lines

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the

purpose.

Quoted 4 lines

2)Computation of FSYS block clock divisor (pre-ratio) is added.

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int

bus_width)" with

Quoted 3 lines

int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will

use

Quoted 1 line

exynos_dwmmc_add_port() for every channel enabled in

device node.

Quoted 2 lines

2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within

the function.

Quoted 3 lines

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127

++++++++++++++++++++++++++++---

Review

Quoted 4 lines

 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/dwmmc.h

Quoted 8 lines

index 8acdf9b..3b147b8 100644

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -1

@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x)   ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);

arch/arm/include/asm/arch-exynos/dwmmc.h line 33

Quoted 10 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -6

-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-       unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-       return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel);

Quoted 23 lines

drivers/mmc/exynos_dw_mmc.c +9 -2

index 72a31b7..1d09e56 100644
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define        DWMMC_MAX_CH_NUM                4
+#define        DWMMC_MAX_FREQ                  52000000
+#define        DWMMC_MIN_FREQ                  400000
+#define        DWMMC_MMC0_CLKSEL_VAL           0x03030001
+#define        DWMMC_MMC2_CLKSEL_VAL           0x03020001

drivers/mmc/exynos_dw_mmc.c line 33

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +4 -3

 
+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-       u32 val;
-       val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-               DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) |

DWMCI_SET_DIV_RATIO(0);

Quoted 4 lines

drivers/mmc/exynos_dw_mmc.c +2 -1

+       dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-       dwmci_writel(host, DWMCI_CLKSEL, val);

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +7 -1

+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+       return get_mmc_clk(dev_index);
 }
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -     mmc channel number.
+ * regbase -   register base address of mmc channel specified in

'index'.

drivers/mmc/exynos_dw_mmc.c

Quoted 5 lines

drivers/mmc/exynos_dw_mmc.c +5 -0

+ * bus_width - operating bus width of mmc channel specified in 'index'.
+ * clksel -    value to be written into CLKSEL register in case of FDT.
+ *             NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel)

drivers/mmc/exynos_dw_mmc.c line 69

Quoted 11 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

 {
        struct dwmci_host *host = NULL;
+       unsigned int div;
+       unsigned long freq, sclk;
        host = malloc(sizeof(struct dwmci_host));
        if (!host) {
                printf("dwmci_host malloc fail!\n");
                return 1;
        }
+       /* request mmc clock vlaue of 50MHz.  */
+       freq = 50000000;

Should this be 52MHz?

Quoted 6 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+       sclk = get_mmc_clk(index);
+       div = DIV_ROUND_UP(sclk, freq);
+       /* set the clock divisor for mmc */
+       set_mmc_clk(index, div);
 

drivers/mmc/exynos_dw_mmc.c line 79

Quoted 6 lines

drivers/mmc/exynos_dw_mmc.c +3 -1

-       host->name = EXYNOS_NAME;
+       host->name = "EXYNOS DWMMC";
        host->ioaddr = (void *)regbase;
        host->buswidth = bus_width;
+
+       if (clksel)

{} around if() part since you have it for else.

Quoted 4 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+               host->clksel_val = clksel;
+       else {
+               if (0 == index)
+                       host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;

drivers/mmc/exynos_dw_mmc.c line 93

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +8 -0

+               if (2 == index)
+                       host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+       }
+
        host->clksel = exynos_dwmci_clksel;
        host->dev_index = index;
+       host->mmc_clk = exynos_dwmci_get_clk;
+       /* Add the mmc channel to be registered with mmc core */
+       if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+               printf("dwmmc%d registration failed\n", index);

Should this be debug()?

drivers/mmc/exynos_dw_mmc.c +19 -0

+               return -1;
+       }
+       return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+       int index, bus_width;
+       int node_list[DWMMC_MAX_CH_NUM];
+       int err = 0, dev_id, flag, count, i;
+       u32 clksel_val, base, timing[3];
+
+       count = fdtdec_find_aliases_for_id(blob, "mmc",
+                               COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+                               DWMMC_MAX_CH_NUM);
+
+       for (i = 0; i < count; i++) {
+               int node = node_list[i];

drivers/mmc/exynos_dw_mmc.c +27 -0

+               if (bus_width <= 0) {
+                       debug("DWMMC: Can't get bus-width\n");
+                       return -1;
+               }
+               if (8 == bus_width)
+                       flag = PINMUX_FLAG_8BIT_MODE;
+               else
+                       flag = PINMUX_FLAG_NONE;
+
+               /* config pinmux for each mmc channel */
+               err = exynos_pinmux_config(dev_id, flag);
+               if (err) {
+                       debug("DWMMC not configured\n");
+                       return err;
+               }
+
+               index = dev_id - PERIPH_ID_SDMMC0;
+
+               /* Get the base address from the device node */
+               base = fdtdec_get_addr(blob, node, "reg");
+               if (!base) {
+                       debug("DWMMC: Can't get base address\n");
+                       return -1;
+               }
+               /* Extract the timing info from the node */
+               err = fdtdec_get_int_array(blob, node, "samsung,timing",
+                                       timing, 3);

drivers/mmc/exynos_dw_mmc.c +4 -1

+               if (err)
+                       debug("dwmmc Channel-%d init failed\n", index);
+       }
        return 0;
 }
-
+#endif

include/dwmmc.h +3 -1

index c8b1d40..e142f3e 100644
@@ -123,6 +123,8 @@
 #define MSIZE(x)               ((x) << 28)
 #define RX_WMARK(x)            ((x) << 16)
 #define TX_WMARK(x)            (x)
+#define RX_WMARK_SHIFT         16
+#define RX_WMARK_MASK          (0xfff << RX_WMARK_SHIFT)
 
 #define DWMCI_IDMAC_OWN                (1 << 31)
 #define DWMCI_IDMAC_CH         (1 << 4)

@@ -144,6 +146,7 @@ struct dwmci_host {
        unsigned int bus_hz;
        int dev_index;
        int buswidth;
+       u32 clksel_val;
        u32 fifoth_val;
        struct mmc *mmc;
 
--

1.8.0

Simon
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Hi Simon,

Please find the responses below.

Thanks & Regards
Amarendra

Quoted 135 lines · Simon Glass

Hi,

Quoted 6 lines · Amar

This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

See below for nit/question.

Quoted 120 lines

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.

Changes since V2:
1)Updation of commit message and resubmition of proper patch
set.

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the
purpose.
2)Computation of FSYS block clock divisor (pre-ratio) is added.

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int
bus_width)" with
int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT
boards.
ii)In FDT case, exynos_dwmmc_init(const void *blob) will
use
exynos_dwmmc_add_port() for every channel enabled in
device node.
2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within
the function.

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127
++++++++++++++++++++++++++++---
 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -7

index 8acdf9b..3b147b8 100644
@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x)   ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-       unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-       return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel);

drivers/mmc/exynos_dw_mmc.c +22 -7

index 72a31b7..1d09e56 100644
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define        DWMMC_MAX_CH_NUM                4
+#define        DWMMC_MAX_FREQ                  52000000
+#define        DWMMC_MIN_FREQ                  400000
+#define        DWMMC_MMC0_CLKSEL_VAL           0x03030001
+#define        DWMMC_MMC2_CLKSEL_VAL           0x03020001
 
+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-       u32 val;
-       val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-               DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) |
 DWMCI_SET_DIV_RATIO(0);
+       dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-       dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+       return get_mmc_clk(dev_index);
 }
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -     mmc channel number.
+ * regbase -   register base address of mmc channel specified in

'index'.
+ * bus_width - operating bus width of mmc channel specified in 'index'.
+ * clksel - value to be written into CLKSEL register in case of FDT.
+ * NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)

 {
        struct dwmci_host *host = NULL;

drivers/mmc/exynos_dw_mmc.c +2 -0

+       unsigned int div;
+       unsigned long freq, sclk;
        host = malloc(sizeof(struct dwmci_host));

Quoted 8 lines

drivers/mmc/exynos_dw_mmc.c line 69

Quoted 6 lines

        if (!host) {
                printf("dwmci_host malloc fail!\n");
                return 1;
        }

drivers/mmc/exynos_dw_mmc.c +2 -0

+       /* request mmc clock vlaue of 50MHz.  */
+       freq = 50000000;

Should this be 52MHz?

Ok shall change it to 52MHz.

Quoted 7 lines

Quoted 7 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+       sclk = get_mmc_clk(index);
+       div = DIV_ROUND_UP(sclk, freq);
+       /* set the clock divisor for mmc */
+       set_mmc_clk(index, div);

Quoted 9 lines

drivers/mmc/exynos_dw_mmc.c line 79

Quoted 6 lines

drivers/mmc/exynos_dw_mmc.c +3 -1

-       host->name = EXYNOS_NAME;
+       host->name = "EXYNOS DWMMC";
        host->ioaddr = (void *)regbase;
        host->buswidth = bus_width;
+
+       if (clksel)

{} around if() part since you have it for else.

Ok will put {} around if() part.

Quoted 16 lines

Quoted 15 lines

drivers/mmc/exynos_dw_mmc.c +12 -0

+               host->clksel_val = clksel;
+       else {
+               if (0 == index)
+                       host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+               if (2 == index)
+                       host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+       }
+
        host->clksel = exynos_dwmci_clksel;
        host->dev_index = index;
+       host->mmc_clk = exynos_dwmci_get_clk;
+       /* Add the mmc channel to be registered with mmc core */
+       if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+               printf("dwmmc%d registration failed\n", index);

Quoted 1 line

Should this be debug()?

I think it should be printf(), because if the mmc channel registration fails, then this failure information needs to be conveyed to the user. This will happen if printf() is used.
If debug() is used, then the statement will be printed only when the DEBUG is defined.

Quoted 107 lines

drivers/mmc/exynos_dw_mmc.c +26 -1

+               return -1;
+       }
+       return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+       int index, bus_width;
+       int node_list[DWMMC_MAX_CH_NUM];
+       int err = 0, dev_id, flag, count, i;
+       u32 clksel_val, base, timing[3];
+
+       count = fdtdec_find_aliases_for_id(blob, "mmc",
+                               COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+                               DWMMC_MAX_CH_NUM);
+
+       for (i = 0; i < count; i++) {
+               int node = node_list[i];
+
+               if (node <= 0)
+                       continue;
 
-       add_dwmci(host, 52000000, 400000);
+               /* Extract device id for each mmc channel */
+               dev_id = pinmux_decode_periph_id(blob, node);
 
+               /* Get the bus width from the device node */
+               bus_width = fdtdec_get_int(blob, node,

"samsung,bus-width", 0);

drivers/mmc/exynos_dw_mmc.c +37 -0

+               if (bus_width <= 0) {
+                       debug("DWMMC: Can't get bus-width\n");
+                       return -1;
+               }
+               if (8 == bus_width)
+                       flag = PINMUX_FLAG_8BIT_MODE;
+               else
+                       flag = PINMUX_FLAG_NONE;
+
+               /* config pinmux for each mmc channel */
+               err = exynos_pinmux_config(dev_id, flag);
+               if (err) {
+                       debug("DWMMC not configured\n");
+                       return err;
+               }
+
+               index = dev_id - PERIPH_ID_SDMMC0;
+
+               /* Get the base address from the device node */
+               base = fdtdec_get_addr(blob, node, "reg");
+               if (!base) {
+                       debug("DWMMC: Can't get base address\n");
+                       return -1;
+               }
+               /* Extract the timing info from the node */
+               err = fdtdec_get_int_array(blob, node, "samsung,timing",
+                                       timing, 3);
+               if (err) {
+                       debug("Can't get sdr-timings for divider\n");
+                       return -1;
+               }
+
+               clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+                               DWMCI_SET_DRV_CLK(timing[1]) |
+                               DWMCI_SET_DIV_RATIO(timing[2]));
+               /* Initialise each mmc channel */
+               err = exynos_dwmci_add_port(index, base, bus_width,

clksel_val);

drivers/mmc/exynos_dw_mmc.c +4 -1

+               if (err)
+                       debug("dwmmc Channel-%d init failed\n", index);
+       }
        return 0;
 }
-
+#endif

include/dwmmc.h +3 -1

index c8b1d40..e142f3e 100644
@@ -123,6 +123,8 @@
 #define MSIZE(x)               ((x) << 28)
 #define RX_WMARK(x)            ((x) << 16)
 #define TX_WMARK(x)            (x)
+#define RX_WMARK_SHIFT         16
+#define RX_WMARK_MASK          (0xfff << RX_WMARK_SHIFT)
 
 #define DWMCI_IDMAC_OWN                (1 << 31)
 #define DWMCI_IDMAC_CH         (1 << 4)

@@ -144,6 +146,7 @@ struct dwmci_host {
        unsigned int bus_hz;
        int dev_index;
        int buswidth;
+       u32 clksel_val;
        u32 fifoth_val;
        struct mmc *mmc;
 
--

1.8.0

Regards,
Simon
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Hi Amarendra,

Quoted 12 lines · Amarendra Reddy

Hi Simon,

Please find the responses below.

Thanks & Regards
Amarendra

Quoted 4 lines · Simon Glass

Hi,

On Tue, Jan 22, 2013 at 12:43 AM, Amar <[email protected]>

Quoted 11 lines · wrote:

Quoted 11 lines

Quoted 6 lines

This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

See below for nit/question.

Quoted 7 lines

Quoted 7 lines

Quoted 7 lines

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from

FDT.

Quoted 11 lines

Quoted 11 lines

Quoted 11 lines

4)Channel index is computed instead of getting from FDT.

Changes since V2:
1)Updation of commit message and resubmition of proper patch
set.

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the
purpose.
2)Computation of FSYS block clock divisor (pre-ratio) is

added.

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int
bus_width)" with
int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT
boards.
ii)In FDT case, exynos_dwmmc_init(const void *blob)

will

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

use
exynos_dwmmc_add_port() for every channel enabled in
device node.
2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val'

within

Quoted 17 lines

Quoted 17 lines

Quoted 17 lines

the function.

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127
++++++++++++++++++++++++++++---
 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -0

index 8acdf9b..3b147b8 100644
@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x)   ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
 

Quoted 3 lines

Quoted 3 lines

arch/arm/include/asm/arch-exynos/dwmmc.h

Quoted 3 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -3

-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-
-static inline unsigned int exynos_dwmmc_init(int index, int

bus_width)

Quoted 2 lines

Quoted 2 lines

arch/arm/include/asm/arch-exynos/dwmmc.h line 34

Quoted 2 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -2

-{
-       unsigned int base = samsung_get_base_mmc() + (0x10000 *

index);

Quoted 50 lines

Quoted 50 lines

Quoted 50 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -2

-       return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel);

drivers/mmc/exynos_dw_mmc.c +18 -6

index 72a31b7..1d09e56 100644
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define        DWMMC_MAX_CH_NUM                4
+#define        DWMMC_MAX_FREQ                  52000000
+#define        DWMMC_MIN_FREQ                  400000
+#define        DWMMC_MMC0_CLKSEL_VAL           0x03030001
+#define        DWMMC_MMC2_CLKSEL_VAL           0x03020001
 
+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-       u32 val;
-       val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-               DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) |
 DWMCI_SET_DIV_RATIO(0);
+       dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-       dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+       return get_mmc_clk(dev_index);
 }
 

Quoted 7 lines

Quoted 7 lines

Quoted 7 lines

drivers/mmc/exynos_dw_mmc.c +4 -1

-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -     mmc channel number.
+ * regbase -   register base address of mmc channel specified in

'index'.
+ * bus_width - operating bus width of mmc channel specified in

'index'.

Quoted 1 line

Quoted 1 line

Quoted 1 line

+ * clksel - value to be written into CLKSEL register in case of

FDT.

Quoted 54 lines

Quoted 16 lines

Quoted 6 lines

+ * NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)

 {
        struct dwmci_host *host = NULL;

drivers/mmc/exynos_dw_mmc.c line 69

Quoted 9 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+       unsigned int div;
+       unsigned long freq, sclk;
        host = malloc(sizeof(struct dwmci_host));
        if (!host) {
                printf("dwmci_host malloc fail!\n");
                return 1;
        }
+       /* request mmc clock vlaue of 50MHz.  */
+       freq = 50000000;

Quoted 1 line

Should this be 52MHz?

Ok shall change it to 52MHz.

Quoted 7 lines

Quoted 7 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+       sclk = get_mmc_clk(index);
+       div = DIV_ROUND_UP(sclk, freq);
+       /* set the clock divisor for mmc */
+       set_mmc_clk(index, div);

Quoted 9 lines

drivers/mmc/exynos_dw_mmc.c line 79

Quoted 6 lines

drivers/mmc/exynos_dw_mmc.c +3 -1

-       host->name = EXYNOS_NAME;
+       host->name = "EXYNOS DWMMC";
        host->ioaddr = (void *)regbase;
        host->buswidth = bus_width;
+
+       if (clksel)

{} around if() part since you have it for else.

Ok will put {} around if() part.

Quoted 16 lines

Quoted 15 lines

drivers/mmc/exynos_dw_mmc.c +12 -0

+               host->clksel_val = clksel;
+       else {
+               if (0 == index)
+                       host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+               if (2 == index)
+                       host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+       }
+
        host->clksel = exynos_dwmci_clksel;
        host->dev_index = index;
+       host->mmc_clk = exynos_dwmci_get_clk;
+       /* Add the mmc channel to be registered with mmc core */
+       if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+               printf("dwmmc%d registration failed\n", index);

Quoted 6 lines

Quoted 1 line

Should this be debug()?

I think it should be printf(), because if the mmc channel registration fails, then this failure information needs to be conveyed to the user. This will happen if printf() is used.
If debug() is used, then the statement will be printed only when the

DEBUG

Quoted 1 line

is defined.

It's a tricky point, and it depends on what else you have in terns of error reporting. This is not a user-facing function, but something called by the internals of your code. I think as a general principle errors should be reported by the commands that started the operation.

In this case exynos_dwmci_add_port() already has an error return code, and its caller can presumable report the error, although it would not include the 'dwmmc' text.

The problem with putting printf()s in drivers is that it can make it impossible to silently do something. For example if I want to write a command to check for a valid partition on an MMC device, and all of the MMC, partition and filesystem code prints out errors along the way, it can make for very confusing output, and can make it impossible to write a higher-level function which silently checks for the valid partition.

So in general I think we should try to keep printf() out of drivers. We have talked on the list about some sort of dynamic verbosity, and someone may look at that at some point, but at the moment we just have printf() and debug().

Regards,
Simon

This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk().

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Updated the function exynos5_mmc_set_clk_div() to receive 'device_i'd as input parameter instead of 'index'.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Removed the new API exynos5_mmc_set_clk_div() from clock.c, because existing API set_mmc_clk() can be used to set mmc clock.

Changes since V4:
1)Updated the subject line to reflect the changes present in this patch. 2)Changes of the file arch/arm/include/asm/arch-exynos/clk.h which were present in this patch, have been moved out of this patch.

 arch/arm/cpu/armv7/exynos/clock.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +2 -3

index 956427c..edce21c 100644
@@ -490,7 +490,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
                (struct exynos4_clock *)samsung_get_base_clock();
        unsigned long uclk, sclk;
        unsigned int sel, ratio, pre_ratio;
-       int shift;
+       int shift = 0;
 
        sel = readl(&clk->src_fsys);
        sel = (sel >> (dev_index << 2)) & 0xf;

@@ -539,7 +539,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
                (struct exynos5_clock *)samsung_get_base_clock();
        unsigned long uclk, sclk;
        unsigned int sel, ratio, pre_ratio;
-       int shift;
+       int shift = 0;
 
        sel = readl(&clk->src_fsys);
        sel = (sel >> (dev_index << 2)) & 0xf;
--

1.8.0

This patch enables and initialises DWMMC for SMDK5250.
Supports both FDT and non-FDT. This patch creates a new file 'exynos5-dt.c' meant for FDT support.
exynos5-dt.c: This file shall contain all code which supports FDT.
Any addition of FDT support for any module needs to be added in this file.
smdk5250.c: This file shall contain the code which supports non-FDT.
version. Any addition of non-FDT support for any module needs to be added in this file.
May be, the file smdk5250.c can be removed in near future when non-FDT is not required.

The Makefile is updated to compile only one of the files exynos5-dt.c / smdk5250.c based on FDT configuration.

NOTE:
Please note that all additions corresponding to FDT need to be added into the file exynos5-dt.c.
At same time if non-FDT support is required then add the corresponding updations into smdk5250.c.

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)A new file 'exynos5-dt.c' is created meant for FDT support 2)Makefile is updated to compile only one of the files exynos5-dt.c / smdk5250.c based on FDT configuration

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
No change.

Changes since V4:
1)Replaced the function call 'exynos_dwmmc_init(0, 8);' with the function exynos_dwmmc_add_port() in smdk5250.c. 2)dram_init() is updated to use for loop to compute the ram size. 3)dram_init_banksize() is updated to use for loop to initialise the dram bank size.
4)board_uart_init() is updated to use for loop to initialise UARTS. 5)In non-FDT case NULL is passed as parameter to board_i2c_init().

 board/samsung/smdk5250/Makefile     |   4 +
 board/samsung/smdk5250/exynos5-dt.c | 211 ++++++++++++++++++++++++++++++++++++
 board/samsung/smdk5250/smdk5250.c   | 170 ++++++++++-------------------
 include/configs/exynos5250-dt.h     |   6 +
 4 files changed, 279 insertions(+), 112 deletions(-)
 create mode 100644 board/samsung/smdk5250/exynos5-dt.c

board/samsung/smdk5250/Makefile +4 -0

index 47c6a5a..ecca9f3 100644
@@ -32,8 +32,12 @@ COBJS        += tzpc_init.o
 COBJS  += smdk5250_spl.o
 
 ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_OF_CONTROL
+COBJS  += exynos5-dt.o
+else
 COBJS  += smdk5250.o
 endif
+endif
 
 ifdef CONFIG_SPL_BUILD
 COBJS  += spl_boot.o

board/samsung/smdk5250/exynos5-dt.c new file +211 -0

new file mode 100644
index 0000000..a4b0e10
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <spi.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sromc.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+       gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#ifdef CONFIG_EXYNOS_SPI
+       spi_init();
+#endif
+       return 0;
+}
+
+int dram_init(void)
+{
+       int i;
+       u32 addr;
+
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+               gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+       }
+       return 0;
+}
+
+#if defined(CONFIG_POWER)
+int power_init_board(void)
+{
+       if (pmic_init(I2C_PMIC)) {
+               debug("Could not initialise PMIC\n");
+               return -1;
+       } else
+               return 0;
+}
+#endif
+
+void dram_init_banksize(void)
+{
+       int i;
+       u32 addr, size;
+
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+               size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+               gd->bd->bi_dram[i].start = addr;
+               gd->bd->bi_dram[i].size = size;
+       }
+}
+
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+       int err;
+       int node;
+
+       node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+       if (node < 0) {
+               debug("Could not find SROMC node\n");
+               return node;
+       }
+
+       config->bank = fdtdec_get_int(blob, node, "bank", 0);
+       config->width = fdtdec_get_int(blob, node, "width", 2);
+
+       err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+                       FDT_SROM_TIMING_COUNT);
+       if (err < 0) {
+               debug("Could not decode SROMC configuration"
+                                       "Error: %s\n", fdt_strerror(err));
+               return -FDT_ERR_NOTFOUND;
+       }
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+       u32 smc_bw_conf, smc_bc_conf;
+       struct fdt_sromc config;
+       fdt_addr_t base_addr;
+       int node;
+
+       node = decode_sromc(gd->fdt_blob, &config);
+       if (node < 0) {
+               debug("%s: Could not find sromc configuration\n", __func__);
+               return 0;
+       }
+       node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+       if (node < 0) {
+               debug("%s: Could not find lan9215 configuration\n", __func__);
+               return 0;
+       }
+
+       /* We now have a node, so any problems from now on are errors */
+       base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+       if (base_addr == FDT_ADDR_T_NONE) {
+               debug("%s: Could not find lan9215 address\n", __func__);
+               return -1;
+       }
+
+       /* Ethernet needs data bus width of 16 bits */
+       if (config.width != 2) {
+               debug("%s: Unsupported bus width %d\n", __func__,
+                       config.width);
+               return -1;
+       }
+       smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+                       | SROMC_BYTE_ENABLE(config.bank);
+
+       smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |
+                       SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
+                       SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
+                       SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
+                       SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |
+                       SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
+                       SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+       /* Select and configure the SROMC bank */
+       exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+       s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+       return smc911x_initialize(0, base_addr);
+#endif
+       return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+       printf("\nBoard: SMDK5250\n");
+
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+       int ret;
+       /* dwmmc initializattion for available channels */
+       ret = exynos_dwmmc_init(gd->fdt_blob);
+       if (ret)
+               debug("dwmmc init failed\n");
+
+       return ret;
+}
+#endif
+
+static int board_uart_init(void)
+{
+       int err, uart_id, ret = 0;
+
+       for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+               err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+               if (err) {
+                       debug("UART%d not configured\n",
+                                        (uart_id - PERIPH_ID_UART0));
+                       ret |= err;
+               }
+       }
+       return ret;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+       int err;
+       err = board_uart_init();
+       if (err) {
+               debug("UART init failed\n");
+               return err;
+       }
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+       board_i2c_init(gd->fdt_blob);
+#endif
+       return err;
+}
+#endif

board/samsung/smdk5250/smdk5250.c +58 -112

index 7a5f132..e3a2593 100644
@@ -28,6 +28,7 @@
 #include <netdev.h>
 #include <spi.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>

@@ -68,80 +69,40 @@ int board_init(void)
 
 int dram_init(void)
 {
-       gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
-                       + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
+       int i;
+       u32 addr;
+
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+               gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+       }
        return 0;
 }
 
 #if defined(CONFIG_POWER)
 int power_init_board(void)
 {
-       if (pmic_init(I2C_PMIC))
+       if (pmic_init(I2C_PMIC)) {
+               debug("Could not initialise PMIC\n");
                return -1;
-       else
+       } else
                return 0;
 }
 #endif
 
 void dram_init_banksize(void)
 {
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
-                                                       PHYS_SDRAM_1_SIZE);
-       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-       gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
-                                                       PHYS_SDRAM_2_SIZE);
-       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-       gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
-                                                       PHYS_SDRAM_3_SIZE);
-       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-       gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
-                                                       PHYS_SDRAM_4_SIZE);
-       gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
-       gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
-                                                       PHYS_SDRAM_5_SIZE);
-       gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
-       gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
-                                                       PHYS_SDRAM_6_SIZE);
-       gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
-       gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
-                                                       PHYS_SDRAM_7_SIZE);
-       gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
-       gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
-                                                       PHYS_SDRAM_8_SIZE);
-}
+       int i;
+       u32 addr, size;
 
-#ifdef CONFIG_OF_CONTROL
-static int decode_sromc(const void *blob, struct fdt_sromc *config)
-{
-       int err;
-       int node;
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+               size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 
-       node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
-       if (node < 0) {
-               debug("Could not find SROMC node\n");
-               return node;
+               gd->bd->bi_dram[i].start = addr;
+               gd->bd->bi_dram[i].size = size;
        }
-
-       config->bank = fdtdec_get_int(blob, node, "bank", 0);
-       config->width = fdtdec_get_int(blob, node, "width", 2);
-
-       err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
-                       FDT_SROM_TIMING_COUNT);
-       if (err < 0) {
-               debug("Could not decode SROMC configuration\n");
-               return -FDT_ERR_NOTFOUND;
-       }
-
-       return 0;
 }
-#endif
 
 int board_eth_init(bd_t *bis)
 {

@@ -149,27 +110,7 @@ int board_eth_init(bd_t *bis)
        u32 smc_bw_conf, smc_bc_conf;
        struct fdt_sromc config;
        fdt_addr_t base_addr;
-       int node;
 
-#ifdef CONFIG_OF_CONTROL
-       node = decode_sromc(gd->fdt_blob, &config);
-       if (node < 0) {
-               debug("%s: Could not find sromc configuration\n", __func__);
-               return 0;
-       }
-       node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
-       if (node < 0) {
-               debug("%s: Could not find lan9215 configuration\n", __func__);
-               return 0;
-       }
-
-       /* We now have a node, so any problems from now on are errors */
-       base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
-       if (base_addr == FDT_ADDR_T_NONE) {
-               debug("%s: Could not find lan9215 address\n", __func__);
-               return -1;
-       }
-#else
        /* Non-FDT configuration - bank number and timing parameters*/
        config.bank = CONFIG_ENV_SROM_BANK;
        config.width = 2;

@@ -182,7 +123,6 @@ int board_eth_init(bd_t *bis)
        config.timing[FDT_SROM_TACP] = 0x09;
        config.timing[FDT_SROM_PMC] = 0x01;
        base_addr = CONFIG_SMC911X_BASE;
-#endif
 
        /* Ethernet needs data bus width of 16 bits */
        if (config.width != 2) {

@@ -221,48 +161,54 @@ int checkboard(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-       int err;
+       int err, ret = 0, index, bus_width;
+       u32 base;
 
        err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
-       if (err) {
+       if (err)
                debug("SDMMC0 not configured\n");
-               return err;
-       }
-
-       err = s5p_mmc_init(0, 8);
-       return err;
+       ret |= err;
+
+       /*EMMC: dwmmc Channel-0 with 8 bit bus width */
+       index = 0;
+       base =  samsung_get_base_mmc() + (0x10000 * index);
+       bus_width = 8;
+       err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
+       if (err)
+               debug("dwmmc Channel-0 init failed\n");
+       ret |= err;
+
+       err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+       if (err)
+               debug("SDMMC2 not configured\n");
+       ret |= err;
+
+       /*SD: dwmmc Channel-2 with 4 bit bus width */
+       index = 2;
+       base = samsung_get_base_mmc() + (0x10000 * index);
+       bus_width = 4;
+       err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
+       if (err)
+               debug("dwmmc Channel-2 init failed\n");
+       ret |= err;
+
+       return ret;
 }
 #endif
 
 static int board_uart_init(void)
 {
-       int err;
-
-       err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
-       if (err) {
-               debug("UART0 not configured\n");
-               return err;
-       }
-
-       err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
-       if (err) {
-               debug("UART1 not configured\n");
-               return err;
+       int err, uart_id, ret = 0;
+
+       for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+               err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+               if (err) {
+                       debug("UART%d not configured\n",
+                                        (uart_id - PERIPH_ID_UART0));
+                       ret |= err;
+               }
        }
-
-       err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
-       if (err) {
-               debug("UART2 not configured\n");
-               return err;
-       }
-
-       err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
-       if (err) {
-               debug("UART3 not configured\n");
-               return err;
-       }
-
-       return 0;
+       return ret;
 }
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F

@@ -275,7 +221,7 @@ int board_early_init_f(void)
                return err;
        }
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
-       board_i2c_init(gd->fdt_blob);
+       board_i2c_init(NULL);
 #endif
        return err;
 }

include/configs/exynos5250-dt.h +6 -1

index cabd2f2..3fa86b2 100644
@@ -95,6 +95,8 @@
 #define CONFIG_MMC
 #define CONFIG_SDHCI
 #define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
 
 #define CONFIG_BOARD_EARLY_INIT_F
 

@@ -210,6 +212,10 @@
 
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
 #define CONFIG_IRAM_STACK      0x02050000
 
 #define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_LOAD_ADDR - 0x1000000)
--

1.8.0

This patch adds APIs to access(open / close) and to resize boot partiton of EMMC.

Signed-off-by Amar <[email protected]>

---
Changes since V1:
New patch.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
No change.

Changes since V4:
1)Replaced the functions mmc_boot_open() & mmc_boot_close() with a single function mmc_boot_part_access().

 drivers/mmc/mmc.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/mmc.h     |  24 +++++++++++
 2 files changed, 141 insertions(+)

drivers/mmc/mmc.c +0 -0

index 72e8ce6..c152934 100644
@@ -1327,3 +1327,120 @@ int mmc_initialize(bd_t *bis)
 
        return 0;