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ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi

PATCH New Stephen Warren 1 participant 2 messages Jan 23, 2013

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Stephen Warren

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PATCH 1/1 ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi

From: Stephen Warren <[email protected]>

No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files.

Signed-off-by Stephen Warren <[email protected]>
---
 arch/arm/boot/dts/tegra30-beaver.dts  |    1 -
 arch/arm/boot/dts/tegra30-cardhu.dtsi |    2 --
 arch/arm/boot/dts/tegra30.dtsi        |    5 +++++
 3 files changed, 5 insertions(+), 3 deletions(-)
arch/arm/boot/dts/tegra30-beaver.dts +0 -1
index 0f296a4..8ff2ff2 100644
@@ -90,7 +90,6 @@
 
 	serial at 70006000 {
 		status = "okay";
-		clock-frequency = <408000000>;
 	};
 
 	i2c at 7000c000 {
arch/arm/boot/dts/tegra30-cardhu.dtsi +0 -2
index ff6b68f..1749927 100644
@@ -120,13 +120,11 @@
 
 	serial at 70006000 {
 		status = "okay";
-		clock-frequency = <408000000>;
 	};
 
 	serial at 70006200 {
 		compatible = "nvidia,tegra30-hsuart";
 		status = "okay";
-		clock-frequency = <408000000>;
 	};
 
 	i2c at 7000c000 {
arch/arm/boot/dts/tegra30.dtsi +5 -0
index ff4a0ca..313fa71 100644
@@ -234,6 +234,7 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <0 36 0x04>;
+		clock-frequency = <408000000>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car 6>;
 		status = "disabled";

@@ -243,6 +244,7 @@
 		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
+		clock-frequency = <408000000>;
 		interrupts = <0 37 0x04>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car 160>;

@@ -253,6 +255,7 @@
 		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
+		clock-frequency = <408000000>;
 		interrupts = <0 46 0x04>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car 55>;

@@ -263,6 +266,7 @@
 		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
+		clock-frequency = <408000000>;
 		interrupts = <0 90 0x04>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car 65>;

@@ -273,6 +277,7 @@
 		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
+		clock-frequency = <408000000>;
 		interrupts = <0 91 0x04>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car 66>;
Signature · 1 line
1.7.10.4
author Applied
#1 lore raw

PATCH 1/1 ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi

Quoted 5 lines · Stephen Warren

From: Stephen Warren <[email protected]>

No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files.

I have applied this to Tegra's for-3.9/dt branch.