Preparatory GIC patches for arm64 support
Subsystems (14)
cover Preparatory GIC patches for arm64 support
Hi,
These patches are primarily aimed at reducing the irq-gic.c dependency on arch/arm and allow it to be used with arch/arm64. The last patch removes the explicit gic_secondary_init() call from the ARM platform code.
We still have a non-generic asm/smp_plat.h include for cpu_logical_map() but I couldn't find a better place to move it (asm/cpu.h isn't generic either, though more widely used than smp_plat.h).
The patches are based on linux-next as they require Rob's GIC irqhip move.
Catalin
Catalin Marinas (4):
arm: Move the set_handle_irq and handle_arch_irq declarations to
asm/irq.h
arm: Move chained_irq_(enter|exit) to a generic file
irqchip: gic: Call handle_bad_irq() directly
irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
arch/arm/include/asm/irq.h | 5 ++++ arch/arm/include/asm/mach/irq.h | 36 ----------------------- arch/arm/mach-at91/gpio.c | 3 +- arch/arm/mach-exynos/common.c | 1 + arch/arm/mach-exynos/platsmp.c | 8 ----- arch/arm/mach-highbank/platsmp.c | 7 ----- arch/arm/mach-imx/platsmp.c | 12 -------- arch/arm/mach-msm/platsmp.c | 8 ----- arch/arm/mach-omap2/omap-smp.c | 7 ----- arch/arm/mach-shmobile/smp-emev2.c | 7 ----- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ----- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ----- arch/arm/mach-socfpga/platsmp.c | 12 -------- arch/arm/mach-spear13xx/platsmp.c | 8 ----- arch/arm/mach-tegra/platsmp.c | 8 ----- arch/arm/mach-ux500/platsmp.c | 8 ----- arch/arm/plat-samsung/irq-vic-timer.c | 3 +- arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +- arch/arm/plat-versatile/platsmp.c | 8 ----- drivers/irqchip/irq-gic.c | 32 ++++++++++++++------ drivers/irqchip/irq-vic.c | 2 +- include/linux/irqchip/arm-gic.h | 1 - include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++++++ 23 files changed, 85 insertions(+), 160 deletions(-) create mode 100644 include/linux/irqchip/chained_irq.h
PATCH 1/4 arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h
This patch prepares the removal of <asm/mach/irq.h> include in the GIC and VIC irqchip drivers.
Signed-off-by Catalin Marinas <[email protected]>
Cc Russell King <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
--- arch/arm/include/asm/irq.h | 5 +++++ arch/arm/include/asm/mach/irq.h | 5 ----- drivers/irqchip/irq-vic.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-)
arch/arm/include/asm/irq.h +5 -0
@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *);void handle_IRQ (unsigned int ,struct pt_regs *);void init_IRQ (void ); +#ifdef CONFIG_MULTI_IRQ_HANDLER +extern void (*handle_arch_irq)(struct pt_regs *); +extern void set_handle_irq (void (*handle_irq)(struct pt_regs *)); +#endif +#endif #endif
arch/arm/include/asm/mach/irq.h +0 -5
@@ -20,11 +20,6 @@ struct seq_file;extern void init_FIQ (int );extern int show_fiq_list (struct seq_file *,int ); -#ifdef CONFIG_MULTI_IRQ_HANDLER -extern void (*handle_arch_irq)(struct pt_regs *); -extern void set_handle_irq (void (*handle_irq)(struct pt_regs *)); -#endif -/* * This is for easy migration, but should be changed in the source */
drivers/irqchip/irq-vic.c +1 -1
@@ -33,7 +33,7 @@#include <linux/irqchip/arm-vic.h> #include <asm/exception.h> -#include <asm/mach/irq.h> +#include <asm/irq.h> #include "irqchip.h"
PATCH 2/4 arm: Move chained_irq_(enter|exit) to a generic file
In reply to Catalin MarinasThese functions have been introduced by commit 10a8c383 (irq: introduce entry and exit functions for chained handlers) in asm/mach/irq.h. This patch moves them to linux/irqchip/chained_irq.h so that generic irqchip drivers do not rely on architecture specific header files.
Signed-off-by Catalin Marinas <[email protected]>
Cc Russell King <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
--- arch/arm/include/asm/mach/irq.h | 31 -------------------- arch/arm/mach-at91/gpio.c | 3 +- arch/arm/mach-exynos/common.c | 1 + arch/arm/plat-samsung/irq-vic-timer.c | 3 +- arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +- drivers/irqchip/irq-gic.c | 2 +- include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++++++ 7 files changed, 57 insertions(+), 38 deletions(-) create mode 100644 include/linux/irqchip/chained_irq.h
arch/arm/include/asm/mach/irq.h +0 -31
@@ -30,35 +30,4 @@ do { \raw_spin_unlock (&desc->lock); \ } while(0) -#ifndef __ASSEMBLY__ -/* -* Entry/exit functions for chained handlers where the primary IRQ chip -* may implement either fasteoi or level-trigger flow control. -*/ -static inline void chained_irq_enter (struct irq_chip *chip, -struct irq_desc *desc) -{ -/* FastEOI controllers require no action on entry. */ -if (chip->irq_eoi) -return ; - -if (chip->irq_mask_ack) { - chip->irq_mask_ack (&desc->irq_data); - }else { - chip->irq_mask (&desc->irq_data); -if (chip->irq_ack) - chip->irq_ack (&desc->irq_data); - } -} - -static inline void chained_irq_exit (struct irq_chip *chip, -struct irq_desc *desc) -{ -if (chip->irq_eoi) - chip->irq_eoi (&desc->irq_data); -else - chip->irq_unmask (&desc->irq_data); -} -#endif -#endif
arch/arm/mach-at91/gpio.c +1 -2
@@ -23,8 +23,7 @@#include <linux/io.h> #include <linux/irqdomain.h> #include <linux/of_address.h> - -#include <asm/mach/irq.h> +#include <linux/irqchip/chained_irq.h> #include <mach/hardware.h> #include <mach/at91_pio.h>
arch/arm/mach-exynos/common.c +1 -0
@@ -25,6 +25,7 @@#include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/irqchip/arm-gic.h> +#include <linux/irqchip/chained_irq.h> #include <asm/proc-fns.h> #include <asm/exception.h>
arch/arm/plat-samsung/irq-vic-timer.c +1 -2
@@ -17,14 +17,13 @@#include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/irqchip/chained_irq.h> #include <mach/map.h> #include <plat/cpu.h> #include <plat/irq-vic-timer.h> #include <plat/regs-timer.h> -#include <asm/mach/irq.h> -static void s3c_irq_demux_vic_timer (unsigned int irq,struct irq_desc *desc) {struct irq_chip *chip =irq_get_chip (irq);
arch/arm/plat-samsung/s5p-irq-gpioint.c +1 -2
@@ -17,13 +17,12 @@#include <linux/io.h> #include <linux/gpio.h> #include <linux/slab.h> +#include <linux/irqchip/chained_irq.h> #include <mach/map.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> -#include <asm/mach/irq.h> -#define GPIO_BASE (chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))#define CON_OFFSET 0x700
drivers/irqchip/irq-gic.c +1 -1
@@ -38,12 +38,12 @@#include <linux/interrupt.h> #include <linux/percpu.h> #include <linux/slab.h> +#include <linux/irqchip/chained_irq.h> #include <linux/irqchip/arm-gic.h> #include <asm/irq.h> #include <asm/exception.h> #include <asm/smp_plat.h> -#include <asm/mach/irq.h> #include "irqchip.h"
include/linux/irqchip/chained_irq.h new file +52 -0
52 lines not on this page · raw message
PATCH 2/4 arm: Move chained_irq_(enter|exit) to a generic file
Quoted 10 lines · Catalin Marinas
These functions have been introduced by commit
10a8c383(irq: introduce entry and exit functions for chained handlers) inasm/mach/irq.h. This patch moves them tolinux/irqchip/chained_irq.hso that generic irqchip drivers do not rely on architecture specific header files.Signed-off-by Catalin Marinas <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Rob Herring <[email protected]>---
[..]
include/linux/irqchip/chained_irq.h line 4
Quoted 10 lines
include/linux/irqchip/chained_irq.h new file +4
-0@@ -0,0 +1,52 @@ +/* +* Chained IRQ handlers support. +* +* Copyright (C) 2011 ARM Ltd.
2013 now ;)
PATCH 2/4 arm: Move chained_irq_(enter|exit) to a generic file
Quoted 13 lines · Santosh Shilimkar
include/linux/irqchip/chained_irq.h line 4
Quoted 10 lines · Catalin Marinas
include/linux/irqchip/chained_irq.h new file +4
-0@@ -0,0 +1,52 @@ +/* +* Chained IRQ handlers support. +* +* Copyright (C) 2011 ARM Ltd. 2013 now ;)
I thought about this but decided to keep the year when the chained IRQ functions were contributed by Will (still ARM's copyright).
Signature · 1 line
Catalin
PATCH 2/4 arm: Move chained_irq_(enter|exit) to a generic file
Quoted 15 lines · Catalin Marinas
Quoted 13 lines · Santosh Shilimkar
include/linux/irqchip/chained_irq.h line 4
Quoted 10 lines · Catalin Marinas
include/linux/irqchip/chained_irq.h new file +4
-0@@ -0,0 +1,52 @@ +/* +* Chained IRQ handlers support. +* +* Copyright (C) 2011 ARM Ltd. 2013 now ;)
Quoted 3 lines
I thought about this but decided to keep the year when the chained IRQ functions were contributed by Will (still ARM's copyright).
Ahh. Its just move to the new file. As you prefer but 2011-13 will do as well :-)
PATCH 3/4 irqchip: gic: Call handle_bad_irq() directly
In reply to Catalin MarinasPreviously, the gic_handle_cascade_irq() function was calling the ARM-specific do_bad_IRQ() function which calls handle_bad_irq() after acquiring the desk->lock. Locking the cascaded IRQ desc is not needed for error reporting, so just call handle_bad_irq() directly.
Signed-off-by Catalin Marinas <[email protected]>
Cc Russell King <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
--- drivers/irqchip/irq-gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/irqchip/irq-gic.c +1 -1
@@ -323,7 +323,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) cascade_irq =irq_find_mapping (chip_data->domain, gic_irq);if (unlikely (gic_irq <32 || gic_irq >1020 )) -do_bad_IRQ (cascade_irq, desc); +handle_bad_irq (cascade_irq, desc);else generic_handle_irq (cascade_irq);
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Catalin MarinasAll the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.
Signed-off-by Catalin Marinas <[email protected]>
Cc Russell King <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Kukjin Kim <[email protected]>
Cc Rob Herring <[email protected]>
Cc Sascha Hauer <[email protected]>
Cc David Brown <[email protected]>
Cc Daniel Walker <[email protected]>
Cc Bryan Huntsman <[email protected]>
Cc Tony Lindgren <[email protected]>
Cc Simon Horman <[email protected]>
Cc Magnus Damm <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Viresh Kumar <[email protected]>
Cc Shiraz Hashim <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Srinidhi Kasagar <[email protected]>
Cc Linus Walleij <[email protected]>
---
Randomly chosen CPU notifier priority. I can add a definition somewhere though they don't seem to be used much and cause conflicts.
arch/arm/mach-exynos/platsmp.c | 8 -------- arch/arm/mach-highbank/platsmp.c | 7 ------- arch/arm/mach-imx/platsmp.c | 12 ------------ arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-omap2/omap-smp.c | 7 ------- arch/arm/mach-shmobile/smp-emev2.c | 7 ------- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- arch/arm/mach-socfpga/platsmp.c | 12 ------------ arch/arm/mach-spear13xx/platsmp.c | 8 -------- arch/arm/mach-tegra/platsmp.c | 8 -------- arch/arm/mach-ux500/platsmp.c | 8 -------- arch/arm/plat-versatile/platsmp.c | 8 -------- drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++------- include/linux/irqchip/arm-gic.h | 1 - 15 files changed, 21 insertions(+), 115 deletions(-)
arch/arm/mach-exynos/platsmp.c +0 -8
@@ -20,7 +20,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h>
@@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit exynos_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
arch/arm/mach-highbank/platsmp.c +0 -7
@@ -17,7 +17,6 @@#include <linux/init.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/smp_scu.h>
@@ -25,11 +24,6 @@extern void secondary_startup (void ); -static void __cpuinit highbank_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit highbank_boot_secondary (unsigned int cpu,struct task_struct *idle) {highbank_set_cpu_jump (cpu, secondary_startup);
@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations highbank_smp_ops__initdata = { .smp_init_cpus = highbank_smp_init_cpus, .smp_prepare_cpus = highbank_smp_prepare_cpus, - .smp_secondary_init = highbank_secondary_init, .smp_boot_secondary = highbank_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = highbank_cpu_die,
arch/arm/mach-imx/platsmp.c +0 -12
@@ -12,7 +12,6 @@#include <linux/init.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/page.h> #include <asm/smp_scu.h> #include <asm/mach/map.h>
@@ -42,16 +41,6 @@ void __init imx_scu_map_io(void) scu_base =IMX_IO_ADDRESS (base); } -static void __cpuinit imx_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit imx_boot_secondary (unsigned int cpu,struct task_struct *idle) {imx_set_cpu_jump (cpu, v7_secondary_startup);
@@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations imx_smp_ops__initdata = { .smp_init_cpus = imx_smp_init_cpus, .smp_prepare_cpus = imx_smp_prepare_cpus, - .smp_secondary_init = imx_secondary_init, .smp_boot_secondary = imx_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = imx_cpu_die,
arch/arm/mach-msm/platsmp.c +0 -8
@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/cputype.h>
@@ -42,13 +41,6 @@ static inline int get_core_count(void)static void __cpuinit msm_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
arch/arm/mach-omap2/omap-smp.c +0 -7
@@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) 4, 0, 0, 0, 0, 0);/* -* If any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * Synchronise with the boot thread. */ spin_lock (&boot_lock);
arch/arm/mach-shmobile/smp-emev2.c +0 -7
@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/emev2.h> #include <asm/smp_plat.h>
@@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu) } -static void __cpuinit emev2_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit emev2_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);
@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)struct smp_operations emev2_smp_ops__initdata = { .smp_init_cpus = emev2_smp_init_cpus, .smp_prepare_cpus = emev2_smp_prepare_cpus, - .smp_secondary_init = emev2_secondary_init, .smp_boot_secondary = emev2_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = emev2_cpu_kill,
arch/arm/mach-shmobile/smp-r8a7779.c +0 -7
@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/r8a7779.h> #include <asm/smp_plat.h>
@@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) } -static void __cpuinit r8a7779_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit r8a7779_boot_secondary (unsigned int cpu,struct task_struct *idle) {struct r8a7779_pm_ch *ch =NULL ;
@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)struct smp_operations r8a7779_smp_ops__initdata = { .smp_init_cpus = r8a7779_smp_init_cpus, .smp_prepare_cpus = r8a7779_smp_prepare_cpus, - .smp_secondary_init = r8a7779_secondary_init, .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = r8a7779_cpu_kill,
arch/arm/mach-shmobile/smp-sh73a0.c +0 -7
@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h>
@@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)return scu_get_core_count (scu_base); } -static void __cpuinit sh73a0_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit sh73a0_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);
@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)struct smp_operations sh73a0_smp_ops__initdata = { .smp_init_cpus = sh73a0_smp_init_cpus, .smp_prepare_cpus = sh73a0_smp_prepare_cpus, - .smp_secondary_init = sh73a0_secondary_init, .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill,
arch/arm/mach-socfpga/platsmp.c +0 -12
@@ -22,7 +22,6 @@#include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h>
@@ -33,16 +32,6 @@extern void __iomem *sys_manager_base_addr;extern void __iomem *rst_manager_base_addr; -static void __cpuinit socfpga_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit socfpga_boot_secondary (unsigned int cpu,struct task_struct *idle) {int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
@@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)struct smp_operations socfpga_smp_ops__initdata = { .smp_init_cpus = socfpga_smp_init_cpus, .smp_prepare_cpus = socfpga_smp_prepare_cpus, - .smp_secondary_init = socfpga_secondary_init, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die,
arch/arm/mach-spear13xx/platsmp.c +0 -8
@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/io.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> #include <mach/spear.h>
@@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);static void __cpuinit spear13xx_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
arch/arm/mach-tegra/platsmp.c +0 -8
@@ -18,7 +18,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <linux/clk/tegra.h> #include <asm/cacheflush.h>
@@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);static void __cpuinit tegra_secondary_init (unsigned int cpu) { -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -cpumask_set_cpu (cpu, &tegra_cpu_init_mask); }
arch/arm/mach-ux500/platsmp.c +0 -8
@@ -16,7 +16,6 @@#include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h>
@@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit ux500_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
arch/arm/plat-versatile/platsmp.c +0 -8
@@ -14,7 +14,6 @@#include <linux/device.h> #include <linux/jiffies.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h>
@@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);void __cpuinit versatile_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
drivers/irqchip/irq-gic.c +21 -7
@@ -28,6 +28,7 @@#include <linux/module.h> #include <linux/list.h> #include <linux/smp.h> +#include <linux/cpu.h> #include <linux/cpu_pm.h> #include <linux/cpumask.h> #include <linux/io.h>
@@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,return 0 ; } +#ifdef CONFIG_SMP +static int __cpuinit gic_secondary_init (struct notifier_block *nfb, +unsigned long action,void *hcpu) +{ +if (action ==CPU_STARTING ) +gic_cpu_init (&gic_data[0 ]); +return NOTIFY_OK ; +} + +/* +* Notifier for enabling the GIC CPU interface. Set an arbitrarily high +* priority because the GIC needs to be up before the ARM generic timers. +*/ +static struct notifier_block __cpuinitdata gic_cpu_notifier = { + .notifier_call = gic_secondary_init, + .priority =100 , +}; +#endif +const struct irq_domain_ops gic_irq_domain_ops = { .map = gic_irq_domain_map, .xlate = gic_irq_domain_xlate,
@@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,#ifdef CONFIG_SMP set_smp_cross_call (gic_raise_softirq); +register_cpu_notifier (&gic_cpu_notifier);#endif set_handle_irq (gic_handle_irq);
@@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,gic_pm_init (gic); } -void __cpuinit gic_secondary_init (unsigned int gic_nr) -{ -BUG_ON (gic_nr >=MAX_GIC_NR ); - -gic_cpu_init (&gic_data[gic_nr]); -} -#ifdef CONFIG_OF static int gic_cnt__initdata =0 ;
include/linux/irqchip/arm-gic.h +0 -1
@@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;void gic_init_bases (unsigned int ,int ,void __iomem *,void __iomem *,u32 offset,struct device_node *); -void gic_secondary_init (unsigned int );void gic_cascade_irq (unsigned int gic_nr,unsigned int irq); static inline void gic_init(unsigned int nr, int start,
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 4 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.
Tegra part,
Acked-by Stephen Warren <[email protected]>
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Catalin MarinasQuoted 6 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.arch/arm/mach-spear13xx/platsmp.c | 8 --------
For SPEAr,
Acked-by Viresh Kumar <[email protected]>
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Catalin MarinasQuoted 6 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>
[..]
Quoted 2 lines
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Nice to see GIC is converted as well like timers. The trick as you mentioned about higher priority of GIC than timer is key for correct initialization of secondary CPUs.
For OMAP changes and the series,
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Catalin MarinasQuoted 23 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Cc Rob Herring <[email protected]>Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Daniel Walker <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Viresh Kumar <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Stephen Warren <[email protected]>Cc Srinidhi Kasagar <[email protected]>Cc Linus Walleij <[email protected]>
Quoted 1 line
---
Acked-by Rob Herring <[email protected]>
Quoted 470 lines
Randomly chosen CPU notifier priority. I can add a definition somewhere though they don't seem to be used much and cause conflicts.
arch/arm/mach-exynos/platsmp.c | 8 -------- arch/arm/mach-highbank/platsmp.c | 7 ------- arch/arm/mach-imx/platsmp.c | 12 ------------ arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-omap2/omap-smp.c | 7 ------- arch/arm/mach-shmobile/smp-emev2.c | 7 ------- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- arch/arm/mach-socfpga/platsmp.c | 12 ------------ arch/arm/mach-spear13xx/platsmp.c | 8 -------- arch/arm/mach-tegra/platsmp.c | 8 -------- arch/arm/mach-ux500/platsmp.c | 8 -------- arch/arm/plat-versatile/platsmp.c | 8 -------- drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++------- include/linux/irqchip/arm-gic.h | 1 - 15 files changed, 21 insertions(+), 115 deletions(-)arch/arm/mach-exynos/platsmp.c +0
-8@@ -20,7 +20,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit exynos_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/mach-highbank/platsmp.c +0
-7@@ -17,7 +17,6 @@#include <linux/init.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/smp_scu.h> @@ -25,11 +24,6 @@extern void secondary_startup (void ); -static void __cpuinit highbank_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit highbank_boot_secondary (unsigned int cpu,struct task_struct *idle) {highbank_set_cpu_jump (cpu, secondary_startup);@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations highbank_smp_ops__initdata = { .smp_init_cpus = highbank_smp_init_cpus, .smp_prepare_cpus = highbank_smp_prepare_cpus, - .smp_secondary_init = highbank_secondary_init, .smp_boot_secondary = highbank_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = highbank_cpu_die,arch/arm/mach-imx/platsmp.c +0
-12@@ -12,7 +12,6 @@#include <linux/init.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/page.h> #include <asm/smp_scu.h> #include <asm/mach/map.h> @@ -42,16 +41,6 @@ void __init imx_scu_map_io(void) scu_base =IMX_IO_ADDRESS (base); } -static void __cpuinit imx_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit imx_boot_secondary (unsigned int cpu,struct task_struct *idle) {imx_set_cpu_jump (cpu, v7_secondary_startup);@@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations imx_smp_ops__initdata = { .smp_init_cpus = imx_smp_init_cpus, .smp_prepare_cpus = imx_smp_prepare_cpus, - .smp_secondary_init = imx_secondary_init, .smp_boot_secondary = imx_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = imx_cpu_die,arch/arm/mach-msm/platsmp.c +0
-8@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> @@ -42,13 +41,6 @@ static inline int get_core_count(void)static void __cpuinit msm_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/mach-omap2/omap-smp.c +0
-7@@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) 4, 0, 0, 0, 0, 0);/* -* If any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * Synchronise with the boot thread. */ spin_lock (&boot_lock);arch/arm/mach-shmobile/smp-emev2.c +0
-7@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/emev2.h> #include <asm/smp_plat.h> @@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu) } -static void __cpuinit emev2_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit emev2_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)struct smp_operations emev2_smp_ops__initdata = { .smp_init_cpus = emev2_smp_init_cpus, .smp_prepare_cpus = emev2_smp_prepare_cpus, - .smp_secondary_init = emev2_secondary_init, .smp_boot_secondary = emev2_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = emev2_cpu_kill,arch/arm/mach-shmobile/smp-r8a7779.c +0
-7@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/r8a7779.h> #include <asm/smp_plat.h> @@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) } -static void __cpuinit r8a7779_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit r8a7779_boot_secondary (unsigned int cpu,struct task_struct *idle) {struct r8a7779_pm_ch *ch =NULL ;@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)struct smp_operations r8a7779_smp_ops__initdata = { .smp_init_cpus = r8a7779_smp_init_cpus, .smp_prepare_cpus = r8a7779_smp_prepare_cpus, - .smp_secondary_init = r8a7779_secondary_init, .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = r8a7779_cpu_kill,arch/arm/mach-shmobile/smp-sh73a0.c +0
-7@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)return scu_get_core_count (scu_base); } -static void __cpuinit sh73a0_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit sh73a0_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)struct smp_operations sh73a0_smp_ops__initdata = { .smp_init_cpus = sh73a0_smp_init_cpus, .smp_prepare_cpus = sh73a0_smp_prepare_cpus, - .smp_secondary_init = sh73a0_secondary_init, .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill,arch/arm/mach-socfpga/platsmp.c +0
-12@@ -22,7 +22,6 @@#include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> @@ -33,16 +32,6 @@extern void __iomem *sys_manager_base_addr;extern void __iomem *rst_manager_base_addr; -static void __cpuinit socfpga_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit socfpga_boot_secondary (unsigned int cpu,struct task_struct *idle) {int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;@@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)struct smp_operations socfpga_smp_ops__initdata = { .smp_init_cpus = socfpga_smp_init_cpus, .smp_prepare_cpus = socfpga_smp_prepare_cpus, - .smp_secondary_init = socfpga_secondary_init, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die,arch/arm/mach-spear13xx/platsmp.c +0
-8@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/io.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> #include <mach/spear.h> @@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);static void __cpuinit spear13xx_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/mach-tegra/platsmp.c +0
-8@@ -18,7 +18,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <linux/clk/tegra.h> #include <asm/cacheflush.h> @@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);static void __cpuinit tegra_secondary_init (unsigned int cpu) { -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -cpumask_set_cpu (cpu, &tegra_cpu_init_mask); }arch/arm/mach-ux500/platsmp.c +0
-8@@ -16,7 +16,6 @@#include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit ux500_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/plat-versatile/platsmp.c +0
-8@@ -14,7 +14,6 @@#include <linux/device.h> #include <linux/jiffies.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);void __cpuinit versatile_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ drivers/irqchip/irq-gic.c +21
-7@@ -28,6 +28,7 @@#include <linux/module.h> #include <linux/list.h> #include <linux/smp.h> +#include <linux/cpu.h> #include <linux/cpu_pm.h> #include <linux/cpumask.h> #include <linux/io.h> @@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,return 0 ; } +#ifdef CONFIG_SMP +static int __cpuinit gic_secondary_init (struct notifier_block *nfb, +unsigned long action,void *hcpu) +{ +if (action ==CPU_STARTING ) +gic_cpu_init (&gic_data[0 ]); +return NOTIFY_OK ; +} + +/* +* Notifier for enabling the GIC CPU interface. Set an arbitrarily high +* priority because the GIC needs to be up before the ARM generic timers. +*/ +static struct notifier_block __cpuinitdata gic_cpu_notifier = { + .notifier_call = gic_secondary_init, + .priority =100 , +}; +#endif +const struct irq_domain_ops gic_irq_domain_ops = { .map = gic_irq_domain_map, .xlate = gic_irq_domain_xlate,@@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,#ifdef CONFIG_SMP set_smp_cross_call (gic_raise_softirq); +register_cpu_notifier (&gic_cpu_notifier);#endif set_handle_irq (gic_handle_irq);@@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,gic_pm_init (gic); } -void __cpuinit gic_secondary_init (unsigned int gic_nr) -{ -BUG_ON (gic_nr >=MAX_GIC_NR ); - -gic_cpu_init (&gic_data[gic_nr]); -} -#ifdef CONFIG_OF static int gic_cnt__initdata =0 ;include/linux/irqchip/arm-gic.h +0
-1@@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;void gic_init_bases (unsigned int ,int ,void __iomem *,void __iomem *,u32 offset,struct device_node *); -void gic_secondary_init (unsigned int );void gic_cascade_irq (unsigned int gic_nr,unsigned int irq); static inline void gic_init(unsigned int nr, int start,
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Catalin MarinasQuoted 15 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Cc Rob Herring <[email protected]>Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Daniel Walker <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>
Quoted 8 lines
Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Viresh Kumar <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Stephen Warren <[email protected]>Cc Srinidhi Kasagar <[email protected]>Cc Linus Walleij <[email protected]>
mach-shmobile portion:
Acked-by Simon Horman <[email protected]>
For the record, I tested this on the kzm9g, kzm9d and marzen boards which use the r8a7779, EMEV2 and r8a7779 SoCs respectively.
Quoted 476 lines
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Randomly chosen CPU notifier priority. I can add a definition somewhere though they don't seem to be used much and cause conflicts.
arch/arm/mach-exynos/platsmp.c | 8 -------- arch/arm/mach-highbank/platsmp.c | 7 ------- arch/arm/mach-imx/platsmp.c | 12 ------------ arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-omap2/omap-smp.c | 7 ------- arch/arm/mach-shmobile/smp-emev2.c | 7 ------- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- arch/arm/mach-socfpga/platsmp.c | 12 ------------ arch/arm/mach-spear13xx/platsmp.c | 8 -------- arch/arm/mach-tegra/platsmp.c | 8 -------- arch/arm/mach-ux500/platsmp.c | 8 -------- arch/arm/plat-versatile/platsmp.c | 8 -------- drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++------- include/linux/irqchip/arm-gic.h | 1 - 15 files changed, 21 insertions(+), 115 deletions(-)arch/arm/mach-exynos/platsmp.c +0
-8@@ -20,7 +20,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit exynos_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/mach-highbank/platsmp.c +0
-7@@ -17,7 +17,6 @@#include <linux/init.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/smp_scu.h> @@ -25,11 +24,6 @@extern void secondary_startup (void ); -static void __cpuinit highbank_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit highbank_boot_secondary (unsigned int cpu,struct task_struct *idle) {highbank_set_cpu_jump (cpu, secondary_startup);@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations highbank_smp_ops__initdata = { .smp_init_cpus = highbank_smp_init_cpus, .smp_prepare_cpus = highbank_smp_prepare_cpus, - .smp_secondary_init = highbank_secondary_init, .smp_boot_secondary = highbank_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = highbank_cpu_die,arch/arm/mach-imx/platsmp.c +0
-12@@ -12,7 +12,6 @@#include <linux/init.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/page.h> #include <asm/smp_scu.h> #include <asm/mach/map.h> @@ -42,16 +41,6 @@ void __init imx_scu_map_io(void) scu_base =IMX_IO_ADDRESS (base); } -static void __cpuinit imx_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit imx_boot_secondary (unsigned int cpu,struct task_struct *idle) {imx_set_cpu_jump (cpu, v7_secondary_startup);@@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations imx_smp_ops__initdata = { .smp_init_cpus = imx_smp_init_cpus, .smp_prepare_cpus = imx_smp_prepare_cpus, - .smp_secondary_init = imx_secondary_init, .smp_boot_secondary = imx_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = imx_cpu_die,arch/arm/mach-msm/platsmp.c +0
-8@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> @@ -42,13 +41,6 @@ static inline int get_core_count(void)static void __cpuinit msm_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/mach-omap2/omap-smp.c +0
-7@@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) 4, 0, 0, 0, 0, 0);/* -* If any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * Synchronise with the boot thread. */ spin_lock (&boot_lock);arch/arm/mach-shmobile/smp-emev2.c +0
-7@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/emev2.h> #include <asm/smp_plat.h> @@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu) } -static void __cpuinit emev2_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit emev2_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)struct smp_operations emev2_smp_ops__initdata = { .smp_init_cpus = emev2_smp_init_cpus, .smp_prepare_cpus = emev2_smp_prepare_cpus, - .smp_secondary_init = emev2_secondary_init, .smp_boot_secondary = emev2_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = emev2_cpu_kill,arch/arm/mach-shmobile/smp-r8a7779.c +0
-7@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/r8a7779.h> #include <asm/smp_plat.h> @@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) } -static void __cpuinit r8a7779_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit r8a7779_boot_secondary (unsigned int cpu,struct task_struct *idle) {struct r8a7779_pm_ch *ch =NULL ;@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)struct smp_operations r8a7779_smp_ops__initdata = { .smp_init_cpus = r8a7779_smp_init_cpus, .smp_prepare_cpus = r8a7779_smp_prepare_cpus, - .smp_secondary_init = r8a7779_secondary_init, .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = r8a7779_cpu_kill,arch/arm/mach-shmobile/smp-sh73a0.c +0
-7@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)return scu_get_core_count (scu_base); } -static void __cpuinit sh73a0_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit sh73a0_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)struct smp_operations sh73a0_smp_ops__initdata = { .smp_init_cpus = sh73a0_smp_init_cpus, .smp_prepare_cpus = sh73a0_smp_prepare_cpus, - .smp_secondary_init = sh73a0_secondary_init, .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill,arch/arm/mach-socfpga/platsmp.c +0
-12@@ -22,7 +22,6 @@#include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> @@ -33,16 +32,6 @@extern void __iomem *sys_manager_base_addr;extern void __iomem *rst_manager_base_addr; -static void __cpuinit socfpga_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit socfpga_boot_secondary (unsigned int cpu,struct task_struct *idle) {int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;@@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)struct smp_operations socfpga_smp_ops__initdata = { .smp_init_cpus = socfpga_smp_init_cpus, .smp_prepare_cpus = socfpga_smp_prepare_cpus, - .smp_secondary_init = socfpga_secondary_init, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die,arch/arm/mach-spear13xx/platsmp.c +0
-8@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/io.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> #include <mach/spear.h> @@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);static void __cpuinit spear13xx_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/mach-tegra/platsmp.c +0
-8@@ -18,7 +18,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <linux/clk/tegra.h> #include <asm/cacheflush.h> @@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);static void __cpuinit tegra_secondary_init (unsigned int cpu) { -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -cpumask_set_cpu (cpu, &tegra_cpu_init_mask); }arch/arm/mach-ux500/platsmp.c +0
-8@@ -16,7 +16,6 @@#include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit ux500_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/plat-versatile/platsmp.c +0
-8@@ -14,7 +14,6 @@#include <linux/device.h> #include <linux/jiffies.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);void __cpuinit versatile_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ drivers/irqchip/irq-gic.c +21
-7@@ -28,6 +28,7 @@#include <linux/module.h> #include <linux/list.h> #include <linux/smp.h> +#include <linux/cpu.h> #include <linux/cpu_pm.h> #include <linux/cpumask.h> #include <linux/io.h> @@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,return 0 ; } +#ifdef CONFIG_SMP +static int __cpuinit gic_secondary_init (struct notifier_block *nfb, +unsigned long action,void *hcpu) +{ +if (action ==CPU_STARTING ) +gic_cpu_init (&gic_data[0 ]); +return NOTIFY_OK ; +} + +/* +* Notifier for enabling the GIC CPU interface. Set an arbitrarily high +* priority because the GIC needs to be up before the ARM generic timers. +*/ +static struct notifier_block __cpuinitdata gic_cpu_notifier = { + .notifier_call = gic_secondary_init, + .priority =100 , +}; +#endif +const struct irq_domain_ops gic_irq_domain_ops = { .map = gic_irq_domain_map, .xlate = gic_irq_domain_xlate,@@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,#ifdef CONFIG_SMP set_smp_cross_call (gic_raise_softirq); +register_cpu_notifier (&gic_cpu_notifier);#endif set_handle_irq (gic_handle_irq);@@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,gic_pm_init (gic); } -void __cpuinit gic_secondary_init (unsigned int gic_nr) -{ -BUG_ON (gic_nr >=MAX_GIC_NR ); - -gic_cpu_init (&gic_data[gic_nr]); -} -#ifdef CONFIG_OF static int gic_cnt__initdata =0 ;include/linux/irqchip/arm-gic.h +0
-1@@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;void gic_init_bases (unsigned int ,int ,void __iomem *,void __iomem *,u32 offset,struct device_node *); -void gic_secondary_init (unsigned int );void gic_cascade_irq (unsigned int gic_nr,unsigned int irq); static inline void gic_init(unsigned int nr, int start,_______________________________________________
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PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 25 lines · Simon Horman
Quoted 15 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Cc Rob Herring <[email protected]>Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Daniel Walker <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>Quoted 8 lines
Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Viresh Kumar <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Stephen Warren <[email protected]>Cc Srinidhi Kasagar <[email protected]>Cc Linus Walleij <[email protected]>
Quoted 6 lines
mach-shmobile portion:
Acked-by Simon Horman <[email protected]>For the record, I tested this on the kzm9g, kzm9d and marzen boards which use the r8a7779, EMEV2 and r8a7779 SoCs respectively.
Thanks. Can I add a Tested-by as well?
Signature · 1 line
Catalin
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 26 lines · Catalin Marinas
Quoted 25 lines · Simon Horman
Quoted 23 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Cc Rob Herring <[email protected]>Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Daniel Walker <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Viresh Kumar <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Stephen Warren <[email protected]>Cc Srinidhi Kasagar <[email protected]>Cc Linus Walleij <[email protected]>
Quoted 8 lines
Quoted 6 lines
mach-shmobile portion:
Acked-by Simon Horman <[email protected]>For the record, I tested this on the kzm9g, kzm9d and marzen boards which use the r8a7779, EMEV2 and r8a7779 SoCs respectively.
Thanks. Can I add a Tested-by as well?
Sure.
Tested-by Simon Horman <[email protected]>
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Catalin MarinasQuoted 15 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Cc Rob Herring <[email protected]>Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Daniel Walker <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>
Quoted 8 lines
Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Viresh Kumar <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Stephen Warren <[email protected]>Cc Srinidhi Kasagar <[email protected]>Cc Linus Walleij <[email protected]>
For ux500, it is
Acked-by srinidhi kasagar <[email protected]>
thanks,
srinidhi
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Catalin MarinasHi Catalin,
Quoted 28 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Cc Rob Herring <[email protected]>Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Daniel Walker <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Viresh Kumar <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Stephen Warren <[email protected]>Cc Srinidhi Kasagar <[email protected]>Cc Linus Walleij <[email protected]>---
Randomly chosen CPU notifier priority. I can add a definition somewhere though they don't seem to be used much and cause conflicts.
Quoted 9 lines
arch/arm/mach-exynos/platsmp.c | 8 -------- arch/arm/mach-highbank/platsmp.c | 7 ------- arch/arm/mach-imx/platsmp.c | 12 ------------ arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-omap2/omap-smp.c | 7 ------- arch/arm/mach-shmobile/smp-emev2.c | 7 ------- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- arch/arm/mach-socfpga/platsmp.c | 12 ------------
For socfpga, I get this error when I build for sofpga_defconfig:
drivers/gpio/gpio-pl061.c: In function ?pl061_irq_handler?:drivers/gpio/gpio-pl061.c:183:2: error: implicit declaration of function ?chained_irq_enter? [-Werror=implicit-function-declaration] drivers/gpio/gpio-pl061.c:192:2: error: implicit declaration of function ?chained_irq_exit? [-Werror=implicit-function-declaration]
Dinh
PATCH 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 41 lines · Dinh Nguyen
Hi Catalin,
Quoted 28 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Cc Rob Herring <[email protected]>Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Daniel Walker <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Viresh Kumar <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Stephen Warren <[email protected]>Cc Srinidhi Kasagar <[email protected]>Cc Linus Walleij <[email protected]>---
Randomly chosen CPU notifier priority. I can add a definition somewhere though they don't seem to be used much and cause conflicts.
Quoted 9 lines
arch/arm/mach-exynos/platsmp.c | 8 -------- arch/arm/mach-highbank/platsmp.c | 7 ------- arch/arm/mach-imx/platsmp.c | 12 ------------ arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-omap2/omap-smp.c | 7 ------- arch/arm/mach-shmobile/smp-emev2.c | 7 ------- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- arch/arm/mach-socfpga/platsmp.c | 12 ------------
Quoted 7 lines
For socfpga, I get this error when I build for
sofpga_defconfig:
drivers/gpio/gpio-pl061.c: In function ?pl061_irq_handler?:drivers/gpio/gpio-pl061.c:183:2: error: implicit declaration of function ?chained_irq_enter? [-Werror=implicit-function-declaration]drivers/gpio/gpio-pl061.c:192:2: error: implicit declaration of function ?chained_irq_exit? [-Werror=implicit-function-declaration]
Ah, I only grep'ed arch/arm for chained_irq_enter() use. The simplest for arch/arm is to actually include chained_irq.h into asm/mach/irq.h since the latter is already included. For code shared with arm64 I'll just include chained_irq.h explicitly.
Thanks.
Signature · 1 line
Catalin