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tegra: SPI drivers

PATCH Superseded Allen Martin 2 participants 10 messages Jan 29, 2013 – Jan 30, 2013

Subsystems (4)
Arm (32-bit) Library code SPI Tegra architecture support
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Allen Martin

author
#0 lore raw

v4 cover tegra: SPI drivers

This series updates the tegra20 SPI driver to add fdt support and adds a new tegra30 SPI driver.

Testing was done on trimslice (tegra20) and cardhu (tegra30).

Changes in v4:
-Added support for fdt aliases to slink driver
-Check "status" field of fdt node to make sure node is enabled Changes in v3:
-Dropped some fdt patches from the series that were picked up in
u-boot-tegra/next already
-Removed SPI node from seaboard, added to trimslice -Incorporated feedback from Simon Glass and Stephen Warren to slink
driver
Changes in v2:
-Added new patch to sort dts files prior to adding new nodes -Moved "max-spi-frequency" out to board dts files
-Moved tegra20 SFLASH fdt changes out to separate patch -Added valid flag to slink driver controller structure

Allen Martin (7):
tegra20: fdt: add SPI SFLASH node
tegra: spi: add fdt support to tegra SPI SFLASH driver
tegra30: add SBC1 to periph id mapping table
tegra30: fdt: add SPI SLINK nodes
tegra: add addresses of SPI SLINK controllers
tegra: add SPI SLINK driver
tegra: cardhu: config: enable SPI

 arch/arm/cpu/tegra30-common/clock.c           |    2 +-
 arch/arm/dts/tegra20.dtsi                     |   12 +
 arch/arm/dts/tegra30.dtsi                     |   72 ++++++
 arch/arm/include/asm/arch-tegra/tegra.h       |    6 +
 arch/arm/include/asm/arch-tegra/tegra_slink.h |   84 ++++++
 board/compulab/dts/tegra20-trimslice.dts      |    5 +
 board/nvidia/common/board.c                   |    3 +-
 board/nvidia/dts/tegra30-cardhu.dts           |    5 +
 drivers/spi/Makefile                          |    1 +
 drivers/spi/tegra_slink.c                     |  343 +++++++++++++++++++++++++
 drivers/spi/tegra_spi.c                       |   45 +++-
 include/configs/cardhu.h                      |   11 +
 include/fdtdec.h                              |    2 +
 lib/fdtdec.c                                  |    2 +
 14 files changed, 589 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h
 create mode 100644 drivers/spi/tegra_slink.c
Signature · 1 line
1.7.10.4
author
#1 lore raw

PATCH v4 1/7 tegra20: fdt: add SPI SFLASH node

Add node for tegra20 SPI SFLASH controller to fdt.

Signed-off-by Allen Martin <[email protected]>
---
 arch/arm/dts/tegra20.dtsi                |   12 ++++++++++++
 board/compulab/dts/tegra20-trimslice.dts |    5 +++++
 2 files changed, 17 insertions(+)
arch/arm/dts/tegra20.dtsi +12 -0
index 12049fd..9a89685 100644
@@ -236,6 +236,18 @@
 		clocks = <&tegra_car 12>, <&tegra_car 124>;
 	};
 
+	spi at 7000c380 {
+		compatible = "nvidia,tegra20-sflash";
+		reg = <0x7000c380 0x80>;
+		interrupts = <0 39 0x04>;
+		nvidia,dma-request-selector = <&apbdma 11>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SPI1, PLLP_OUT0 */
+		clocks = <&tegra_car 43>;
+	};
+
 	i2c at 7000c400 {
 		#address-cells = <1>;
 		#size-cells = <0>;
board/compulab/dts/tegra20-trimslice.dts +5 -0
index c8a4dd4..7aeed67 100644
@@ -23,6 +23,11 @@
 		status = "disabled";
 	};
 
+	spi at 7000c380 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
 	i2c at 7000c400 {
 		status = "disabled";
 	};
Signature · 1 line
1.7.10.4
author
#3 lore raw

PATCH v4 2/7 tegra: spi: add fdt support to tegra SPI SFLASH driver

In reply to Allen Martin

Add support for configuring tegra SPI driver from devicetree. Support is keyed off CONFIG_OF_CONTROL. Add entry in seaboard dts file for spi controller to describe seaboard spi.

Signed-off-by Allen Martin <[email protected]>
---
 drivers/spi/tegra_spi.c |   45 +++++++++++++++++++++++++++++++++++++++++++--
 include/fdtdec.h        |    1 +
 lib/fdtdec.c            |    1 +
 3 files changed, 45 insertions(+), 2 deletions(-)
drivers/spi/tegra_spi.c +43 -2
index 9bb34e2..ce19095 100644
@@ -32,6 +32,9 @@
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/tegra_spi.h>
 #include <spi.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_SPI_CORRUPTS_UART)
  #define corrupt_delay()	udelay(CONFIG_SPI_CORRUPTS_UART_DLY);

@@ -44,6 +47,7 @@ struct tegra_spi_slave {
 	struct spi_tegra *regs;
 	unsigned int freq;
 	unsigned int mode;
+	int periph_id;
 };
 
 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)

@@ -84,8 +88,45 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	}
 	spi->slave.bus = bus;
 	spi->slave.cs = cs;
-	spi->freq = max_hz;
+#ifdef CONFIG_OF_CONTROL
+	int node = fdtdec_next_compatible(gd->fdt_blob, 0,
+					  COMPAT_NVIDIA_TEGRA20_SFLASH);
+	if (node < 0) {
+		debug("%s: cannot locate sflash node\n", __func__);
+		return NULL;
+	}
+	if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
+		debug("%s: sflash is disabled\n", __func__);
+		return NULL;
+	}
+	spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob,
+							node, "reg");
+	if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) {
+		debug("%s: no sflash register found\n", __func__);
+		return NULL;
+	}
+	spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0);
+	if (!spi->freq) {
+		debug("%s: no sflash max frequency found\n", __func__);
+		return NULL;
+	}
+	spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
+	if (spi->periph_id == PERIPH_ID_NONE) {
+		debug("%s: could not decode periph id\n", __func__);
+		return NULL;
+	}
+#else
 	spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
+	spi->freq = TEGRA_SPI_MAX_FREQ;
+	spi->periph_id = PERIPH_ID_SPI1;
+#endif
+	if (max_hz < spi->freq) {
+		debug("%s: limiting frequency from %u to %u\n", __func__,
+		      spi->freq, max_hz);
+		spi->freq = max_hz;
+	}
+	debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n",
+	      __func__, spi->regs, spi->freq, spi->periph_id);
 	spi->mode = mode;
 
 	return &spi->slave;

@@ -110,7 +151,7 @@ int spi_claim_bus(struct spi_slave *slave)
 	u32 reg;
 
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq);
+	clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq);
 
 	/* Clear stale status here */
 	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
include/fdtdec.h +1 -0
index f77d195..5b67a77 100644
@@ -70,6 +70,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
 	COMPAT_NVIDIA_TEGRA20_PWM,	/* Tegra 2 PWM controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA20_SFLASH,	/* Tegra 2 SPI flash controller */
 	COMPAT_SMSC_LAN9215,		/* SMSC 10/100 Ethernet LAN9215 */
 	COMPAT_SAMSUNG_EXYNOS5_SROMC,	/* Exynos5 SROMC */
 	COMPAT_SAMSUNG_S3C2440_I2C,	/* Exynos I2C Controller */
lib/fdtdec.c +1 -0
index 16921e1..385e0e5 100644
@@ -45,6 +45,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
 	COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+	COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
 	COMPAT(SMSC_LAN9215, "smsc,lan9215"),
 	COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
 	COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
Signature · 1 line
1.7.10.4
author
#4 lore raw

PATCH v4 3/7 tegra30: add SBC1 to periph id mapping table

In reply to Allen Martin

SBC1 is SPI controller 1 on tegra30

Signed-off-by Allen Martin <[email protected]>
Acked-by Simon Glass <[email protected]>
---
 arch/arm/cpu/tegra30-common/clock.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/cpu/tegra30-common/clock.c +1 -1
index ee3c8b1..a93f2c9 100644
@@ -290,7 +290,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 
 	/* 40 */
 	NONE(KFUSE),
-	NONE(SBC1),     /* SBC1, 0x34, is this SPI1? */
+	PERIPHC_SBC1,
 	PERIPHC_NOR,
 	NONE(RESERVED43),
 	PERIPHC_SBC2,
Signature · 1 line
1.7.10.4
author
#5 lore raw

PATCH v4 4/7 tegra30: fdt: add SPI SLINK nodes

In reply to Allen Martin

Add tegra30 SPI SLINK nodes to fdt.

Signed-off-by Allen Martin <[email protected]>
Acked-by Simon Glass <[email protected]>
---
 arch/arm/dts/tegra30.dtsi           |   72 +++++++++++++++++++++++++++++++++++
 board/nvidia/dts/tegra30-cardhu.dts |    5 +++
 2 files changed, 77 insertions(+)
arch/arm/dts/tegra30.dtsi +72 -0
index aa7e7ae..7b8126f 100644
@@ -90,4 +90,76 @@
 		/* PERIPH_ID_I2C_DVC, CLK_M */
 		clocks = <&tegra_car 47>;
 	};
+
+	spi at 7000d400 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC1, PLLP_OUT0 */
+		clocks = <&tegra_car 41>;
+	};
+
+	spi at 7000d600 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC2, PLLP_OUT0 */
+		clocks = <&tegra_car 44>;
+	};
+
+	spi at 7000d800 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d480 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC3, PLLP_OUT0 */
+		clocks = <&tegra_car 46>;
+	};
+
+	spi at 7000da00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC4, PLLP_OUT0 */
+		clocks = <&tegra_car 68>;
+	};
+
+	spi at 7000dc00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC5, PLLP_OUT0 */
+		clocks = <&tegra_car 104>;
+	};
+
+	spi at 7000de00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC6, PLLP_OUT0 */
+		clocks = <&tegra_car 105>;
+	};
 };
board/nvidia/dts/tegra30-cardhu.dts +5 -0
index 3223ed4..f9f80c5 100644
@@ -39,4 +39,9 @@
 	i2c at 7000d000 {
 		clock-frequency = <100000>;
 	};
+
+	spi at 7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
 };
Signature · 1 line
1.7.10.4
author
#6 lore raw

PATCH v4 5/7 tegra: add addresses of SPI SLINK controllers

In reply to Allen Martin

Add I/O addresses of SPI SLINK controllers 1-6

Signed-off-by Allen Martin <[email protected]>
Acked-by Simon Glass <[email protected]>
---
 arch/arm/include/asm/arch-tegra/tegra.h |    6 ++++++
 1 file changed, 6 insertions(+)
arch/arm/include/asm/arch-tegra/tegra.h +6 -0
index f97cfd0..bf7229d 100644
@@ -40,6 +40,12 @@
 #define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
 #define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
 #define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_SLINK1_BASE	(NV_PA_APB_MISC_BASE + 0xD400)
+#define NV_PA_SLINK2_BASE	(NV_PA_APB_MISC_BASE + 0xD600)
+#define NV_PA_SLINK3_BASE	(NV_PA_APB_MISC_BASE + 0xD800)
+#define NV_PA_SLINK4_BASE	(NV_PA_APB_MISC_BASE + 0xDA00)
+#define NV_PA_SLINK5_BASE	(NV_PA_APB_MISC_BASE + 0xDC00)
+#define NV_PA_SLINK6_BASE	(NV_PA_APB_MISC_BASE + 0xDE00)
 #define TEGRA_DVC_BASE		(NV_PA_APB_MISC_BASE + 0xD000)
 #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
 #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
Signature · 1 line
1.7.10.4
author
#7 lore raw

PATCH v4 6/7 tegra: add SPI SLINK driver

In reply to Allen Martin

Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller.

This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1.

To enable this driver, use CONFIG_TEGRA_SLINK

Signed-off-by Allen Martin <[email protected]>
---
 arch/arm/include/asm/arch-tegra/tegra_slink.h |   84 ++++++
 board/nvidia/common/board.c                   |    3 +-
 drivers/spi/Makefile                          |    1 +
 drivers/spi/tegra_slink.c                     |  343 +++++++++++++++++++++++++
 include/fdtdec.h                              |    1 +
 lib/fdtdec.c                                  |    1 +
 6 files changed, 432 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h
 create mode 100644 drivers/spi/tegra_slink.c
arch/arm/include/asm/arch-tegra/tegra_slink.h new file +84 -0
new file mode 100644
index 0000000..74804b5
@@ -0,0 +1,84 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_SLINK_H_
+#define _TEGRA_SLINK_H_
+
+#include <asm/types.h>
+
+struct slink_tegra {
+	u32 command;	/* SLINK_COMMAND_0 register  */
+	u32 command2;	/* SLINK_COMMAND2_0 reg */
+	u32 status;	/* SLINK_STATUS_0 register */
+	u32 reserved;	/* Reserved offset 0C */
+	u32 mas_data;	/* SLINK_MAS_DATA_0 reg */
+	u32 slav_data;	/* SLINK_SLAVE_DATA_0 reg */
+	u32 dma_ctl;	/* SLINK_DMA_CTL_0 register */
+	u32 status2;	/* SLINK_STATUS2_0 reg */
+	u32 rsvd[56];	/* 0x20 to 0xFF reserved */
+	u32 tx_fifo;	/* SLINK_TX_FIFO_0 reg off 100h */
+	u32 rsvd2[31];	/* 0x104 to 0x17F reserved */
+	u32 rx_fifo;	/* SLINK_RX_FIFO_0 reg off 180h */
+};
+
+/* COMMAND */
+#define SLINK_CMD_ENB			(1 << 31)
+#define SLINK_CMD_GO			(1 << 30)
+#define SLINK_CMD_M_S			(1 << 28)
+#define SLINK_CMD_CK_SDA		(1 << 21)
+#define SLINK_CMD_CS_POL		(1 << 13)
+#define SLINK_CMD_CS_VAL		(1 << 12)
+#define SLINK_CMD_CS_SOFT		(1 << 11)
+#define SLINK_CMD_BIT_LENGTH		(1 << 4)
+#define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
+/* COMMAND2 */
+#define SLINK_CMD2_TXEN			(1 << 30)
+#define SLINK_CMD2_RXEN			(1 << 31)
+#define SLINK_CMD2_SS_EN		(1 << 18)
+#define SLINK_CMD2_SS_EN_SHIFT		18
+#define SLINK_CMD2_SS_EN_MASK		0x000C0000
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN	(1 << 17)
+/* STATUS */
+#define SLINK_STAT_BSY			(1 << 31)
+#define SLINK_STAT_RDY			(1 << 30)
+#define SLINK_STAT_ERR			(1 << 29)
+#define SLINK_STAT_RXF_FLUSH		(1 << 27)
+#define SLINK_STAT_TXF_FLUSH		(1 << 26)
+#define SLINK_STAT_RXF_OVF		(1 << 25)
+#define SLINK_STAT_TXF_UNR		(1 << 24)
+#define SLINK_STAT_RXF_EMPTY		(1 << 23)
+#define SLINK_STAT_RXF_FULL		(1 << 22)
+#define SLINK_STAT_TXF_EMPTY		(1 << 21)
+#define SLINK_STAT_TXF_FULL		(1 << 20)
+#define SLINK_STAT_TXF_OVF		(1 << 19)
+#define SLINK_STAT_RXF_UNR		(1 << 18)
+#define SLINK_STAT_CUR_BLKCNT		(1 << 15)
+/* STATUS2 */
+#define SLINK_STAT2_RXF_FULL_CNT	(1 << 16)
+#define SLINK_STAT2_TXF_FULL_CNT	(1 << 0)
+
+#define SPI_TIMEOUT		1000
+#define TEGRA_SPI_MAX_FREQ	52000000
+
+#endif	/* _TEGRA_SLINK_H_ */
board/nvidia/common/board.c +2 -1
index e986fcf..d1d8a29 100644
@@ -131,10 +131,11 @@ int board_init(void)
 #ifdef CONFIG_SPI_UART_SWITCH
 	gpio_config_uart();
 #endif
-#ifdef CONFIG_TEGRA_SPI
+#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
 	pin_mux_spi();
 	spi_init();
 #endif
+
 #ifdef CONFIG_PWM_TEGRA
 	if (pwm_init(gd->fdt_blob))
 		debug("%s: Failed to init pwm\n", __func__);
drivers/spi/Makefile +1 -0
index 824d357..83abcbd 100644
@@ -46,6 +46,7 @@ COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
 COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
+COBJS-$(CONFIG_TEGRA_SLINK) += tegra_slink.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 
 COBJS	:= $(COBJS-y)
drivers/spi/tegra_slink.c new file +343 -0

343 lines not on this page · raw message

include/fdtdec.h +1 -0
index 5b67a77..77f244f 100644
@@ -71,6 +71,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_PWM,	/* Tegra 2 PWM controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
 	COMPAT_NVIDIA_TEGRA20_SFLASH,	/* Tegra 2 SPI flash controller */
+	COMPAT_NVIDIA_TEGRA20_SLINK,	/* Tegra 2 SPI SLINK controller */
 	COMPAT_SMSC_LAN9215,		/* SMSC 10/100 Ethernet LAN9215 */
 	COMPAT_SAMSUNG_EXYNOS5_SROMC,	/* Exynos5 SROMC */
 	COMPAT_SAMSUNG_S3C2440_I2C,	/* Exynos I2C Controller */
lib/fdtdec.c +1 -0
index 385e0e5..3ae348d 100644
@@ -46,6 +46,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
 	COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
+	COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"),
 	COMPAT(SMSC_LAN9215, "smsc,lan9215"),
 	COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
 	COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
Signature · 1 line
1.7.10.4
author
#8 lore raw

PATCH v4 7/7 tegra: cardhu: config: enable SPI

In reply to Allen Martin

Turn on SPI in cardhu config file

Signed-off-by Allen Martin <[email protected]>
Acked-by Simon Glass <[email protected]>
---
 include/configs/cardhu.h |   11 +++++++++++
 1 file changed, 11 insertions(+)
include/configs/cardhu.h +11 -0
index aa725ba..1616b39 100644
@@ -49,6 +49,17 @@
 
 #define CONFIG_ENV_IS_NOWHERE
 
+/* SPI */
+#define CONFIG_TEGRA_SLINK
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
Signature · 1 line
1.7.10.4
author
#9 lore raw

v4 cover tegra: SPI drivers

In reply to Allen Martin
Quoted 5 lines · Allen Martin

This series updates the tegra20 SPI driver to add fdt support and adds a new tegra30 SPI driver.

Testing was done on trimslice (tegra20) and cardhu (tegra30).

Tom, this series applies cleanly on top of your T114 series.

Quoted 34 lines

Changes in v4:

(quoted diff) +0 -2
-Added support for fdt aliases to slink driver
-Check "status" field of fdt node to make sure node is enabled

Changes in v3:

(quoted diff) +0 -3
-Dropped some fdt patches from the series that were picked up in 
 u-boot-tegra/next already 
-Removed SPI node from seaboard, added to trimslice
-Incorporated feedback from Simon Glass and Stephen Warren to slink
 driver

Changes in v2:

(quoted diff) +0 -4
-Added new patch to sort dts files prior to adding new nodes
-Moved "max-spi-frequency" out to board dts files
-Moved tegra20 SFLASH fdt changes out to separate patch
-Added valid flag to slink driver controller structure

Allen Martin (7):
tegra20: fdt: add SPI SFLASH node
tegra: spi: add fdt support to tegra SPI SFLASH driver
tegra30: add SBC1 to periph id mapping table
tegra30: fdt: add SPI SLINK nodes
tegra: add addresses of SPI SLINK controllers
tegra: add SPI SLINK driver
tegra: cardhu: config: enable SPI

 arch/arm/cpu/tegra30-common/clock.c           |    2 +-
 arch/arm/dts/tegra20.dtsi                     |   12 +
 arch/arm/dts/tegra30.dtsi                     |   72 ++++++
 arch/arm/include/asm/arch-tegra/tegra.h       |    6 +
 arch/arm/include/asm/arch-tegra/tegra_slink.h |   84 ++++++
 board/compulab/dts/tegra20-trimslice.dts      |    5 +
 board/nvidia/common/board.c                   |    3 +-
 board/nvidia/dts/tegra30-cardhu.dts           |    5 +
 drivers/spi/Makefile                          |    1 +
Quoted 12 lines
 drivers/spi/tegra_slink.c                     |  343 +++++++++++++++++++++++++
 drivers/spi/tegra_spi.c                       |   45 +++-
 include/configs/cardhu.h                      |   11 +
 include/fdtdec.h                              |    2 +
 lib/fdtdec.c                                  |    2 +
 14 files changed, 589 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h
 create mode 100644 drivers/spi/tegra_slink.c
Signature · 1 line
1.7.10.4

-Allen

Signature · 1 line
nvpublic