ARM: OMAP5: Misc fixes

PATCH New Santosh Shilimkar 3 participants 13 messages Jan 18, 2013 – Jan 30, 2013

Subsystems (5)

Device tree bindings Arm (32-bit) Arm sub-architectures OMAP2+ support +1 more subsystems

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Santosh Shilimkar

author

2013-01-18 15:31 UTC #0 lore raw

cover ARM: OMAP5: Misc fixes

Series contains few random fixes needed for OMAP5 es2.0 boot going. There is no depedency with data files for this series and can be applied indepedently.

Tested on OMAP5 uEVM and sEVM boards.

The following changes since commit 7d1f9aeff1ee4a20b1aeb377dd0f579fe9647619:

Linux 3.8-rc4 (2013-01-17 19:25:45 -0800)

are available in the git repository at:

git://github.com/SantoshShilimkar/linux.git for_3.9/omap5_misc_fixes

for you to fetch changes up to 4bedcaba7da88d06cde60aa595dfe57ddd8495cc:

ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer (2013-01-18 20:47:42 +0530)

----------------------------------------------------------------

Rajendra Nayak (1):
ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Santosh Shilimkar (4):
ARM: OMAP5: Update SOC id detection code for ES2
ARM: OMAP2+: timer: Update the OMAP5 clocksource name as per clock
data
ARM: OMAP: prm: Allow prm init to success on OMAP5 SOCs
ARM: dts: omap5-evm: Update available memory to 2032 MB

 arch/arm/boot/dts/omap5-evm.dts |    2 +-
 arch/arm/boot/dts/omap5.dtsi    |   16 ++++++++++++----
 arch/arm/mach-omap2/id.c        |   16 +++++++++++++---
 arch/arm/mach-omap2/prm44xx.c   |    2 +-
 arch/arm/mach-omap2/soc.h       |    2 ++
 arch/arm/mach-omap2/timer.c     |    5 +++--
 6 files changed, 32 insertions(+), 11 deletions(-)

Signature · 1 line

1.7.9.5

Santosh Shilimkar

author

2013-01-18 15:31 UTC #1 lore raw

PATCH 1/5 ARM: OMAP5: Update SOC id detection code for ES2

Update OMAP5 ES2 idcode and make ES2 as default detection.

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/mach-omap2/id.c  |   16 +++++++++++++---
 arch/arm/mach-omap2/soc.h |    2 ++
 2 files changed, 15 insertions(+), 3 deletions(-)

arch/arm/mach-omap2/id.c +13 -3

index 45cc7ed4..ed6f407 100644
@@ -519,22 +519,32 @@ void __init omap5xxx_check_revision(void)
 	case 0xb942:
 		switch (rev) {
 		case 0:
-		default:
 			omap_revision = OMAP5430_REV_ES1_0;
+			break;
+		case 1:
+			omap_revision = OMAP5430_REV_ES2_0;
+			break;
+		default:
+			omap_revision = OMAP5430_REV_ES2_0;
 		}
 		break;
 
 	case 0xb998:
 		switch (rev) {
 		case 0:
-		default:
 			omap_revision = OMAP5432_REV_ES1_0;
+			break;
+		case 1:
+			omap_revision = OMAP5432_REV_ES2_0;
+			break;
+		default:
+			omap_revision = OMAP5432_REV_ES2_0;
 		}
 		break;
 
 	default:
 		/* Unknown default to latest silicon rev as default*/
-		omap_revision = OMAP5430_REV_ES1_0;
+		omap_revision = OMAP5430_REV_ES2_0;
 	}
 
 	pr_info("OMAP%04x ES%d.0\n",

arch/arm/mach-omap2/soc.h +2 -0

index f31d907..4c90b3b 100644
@@ -404,7 +404,9 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 #define OMAP54XX_CLASS		0x54000054
 #define OMAP5430_REV_ES1_0	(OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5430_REV_ES2_0	(OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
 #define OMAP5432_REV_ES1_0	(OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+#define OMAP5432_REV_ES2_0	(OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
 
 void omap2xxx_check_revision(void);
 void omap3xxx_check_revision(void);

Signature · 1 line

1.7.9.5

Santosh Shilimkar

author

2013-01-18 15:31 UTC #2 lore raw

PATCH 2/5 ARM: OMAP2+: timer: Update the OMAP5 clocksource name as per clock data

In reply to Santosh Shilimkar

OMAP5 clockdata has different sys clock clock node name. Fix the timer code to take care of it.

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/mach-omap2/timer.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

arch/arm/mach-omap2/timer.c +3 -2

index 691aa67..a0a1b14 100644
@@ -62,6 +62,7 @@
 #define OMAP2_MPU_SOURCE	"sys_ck"
 #define OMAP3_MPU_SOURCE	OMAP2_MPU_SOURCE
 #define OMAP4_MPU_SOURCE	"sys_clkin_ck"
+#define OMAP5_MPU_SOURCE	"sys_clkin"
 #define OMAP2_32K_SOURCE	"func_32k_ck"
 #define OMAP3_32K_SOURCE	"omap_32k_fck"
 #define OMAP4_32K_SOURCE	"sys_32k_ck"

@@ -498,7 +499,7 @@ static void __init realtime_counter_init(void)
 		pr_err("%s: ioremap failed\n", __func__);
 		return;
 	}
-	sys_clk = clk_get(NULL, "sys_clkin_ck");
+	sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
 	if (IS_ERR(sys_clk)) {
 		pr_err("%s: failed to get system clock handle\n", __func__);
 		iounmap(base);

@@ -638,7 +639,7 @@ OMAP_SYS_TIMER(4, local);
 
 #ifdef CONFIG_SOC_OMAP5
 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-			2, OMAP4_MPU_SOURCE);
+			2, OMAP5_MPU_SOURCE);
 static void __init omap5_realtime_timer_init(void)
 {
 	int err;

Signature · 1 line

1.7.9.5

Jon Hunter

2013-01-30 17:42 UTC #3 lore raw

PATCH 2/5 ARM: OMAP2+: timer: Update the OMAP5 clocksource name as per clock data

Quoted 13 lines · Santosh Shilimkar

OMAP5 clockdata has different sys clock clock node name. Fix the timer code to take care of it.
Signed-off-by Santosh Shilimkar <[email protected]>
---
 arch/arm/mach-omap2/timer.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
arch/arm/mach-omap2/timer.c +0 -0
index 691aa67..a0a1b14 100644

arch/arm/mach-omap2/timer.c line 65

Quoted 4 lines

arch/arm/mach-omap2/timer.c +1 -0

@@ -62,6 +62,7 @@
 #define OMAP2_MPU_SOURCE	"sys_ck"
 #define OMAP3_MPU_SOURCE	OMAP2_MPU_SOURCE
 #define OMAP4_MPU_SOURCE	"sys_clkin_ck"
+#define OMAP5_MPU_SOURCE	"sys_clkin"

I would like to remove this definitions and in fact posted a patch today to do that [1] ;-)

Quoted 13 lines

arch/arm/mach-omap2/timer.c +1 -1

 #define OMAP2_32K_SOURCE	"func_32k_ck"
 #define OMAP3_32K_SOURCE	"omap_32k_fck"
 #define OMAP4_32K_SOURCE	"sys_32k_ck"

@@ -498,7 +499,7 @@ static void __init realtime_counter_init(void)
 		pr_err("%s: ioremap failed\n", __func__);
 		return;
 	}
-	sys_clk = clk_get(NULL, "sys_clkin_ck");
+	sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
 	if (IS_ERR(sys_clk)) {
 		pr_err("%s: failed to get system clock handle\n", __func__);
 		iounmap(base);

arch/arm/mach-omap2/timer.c OMAP_SYS_TIMER(4, local); · line 642

Quoted 5 lines

arch/arm/mach-omap2/timer.c +1 -1

@@ -638,7 +639,7 @@ OMAP_SYS_TIMER(4, local);
 
 #ifdef CONFIG_SOC_OMAP5
 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-			2, OMAP4_MPU_SOURCE);
+			2, OMAP5_MPU_SOURCE);

I am hoping we can remove this completely for omap5 and use the same function defined for omap2 [2].

Care to try your series on top of mine [3] on omap5?

Cheers
Jon

[1] http://www.spinics.net/lists/arm-kernel/msg221263.html
[2] http://www.spinics.net/lists/arm-kernel/msg221264.html
[3] http://www.spinics.net/lists/arm-kernel/msg221260.html

Santosh Shilimkar

author

2013-01-18 15:31 UTC #4 lore raw

PATCH 3/5 ARM: OMAP: prm: Allow prm init to success on OMAP5 SOCs

In reply to Santosh Shilimkar

Allow prm init to success on OMAP5 SOCs.

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/mach-omap2/prm44xx.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/mach-omap2/prm44xx.c +1 -1

index c05a343..1aae198 100644
@@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 
 int __init omap44xx_prm_init(void)
 {
-	if (!cpu_is_omap44xx())
+	if (!cpu_is_omap44xx() && !soc_is_omap54xx())
 		return 0;
 
 	return prm_register(&omap44xx_prm_ll_data);

Signature · 1 line

1.7.9.5

Santosh Shilimkar

author

2013-01-18 15:31 UTC #5 lore raw

PATCH 4/5 ARM: dts: omap5-evm: Update available memory to 2032 MB

In reply to Santosh Shilimkar

On OMAP5 to detect invalid/bad memory accesses, 16MB of DDR is used as a trap. Hence available memory for linux OS is 2032 MB on boards popullated with 2 GB memory.

Cc Benoit Cousson <[email protected]>

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/boot/dts/omap5-evm.dts |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/boot/dts/omap5-evm.dts +1 -1

index 8722c15..b0e218a 100644
@@ -16,7 +16,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x80000000>; /* 2 GB */
+		reg = <0x80000000 0x7F000000>; /* 2032 MB */
 	};
 
 	vmmcsd_fixed: fixedregulator-mmcsd {

Signature · 1 line

1.7.9.5

Santosh Shilimkar

author

2013-01-18 15:31 UTC #6 lore raw

PATCH 5/5 ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

In reply to Santosh Shilimkar

From: Rajendra Nayak <[email protected]>

Specify both secure as well as nonsecure PPI IRQ for arch timer. This fixes the following errors seen on DT OMAP5 boot..

[    0.000000] arch_timer: No interrupt available, giving up

Cc Benoit Cousson <[email protected]>

Signed-off-by Rajendra Nayak <[email protected]>

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/boot/dts/omap5.dtsi |   16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

arch/arm/boot/dts/omap5.dtsi +12 -4

index 790bb2a..7a78d1b 100644
@@ -35,8 +35,12 @@
 			compatible = "arm,cortex-a15";
 			timer {
 				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
+				/*
+				 * PPI secure/nonsecure IRQ,
+				 * active low level-sensitive
+				 */
+				interrupts = <1 13 0x308>,
+					     <1 14 0x308>;
 				clock-frequency = <6144000>;
 			};
 		};

@@ -44,8 +48,12 @@
 			compatible = "arm,cortex-a15";
 			timer {
 				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
+				/*
+				 * PPI secure/nonsecure IRQ,
+				 * active low level-sensitive
+				 */
+				interrupts = <1 13 0x308>,
+					     <1 14 0x308>;
 				clock-frequency = <6144000>;
 			};
 		};

Signature · 1 line

1.7.9.5

Marc Zyngier

2013-01-18 16:02 UTC #7 lore raw

PATCH 5/5 ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Quoted 21 lines · Santosh Shilimkar

From: Rajendra Nayak <[email protected]>
Specify both secure as well as nonsecure PPI IRQ for arch timer. This fixes the following errors seen on DT OMAP5 boot..
[    0.000000] arch_timer: No interrupt available, giving up
Cc Benoit Cousson <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---
 arch/arm/boot/dts/omap5.dtsi |   16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)
arch/arm/boot/dts/omap5.dtsi +0 -0
index 790bb2a..7a78d1b 100644
@@ -35,8 +35,12 @@
 			compatible = "arm,cortex-a15";

arch/arm/boot/dts/omap5.dtsi line 43

Quoted 10 lines

arch/arm/boot/dts/omap5.dtsi +6 -2

 			timer {
 				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
+				/*
+				 * PPI secure/nonsecure IRQ,
+				 * active low level-sensitive
+				 */
+				interrupts = <1 13 0x308>,
+					     <1 14 0x308>;

Care to add the virtual and HYP timer interrupts? So KVM can get a chance to run on this HW...

Quoted 5 lines

arch/arm/boot/dts/omap5.dtsi +0 -0

 				clock-frequency = <6144000>;
 			};
 		};

@@ -44,8 +48,12 @@
 			compatible = "arm,cortex-a15";

arch/arm/boot/dts/omap5.dtsi line 56

Quoted 10 lines

arch/arm/boot/dts/omap5.dtsi +6 -2

 			timer {
 				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
+				/*
+				 * PPI secure/nonsecure IRQ,
+				 * active low level-sensitive
+				 */
+				interrupts = <1 13 0x308>,
+					     <1 14 0x308>;

Same here.

arch/arm/boot/dts/omap5.dtsi line 46

Quoted 4 lines

arch/arm/boot/dts/omap5.dtsi +0 -0

 				clock-frequency = <6144000>;
 			};
 		};

Thanks,

M.

Signature · 1 line

Jazz is not dead. It just smells funny...

Santosh Shilimkar

author

2013-01-18 16:59 UTC #8 lore raw

PATCH 5/5 ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Quoted 27 lines · Marc Zyngier

Quoted 26 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Specify both secure as well as nonsecure PPI IRQ for arch timer. This fixes the following errors seen on DT OMAP5 boot..
[    0.000000] arch_timer: No interrupt available, giving up
Cc Benoit Cousson <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---
  arch/arm/boot/dts/omap5.dtsi |   16 ++++++++++++----
  1 file changed, 12 insertions(+), 4 deletions(-)
arch/arm/boot/dts/omap5.dtsi +1 -2
index 790bb2a..7a78d1b 100644
@@ -35,8 +35,12 @@
  			compatible = "arm,cortex-a15";
  			timer {
  				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
+				/*

Quoted 9 lines

arch/arm/boot/dts/omap5.dtsi line 43
Quoted 5 lines
arch/arm/boot/dts/omap5.dtsi +5 -0
+				 * PPI secure/nonsecure IRQ,
+				 * active low level-sensitive
+				 */
+				interrupts = <1 13 0x308>,
+					     <1 14 0x308>;
Care to add the virtual and HYP timer interrupts? So KVM can get a chance to run on this HW...

Thanks Marc for spotting it. Will take care of it.

Regards
Santosh

Marc Zyngier

2013-01-18 17:08 UTC #9 lore raw

PATCH 5/5 ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Quoted 37 lines · Santosh Shilimkar

Quoted 27 lines · Marc Zyngier
Quoted 26 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Specify both secure as well as nonsecure PPI IRQ for arch timer. This fixes the following errors seen on DT OMAP5 boot..
[    0.000000] arch_timer: No interrupt available, giving up
Cc Benoit Cousson <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---
  arch/arm/boot/dts/omap5.dtsi |   16 ++++++++++++----
  1 file changed, 12 insertions(+), 4 deletions(-)
arch/arm/boot/dts/omap5.dtsi +1 -2
index 790bb2a..7a78d1b 100644
@@ -35,8 +35,12 @@
  			compatible = "arm,cortex-a15";
  			timer {
  				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
+				/*
Quoted 9 lines
arch/arm/boot/dts/omap5.dtsi line 43
Quoted 5 lines
arch/arm/boot/dts/omap5.dtsi +5 -0
+				 * PPI secure/nonsecure IRQ,
+				 * active low level-sensitive
+				 */
+				interrupts = <1 13 0x308>,
+					     <1 14 0x308>;
Care to add the virtual and HYP timer interrupts? So KVM can get a chance to run on this HW...

Quoted 1 line

Thanks Marc for spotting it. Will take care of it.

I just realised something silly... You have one timer node *per cpu*, and this is not really expected.

The driver really wants one single node. See arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts for an example.

Oh, and your GIC node could do with some updating too (no VGIC regs or interrupt).

M.

Signature · 1 line

Jazz is not dead. It just smells funny...

Santosh Shilimkar

author

2013-01-18 18:50 UTC #10 lore raw

PATCH 5/5 ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Quoted 38 lines · Marc Zyngier

Quoted 37 lines · Santosh Shilimkar
Quoted 36 lines · Marc Zyngier
Quoted 21 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Specify both secure as well as nonsecure PPI IRQ for arch timer. This fixes the following errors seen on DT OMAP5 boot..
[    0.000000] arch_timer: No interrupt available, giving up
Cc Benoit Cousson <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---
   arch/arm/boot/dts/omap5.dtsi |   16 ++++++++++++----
   1 file changed, 12 insertions(+), 4 deletions(-)
arch/arm/boot/dts/omap5.dtsi +0 -0
index 790bb2a..7a78d1b 100644
@@ -35,8 +35,12 @@
   			compatible = "arm,cortex-a15";
arch/arm/boot/dts/omap5.dtsi line 43
Quoted 10 lines
arch/arm/boot/dts/omap5.dtsi +6 -2
   			timer {
   				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
+				/*
+				 * PPI secure/nonsecure IRQ,
+				 * active low level-sensitive
+				 */
+				interrupts = <1 13 0x308>,
+					     <1 14 0x308>;
Care to add the virtual and HYP timer interrupts? So KVM can get a chance to run on this HW...

Quoted 5 lines

Quoted 1 line
Thanks Marc for spotting it. Will take care of it.
I just realised something silly... You have one timer node *per cpu*, and this is not really expected.

This was discussed on the list here [1]
Benoit suggested to add per CPU node since arch timer is per CPU and DT should describe the hw the way it is. Did we miss something ?

Quoted 3 lines

The driver really wants one single node. See arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts for an example.

I remember adding only one node based on above file and then updating the patch based on the comment.

Quoted 3 lines

Oh, and your GIC node could do with some updating too (no VGIC regs or interrupt).

Will have a look at that as well.

Regards
Santosh,

[1] https://patchwork.kernel.org/patch/1312061/

Marc Zyngier

2013-01-19 14:46 UTC #11 lore raw

PATCH 5/5 ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Quoted 42 lines · Santosh Shilimkar

Quoted 41 lines · Marc Zyngier
Quoted 39 lines · Santosh Shilimkar
Quoted 28 lines · Marc Zyngier
Quoted 27 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Specify both secure as well as nonsecure PPI IRQ for arch timer. This fixes the following errors seen on DT OMAP5 boot..
[    0.000000] arch_timer: No interrupt available, giving up
Cc Benoit Cousson <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---
   arch/arm/boot/dts/omap5.dtsi |   16 ++++++++++++----
   1 file changed, 12 insertions(+), 4 deletions(-)
arch/arm/boot/dts/omap5.dtsi +1 -2
index 790bb2a..7a78d1b 100644
@@ -35,8 +35,12 @@
   			compatible = "arm,cortex-a15";
   			timer {
   				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
+				/*
Quoted 9 lines
arch/arm/boot/dts/omap5.dtsi line 43
Quoted 5 lines
arch/arm/boot/dts/omap5.dtsi +5 -0
+				 * PPI secure/nonsecure IRQ,
+				 * active low level-sensitive
+				 */
+				interrupts = <1 13 0x308>,
+					     <1 14 0x308>;
Care to add the virtual and HYP timer interrupts? So KVM can get a chance to run on this HW...
Thanks Marc for spotting it. Will take care of it.

Quoted 7 lines

Quoted 3 lines
I just realised something silly... You have one timer node *per cpu*, and this is not really expected.
This was discussed on the list here [1]
Benoit suggested to add per CPU node since arch timer is per CPU and DT should describe the hw the way it is. Did we miss something ?

The current approach is not to duplicate banked resources. We do not have duplicated twd-timer nodes on Cortex A9, we do not expose multiple CPU interfaces for the GIC...

And speaking of the GIC: how do you interpret the CPU mask in the interrupt field of the timer? The value 0x3xx in the third field is there to indicate that CPU0 and CPU1 are getting interrupted by the timer. What does it mean when you duplicate it?

M.

Signature · 1 line

Fast, cheap, reliable. Pick two.

Santosh Shilimkar

author

2013-01-19 17:26 UTC #12 lore raw

PATCH 5/5 ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Quoted 47 lines · Marc Zyngier

Quoted 45 lines · Santosh Shilimkar
Quoted 44 lines · Marc Zyngier
Quoted 38 lines · Santosh Shilimkar
Quoted 28 lines · Marc Zyngier
Quoted 27 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Specify both secure as well as nonsecure PPI IRQ for arch timer. This fixes the following errors seen on DT OMAP5 boot..
[    0.000000] arch_timer: No interrupt available, giving up
Cc Benoit Cousson <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---
    arch/arm/boot/dts/omap5.dtsi |   16 ++++++++++++----
    1 file changed, 12 insertions(+), 4 deletions(-)
arch/arm/boot/dts/omap5.dtsi +1 -2
index 790bb2a..7a78d1b 100644
@@ -35,8 +35,12 @@
    			compatible = "arm,cortex-a15";
    			timer {
    				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
+				/*
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arch/arm/boot/dts/omap5.dtsi line 43
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arch/arm/boot/dts/omap5.dtsi +5 -0
+				 * PPI secure/nonsecure IRQ,
+				 * active low level-sensitive
+				 */
+				interrupts = <1 13 0x308>,
+					     <1 14 0x308>;
Care to add the virtual and HYP timer interrupts? So KVM can get a chance to run on this HW...
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Thanks Marc for spotting it. Will take care of it.
I just realised something silly... You have one timer node *per cpu*, and this is not really expected.

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This was discussed on the list here [1]
Benoit suggested to add per CPU node since arch timer is per CPU and DT should describe the hw the way it is. Did we miss something ?
The current approach is not to duplicate banked resources. We do not have duplicated twd-timer nodes on Cortex A9, we do not expose multiple CPU interfaces for the GIC...

Yes, I have observed that. The arch/twd timer DT extraction code doesn't expect per CPU DT node and on that basis only, initial patch was adding single timer node outside cpu node. Benoit comment was that the DT should describe the way hardware is and probably the DT extraction code should be updated accordingly.

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And speaking of the GIC: how do you interpret the CPU mask in the interrupt field of the timer? The value 0x3xx in the third field is there to indicate that CPU0 and CPU1 are getting interrupted by the timer. What
does it mean when you duplicate it?> M.

Here too I have to keep mask for both CPUs because of the current DT extraction code. I some how forgot to bring that discussion to your notice. I can update the DT files to go back to the single timer node if the plan is not to duplicate the per CPU resources.

Benoit,
Whats your take on it ?

Regards
Santosh