ARM: OMAP: Clear GPMC bits when applying new setting.

PATCH In review Mark Jackson 2 participants 3 messages Mar 5, 2013 – Mar 6, 2013

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Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP power management support +1 more subsystems

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Mark Jackson

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2013-03-05 10:13 UTC #0 lore raw

PATCH v2 1/1 ARM: OMAP: Clear GPMC bits when applying new setting.

When setting the GPMC device type, make sure any previous bits are cleared down, before applying the new setting.

Signed-off-by Mark Jackson <[email protected]>

---
Changes in v2:
- Change mux type to 2 bits
- Add extra mux types in gpmc.h

 arch/arm/mach-omap2/gpmc.c |    4 ++++
 arch/arm/mach-omap2/gpmc.h |    5 ++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

arch/arm/mach-omap2/gpmc.c +4 -0

index 410e1ba..479369c 100644
@@ -613,6 +613,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
 
 	case GPMC_CONFIG_DEV_TYPE:
 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+		/* clear 4 target bits */
+		regval &= ~(GPMC_CONFIG1_DEVICETYPE(3) |
+			    GPMC_CONFIG1_MUXTYPE(3));
+		/* set the proper value */
 		regval |= GPMC_CONFIG1_DEVICETYPE(wval);
 		if (wval == GPMC_DEVICETYPE_NOR)
 			regval |= GPMC_CONFIG1_MUXADDDATA;

arch/arm/mach-omap2/gpmc.h +4 -1

index fe0a844..f79cbde 100644
@@ -58,7 +58,10 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
+#define GPMC_CONFIG1_MUXNONMUX          GPMC_CONFIG1_MUXTYPE(0)
+#define GPMC_CONFIG1_MUXAAD             GPMC_CONFIG1_MUXTYPE(1)
+#define GPMC_CONFIG1_MUXADDDATA         GPMC_CONFIG1_MUXTYPE(2)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))

Signature · 1 line

1.7.9.5

Jon Hunter

2013-03-06 22:40 UTC #1 lore raw

Quoted 34 lines · Mark Jackson

When setting the GPMC device type, make sure any previous bits are cleared down, before applying the new setting.

Signed-off-by Mark Jackson <[email protected]>

---
Changes in v2:
- Change mux type to 2 bits
- Add extra mux types in gpmc.h

 arch/arm/mach-omap2/gpmc.c |    4 ++++
 arch/arm/mach-omap2/gpmc.h |    5 ++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

arch/arm/mach-omap2/gpmc.c +4 -0

index 410e1ba..479369c 100644
@@ -613,6 +613,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
 
 	case GPMC_CONFIG_DEV_TYPE:
 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+		/* clear 4 target bits */
+		regval &= ~(GPMC_CONFIG1_DEVICETYPE(3) |
+			    GPMC_CONFIG1_MUXTYPE(3));
+		/* set the proper value */
 		regval |= GPMC_CONFIG1_DEVICETYPE(wval);
 		if (wval == GPMC_DEVICETYPE_NOR)
 			regval |= GPMC_CONFIG1_MUXADDDATA;

arch/arm/mach-omap2/gpmc.h +0 -0

index fe0a844..f79cbde 100644
@@ -58,7 +58,10 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)

arch/arm/mach-omap2/gpmc.h line 67

Quoted 10 lines

arch/arm/mach-omap2/gpmc.h +4 -1

 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
+#define GPMC_CONFIG1_MUXNONMUX          GPMC_CONFIG1_MUXTYPE(0)
+#define GPMC_CONFIG1_MUXAAD             GPMC_CONFIG1_MUXTYPE(1)
+#define GPMC_CONFIG1_MUXADDDATA         GPMC_CONFIG1_MUXTYPE(2)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))

Thanks for updating. I do plan to get rid of the part of the gpmc_cs_configure() function [1]. However, I will pull in and based my series on top of this.

Jon

[1] https://patchwork.kernel.org/patch/2186631/

Jon Hunter

2013-03-06 22:53 UTC #2 lore raw

Quoted 42 lines · Jon Hunter

Quoted 40 lines · Mark Jackson

When setting the GPMC device type, make sure any previous bits are cleared down, before applying the new setting.

Signed-off-by Mark Jackson <[email protected]>

---
Changes in v2:
- Change mux type to 2 bits
- Add extra mux types in gpmc.h

 arch/arm/mach-omap2/gpmc.c |    4 ++++
 arch/arm/mach-omap2/gpmc.h |    5 ++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

arch/arm/mach-omap2/gpmc.c +4 -0

index 410e1ba..479369c 100644
@@ -613,6 +613,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
 
 	case GPMC_CONFIG_DEV_TYPE:
 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+		/* clear 4 target bits */
+		regval &= ~(GPMC_CONFIG1_DEVICETYPE(3) |
+			    GPMC_CONFIG1_MUXTYPE(3));
+		/* set the proper value */
 		regval |= GPMC_CONFIG1_DEVICETYPE(wval);
 		if (wval == GPMC_DEVICETYPE_NOR)
 			regval |= GPMC_CONFIG1_MUXADDDATA;

arch/arm/mach-omap2/gpmc.h +3 -1

index fe0a844..f79cbde 100644
@@ -58,7 +58,10 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
+#define GPMC_CONFIG1_MUXNONMUX          GPMC_CONFIG1_MUXTYPE(0)
+#define GPMC_CONFIG1_MUXAAD             GPMC_CONFIG1_MUXTYPE(1)

Quoted 8 lines

arch/arm/mach-omap2/gpmc.h line 67
Quoted 4 lines
arch/arm/mach-omap2/gpmc.h +1 -0
+#define GPMC_CONFIG1_MUXADDDATA         GPMC_CONFIG1_MUXTYPE(2)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
Thanks for updating. I do plan to get rid of the part of the gpmc_cs_configure() function [1]. However, I will pull in and based my series on top of this.

Just updated changelog to add a comment about the change in the bit fields in case anyone asks ...

Quoted 1 line

From 476acdd9049badc3971b1f1f3df200748dd9a196 Mon Sep 17 00:00:00 2001

From: Mark Jackson <[email protected]>
Date: Tue, 5 Mar 2013 10:13:40 +0000
Subject: [PATCH] ARM: OMAP: Clear GPMC bits when applying new setting.

When setting the GPMC device type, make sure any previous bits are cleared down, before applying the new setting.

For OMAP4+ devices MUXADDDATA is a 2-bit field (bits 9:8) where as for OMAP2/3 devices it was only a one bit field (bit 9). For OMAP2/3 devices bit 8 is reserved and the OMAP documentation says to write a 0 to this bit. So clearing bit 8 on OMAP2/3 devices should not be a problem. Hence update the code to handle both bits 8 and 9 for all devices.

Signed-off-by Mark Jackson <[email protected]>

[[email protected]: updated changelog]

Signed-off-by Jon Hunter <[email protected]>

---
 arch/arm/mach-omap2/gpmc.c |    4 ++++
 arch/arm/mach-omap2/gpmc.h |    5 ++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

arch/arm/mach-omap2/gpmc.c +4 -0

index 410e1ba..479369c 100644
@@ -613,6 +613,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
 
 	case GPMC_CONFIG_DEV_TYPE:
 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+		/* clear 4 target bits */
+		regval &= ~(GPMC_CONFIG1_DEVICETYPE(3) |
+			    GPMC_CONFIG1_MUXTYPE(3));
+		/* set the proper value */
 		regval |= GPMC_CONFIG1_DEVICETYPE(wval);
 		if (wval == GPMC_DEVICETYPE_NOR)
 			regval |= GPMC_CONFIG1_MUXADDDATA;

arch/arm/mach-omap2/gpmc.h +4 -1

index fe0a844..f79cbde 100644
@@ -58,7 +58,10 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
+#define GPMC_CONFIG1_MUXNONMUX          GPMC_CONFIG1_MUXTYPE(0)
+#define GPMC_CONFIG1_MUXAAD             GPMC_CONFIG1_MUXTYPE(1)
+#define GPMC_CONFIG1_MUXADDDATA         GPMC_CONFIG1_MUXTYPE(2)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))

Signature · 1 line

1.7.10.4