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MIPS: Netlogic: Remove unused EIMR/EIRR functions

PATCH In review Jayachandran C 3 participants 13 messages Mar 23, 2013 – Mar 25, 2013 1 message not in the archive MIPS

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A message that is not in the archive (sent off-list or not yet received): [email protected]

Jayachandran C

author
#1 lore raw

PATCH 1/9 MIPS: Netlogic: Optimize and fix write_c0_eimr()

Remove the irq save/restore from write_c0_eimr(), as it is always called with interrupts off.

This allows us to remove workaround in write_c0_eimr() to fix up the flags used by local_irq_save. This fixup worked on XLR, but will break when 32-bit support is added to r2 cpus like XLP.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/netlogic/mips-extns.h |   13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)
arch/mips/include/asm/netlogic/mips-extns.h +5 -8
index 8ad2e0f..69d18a0 100644
@@ -43,16 +43,15 @@
 #define write_c0_eirr(val)	__write_64bit_c0_register($9, 6, val)
 
 /*
- * Writing EIMR in 32 bit is a special case, the lower 8 bit of the
- * EIMR is shadowed in the status register, so we cannot save and
- * restore status register for split read.
+ * NOTE: Do not save/restore flags around write_c0_eimr().
+ * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS
+ * register. Restoring flags will overwrite the lower 8 bits of EIMR.
+ *
+ * Call with interrupts disabled.
  */
 #define write_c0_eimr(val)						\
 do {									\
 	if (sizeof(unsigned long) == 4) {				\
-		unsigned long __flags;					\
-									\
-		local_irq_save(__flags);				\
 		__asm__ __volatile__(					\
 			".set\tmips64\n\t"				\
 			"dsll\t%L0, %L0, 32\n\t"			\

@@ -62,8 +61,6 @@ do {									\
 			"dmtc0\t%L0, $9, 7\n\t"				\
 			".set\tmips0"					\
 			: : "r" (val));					\
-		__flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\
-		local_irq_restore(__flags);				\
 	} else								\
 		__write_64bit_c0_register($9, 7, (val));		\
 } while (0)
Signature · 1 line
1.7.9.5
author
#2 lore raw

PATCH 2/9 MIPS: Netlogic: Remove unused EIMR/EIRR functions

In reply to a message not in the archive

Remove the definitions of {read,write}_c0_{eirr,eimr}. These functions are now unused after the PIC and IRQ code has been updated to use optimized EIMR/EIRR functions which work on both 32-bit and 64-bit.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/netlogic/mips-extns.h |    7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)
arch/mips/include/asm/netlogic/mips-extns.h +1 -6
index 69d18a0..f299d31 100644
@@ -38,10 +38,6 @@
 /*
  * XLR and XLP interrupt request and interrupt mask registers
  */
-#define read_c0_eirr()		__read_64bit_c0_register($9, 6)
-#define read_c0_eimr()		__read_64bit_c0_register($9, 7)
-#define write_c0_eirr(val)	__write_64bit_c0_register($9, 6, val)
-
 /*
  * NOTE: Do not save/restore flags around write_c0_eimr().
  * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS

@@ -125,7 +121,7 @@ static inline uint64_t read_c0_eirr_and_eimr(void)
 	uint64_t val;
 
 #ifdef CONFIG_64BIT
-	val = read_c0_eimr() & read_c0_eirr();
+	val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7);
 #else
 	__asm__ __volatile__(
 		".set	push\n\t"

@@ -140,7 +136,6 @@ static inline uint64_t read_c0_eirr_and_eimr(void)
 		".set	pop"
 		: "=r" (val));
 #endif
-
 	return val;
 }
Signature · 1 line
1.7.9.5
#3 lore raw

Hello.

Quoted 13 lines · Jayachandran C

Remove the definitions of {read,write}_c0_{eirr,eimr}. These functions are now unused after the PIC and IRQ code has been updated to use optimized EIMR/EIRR functions which work on both 32-bit and 64-bit.

Signed-off-by Jayachandran C <[email protected]>
---
  arch/mips/include/asm/netlogic/mips-extns.h |    7 +------
  1 file changed, 1 insertion(+), 6 deletions(-)
arch/mips/include/asm/netlogic/mips-extns.h +0 -0
index 69d18a0..f299d31 100644

[...]

arch/mips/include/asm/netlogic/mips-extns.h static inline uint64_t read_c0_eirr_and_eimr(void) · line 143

Quoted 5 lines
arch/mips/include/asm/netlogic/mips-extns.h +0 -1
@@ -140,7 +136,6 @@ static inline uint64_t read_c0_eirr_and_eimr(void)
  		".set	pop"
  		: "=r" (val));
  #endif
-

Unrelated whitespace change.

arch/mips/include/asm/netlogic/mips-extns.h static inline uint64_t read_c0_eirr_and_eimr(void) · line 141

Quoted 3 lines
arch/mips/include/asm/netlogic/mips-extns.h +0 -0
  	return val;
  }

WBR, Sergei

author
#4 lore raw
Quoted 18 lines · Sergei Shtylyov

Hello.

Quoted 13 lines · Jayachandran C

Remove the definitions of {read,write}_c0_{eirr,eimr}. These functions are now unused after the PIC and IRQ code has been updated to use optimized EIMR/EIRR functions which work on both 32-bit and 64-bit.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/netlogic/mips-extns.h |    7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)
arch/mips/include/asm/netlogic/mips-extns.h +0 -0
index 69d18a0..f299d31 100644

[...]

Quoted 10 lines

arch/mips/include/asm/netlogic/mips-extns.h static inline uint64_t read_c0_eirr_and_eimr(void) · line 143

Quoted 5 lines
arch/mips/include/asm/netlogic/mips-extns.h +0 -1
@@ -140,7 +136,6 @@ static inline uint64_t read_c0_eirr_and_eimr(void)
 		".set	pop"
 		: "=r" (val));
 #endif
-

Unrelated whitespace change.

Quoted 2 lines
arch/mips/include/asm/netlogic/mips-extns.h +0 -0
 	return val;
 }

While updating that function, I had removed an empty line which was not really needed. Not sure if it is worth adding a line in commit message for that.

JC.

author
#5 lore raw

PATCH 3/9 MIPS: Netlogic: print cpumask with cpumask_scnprintf

In reply to a message not in the archive

Use standard function to print cpumask. Also fixup the name of the variable used and make it static.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/netlogic/common/smp.c |   21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)
arch/mips/netlogic/common/smp.c +12 -9
index 2bb95dc..ffba524 100644
@@ -148,8 +148,7 @@ void nlm_cpus_done(void)
 int nlm_cpu_ready[NR_CPUS];
 unsigned long nlm_next_gp;
 unsigned long nlm_next_sp;
-
-cpumask_t phys_cpu_present_map;
+static cpumask_t phys_cpu_present_mask;
 
 void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
 {

@@ -169,11 +168,12 @@ void __init nlm_smp_setup(void)
 {
 	unsigned int boot_cpu;
 	int num_cpus, i, ncore;
+	char buf[64];
 
 	boot_cpu = hard_smp_processor_id();
-	cpumask_clear(&phys_cpu_present_map);
+	cpumask_clear(&phys_cpu_present_mask);
 
-	cpumask_set_cpu(boot_cpu, &phys_cpu_present_map);
+	cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask);
 	__cpu_number_map[boot_cpu] = 0;
 	__cpu_logical_map[0] = boot_cpu;
 	set_cpu_possible(0, true);

@@ -185,7 +185,7 @@ void __init nlm_smp_setup(void)
 		 * it is only set for ASPs (see smpboot.S)
 		 */
 		if (nlm_cpu_ready[i]) {
-			cpumask_set_cpu(i, &phys_cpu_present_map);
+			cpumask_set_cpu(i, &phys_cpu_present_mask);
 			__cpu_number_map[i] = num_cpus;
 			__cpu_logical_map[num_cpus] = i;
 			set_cpu_possible(num_cpus, true);

@@ -193,16 +193,19 @@ void __init nlm_smp_setup(void)
 		}
 	}
 
+	cpumask_scnprintf(buf, ARRAY_SIZE(buf), &phys_cpu_present_mask);
+	pr_info("Physical CPU mask: %s\n", buf);
+	cpumask_scnprintf(buf, ARRAY_SIZE(buf), cpu_possible_mask);
+	pr_info("Possible CPU mask: %s\n", buf);
+
 	/* check with the cores we have worken up */
 	for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
 		ncore += hweight32(nlm_get_node(i)->coremask);
 
-	pr_info("Phys CPU present map: %lx, possible map %lx\n",
-		(unsigned long)cpumask_bits(&phys_cpu_present_map)[0],
-		(unsigned long)cpumask_bits(cpu_possible_mask)[0]);
-
 	pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore,
 		nlm_threads_per_core, num_cpus);
+
+	/* switch NMI handler to boot CPUs */
 	nlm_set_nmi_handler(nlm_boot_secondary_cpus);
 }
Signature · 1 line
1.7.9.5
author
#6 lore raw

PATCH 4/9 MIPS: Netlogic: Avoid using fixed PIC IRT index

In reply to a message not in the archive

The index for a device interrupt in the PIC interrupt routing table changes for different chips in the XLP family. Avoid using the fixed entries and derive the index value from the SoC device header.

Add workarounds for some devices which do not report the IRT index correctly.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/netlogic/xlp-hal/pic.h |   53 ----------------------
 arch/mips/netlogic/xlp/nlm_hal.c             |   62 +++++++++++++++++---------
 2 files changed, 40 insertions(+), 75 deletions(-)
arch/mips/include/asm/netlogic/xlp-hal/pic.h +0 -53
index 3df5301..a981f46 100644
@@ -191,59 +191,6 @@
 #define PIC_IRT_PCIE_LINK_2_INDEX	80
 #define PIC_IRT_PCIE_LINK_3_INDEX	81
 #define PIC_IRT_PCIE_LINK_INDEX(num)	((num) + PIC_IRT_PCIE_LINK_0_INDEX)
-/* 78 to 81 */
-#define PIC_NUM_NA_IRTS			32
-/* 82 to 113 */
-#define PIC_IRT_NA_0_INDEX		82
-#define PIC_IRT_NA_INDEX(num)		((num) + PIC_IRT_NA_0_INDEX)
-#define PIC_IRT_POE_INDEX		114
-
-#define PIC_NUM_USB_IRTS		6
-#define PIC_IRT_USB_0_INDEX		115
-#define PIC_IRT_EHCI_0_INDEX		115
-#define PIC_IRT_OHCI_0_INDEX		116
-#define PIC_IRT_OHCI_1_INDEX		117
-#define PIC_IRT_EHCI_1_INDEX		118
-#define PIC_IRT_OHCI_2_INDEX		119
-#define PIC_IRT_OHCI_3_INDEX		120
-#define PIC_IRT_USB_INDEX(num)		((num) + PIC_IRT_USB_0_INDEX)
-/* 115 to 120 */
-#define PIC_IRT_GDX_INDEX		121
-#define PIC_IRT_SEC_INDEX		122
-#define PIC_IRT_RSA_INDEX		123
-
-#define PIC_NUM_COMP_IRTS		4
-#define PIC_IRT_COMP_0_INDEX		124
-#define PIC_IRT_COMP_INDEX(num)		((num) + PIC_IRT_COMP_0_INDEX)
-/* 124 to 127 */
-#define PIC_IRT_GBU_INDEX		128
-#define PIC_IRT_ICC_0_INDEX		129 /* ICC - Inter Chip Coherency */
-#define PIC_IRT_ICC_1_INDEX		130
-#define PIC_IRT_ICC_2_INDEX		131
-#define PIC_IRT_CAM_INDEX		132
-#define PIC_IRT_UART_0_INDEX		133
-#define PIC_IRT_UART_1_INDEX		134
-#define PIC_IRT_I2C_0_INDEX		135
-#define PIC_IRT_I2C_1_INDEX		136
-#define PIC_IRT_SYS_0_INDEX		137
-#define PIC_IRT_SYS_1_INDEX		138
-#define PIC_IRT_JTAG_INDEX		139
-#define PIC_IRT_PIC_INDEX		140
-#define PIC_IRT_NBU_INDEX		141
-#define PIC_IRT_TCU_INDEX		142
-#define PIC_IRT_GCU_INDEX		143 /* GBC - Global Coherency */
-#define PIC_IRT_DMC_0_INDEX		144
-#define PIC_IRT_DMC_1_INDEX		145
-
-#define PIC_NUM_GPIO_IRTS		4
-#define PIC_IRT_GPIO_0_INDEX		146
-#define PIC_IRT_GPIO_INDEX(num)		((num) + PIC_IRT_GPIO_0_INDEX)
-
-/* 146 to 149 */
-#define PIC_IRT_NOR_INDEX		150
-#define PIC_IRT_NAND_INDEX		151
-#define PIC_IRT_SPI_INDEX		152
-#define PIC_IRT_MMC_INDEX		153
 
 #define PIC_CLOCK_TIMER			7
 #define PIC_IRQ_BASE			8
arch/mips/netlogic/xlp/nlm_hal.c +40 -22

83 lines not on this page · raw message

Signature · 1 line
1.7.9.5
author
#7 lore raw

PATCH 5/9 MIPS: Netlogic: Add 32-bit support for XLP

In reply to a message not in the archive

Update asm/netlogic/haldefs.h to extend register access functions nlm_{read,write}_reg64() for 32-bit compilation. When compiled for 32-bit the functions will read 64 IO registers with interrupts disabled.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/netlogic/haldefs.h |   56 ++++++++++++++++++++++++++----
 1 file changed, 50 insertions(+), 6 deletions(-)
arch/mips/include/asm/netlogic/haldefs.h +50 -6
index 419d8ae..61fecb8 100644
@@ -35,14 +35,13 @@
 #ifndef __NLM_HAL_HALDEFS_H__
 #define __NLM_HAL_HALDEFS_H__
 
+#include <linux/irqflags.h>	/* for local_irq_disable */
+
 /*
  * This file contains platform specific memory mapped IO implementation
  * and will provide a way to read 32/64 bit memory mapped registers in
  * all ABIs
  */
-#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
-#error "o32 compile not supported on XLP yet"
-#endif
 /*
  * For o32 compilation, we have to disable interrupts and enable KX bit to
  * access 64 bit addresses or data.

@@ -87,13 +86,40 @@ nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
 	*addr = val;
 }
 
+/*
+ * For o32 compilation, we have to disable interrupts to access 64 bit
+ * registers
+ *
+ * We need to disable interrupts because we save just the lower 32 bits of
+ * registers in  interrupt handling. So if we get hit by an interrupt while
+ * using the upper 32 bits of a register, we lose.
+ */
+
 static inline uint64_t
 nlm_read_reg64(uint64_t base, uint32_t reg)
 {
 	uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
 	volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
-
-	return *ptr;
+	uint64_t val;
+
+	if (sizeof(unsigned long) == 4) {
+		unsigned long flags;
+
+		local_irq_save(flags);
+		__asm__ __volatile__(
+			".set	push"			"\n\t"
+			".set	mips64"			"\n\t"
+			"ld	%L0, %1"		"\n\t"
+			"dsra32	%M0, %L0, 0"		"\n\t"
+			"sll	%L0, %L0, 0"		"\n\t"
+			".set	pop"			"\n"
+			: "=r" (val)
+			: "m" (*ptr));
+		local_irq_restore(flags);
+	} else
+		val = *ptr;
+
+	return val;
 }
 
 static inline void

@@ -102,7 +128,25 @@ nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
 	uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
 	volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
 
-	*ptr = val;
+	if (sizeof(unsigned long) == 4) {
+		unsigned long flags;
+		uint64_t tmp;
+
+		local_irq_save(flags);
+		__asm__ __volatile__(
+			".set	push"			"\n\t"
+			".set	mips64"			"\n\t"
+			"dsll32	%L0, %L0, 0"		"\n\t"
+			"dsrl32	%L0, %L0, 0"		"\n\t"
+			"dsll32	%M0, %M0, 0"		"\n\t"
+			"or	%L0, %L0, %M0"		"\n\t"
+			"sd	%L0, %2"		"\n\t"
+			".set	pop"			"\n"
+			: "=r" (tmp)
+			: "0" (val), "m" (*ptr));
+		local_irq_restore(flags);
+	} else
+		*ptr = val;
 }
 
 /*
Signature · 1 line
1.7.9.5
author
#8 lore raw

PATCH 6/9 MIPS: Netlogic: Remove unused code

In reply to a message not in the archive

Remove unused functions and redundant comments from arch/mips/include/asm/netlogic/haldefs.h

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/netlogic/haldefs.h |   36 ------------------------------
 1 file changed, 36 deletions(-)
arch/mips/include/asm/netlogic/haldefs.h +0 -36
index 61fecb8..79c7ccc 100644
@@ -42,34 +42,6 @@
  * and will provide a way to read 32/64 bit memory mapped registers in
  * all ABIs
  */
-/*
- * For o32 compilation, we have to disable interrupts and enable KX bit to
- * access 64 bit addresses or data.
- *
- * We need to disable interrupts because we save just the lower 32 bits of
- * registers in	 interrupt handling. So if we get hit by an interrupt while
- * using the upper 32 bits of a register, we lose.
- */
-static inline uint32_t nlm_save_flags_kx(void)
-{
-	return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
-}
-
-static inline uint32_t nlm_save_flags_cop2(void)
-{
-	return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
-}
-
-static inline void nlm_restore_flags(uint32_t sr)
-{
-	write_c0_status(sr);
-}
-
-/*
- * The n64 implementations are simple, the o32 implementations when they
- * are added, will have to disable interrupts and enable KX before doing
- * 64 bit ops.
- */
 static inline uint32_t
 nlm_read_reg(uint64_t base, uint32_t reg)
 {

@@ -187,14 +159,6 @@ nlm_pcicfg_base(uint32_t devoffset)
 	return nlm_io_base + devoffset;
 }
 
-static inline uint64_t
-nlm_xkphys_map_pcibar0(uint64_t pcibase)
-{
-	uint64_t paddr;
-
-	paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
-	return (uint64_t)0x9000000000000000 | paddr;
-}
 #elif defined(CONFIG_CPU_XLR)
 
 static inline uint64_t
Signature · 1 line
1.7.9.5
author
#9 lore raw

PATCH 7/9 MIPS: Netlogic: Support for multiple built-in device trees

In reply to a message not in the archive

This enables us to have a default device tree per SoC family to be built into the kernel. The default device tree for XLP3xx has been added as part of this change. Later this can be used to provide support default boards for XLP2xx and XLP9xx SoCs.

Kconfig options are provided for each default device tree so that just the needed ones can be selected to be built into the kernel.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/netlogic/Kconfig         |   17 +++--
 arch/mips/netlogic/dts/Makefile    |    1 +
 arch/mips/netlogic/dts/xlp_evp.dts |    2 +-
 arch/mips/netlogic/dts/xlp_svp.dts |  124 ++++++++++++++++++++++++++++++++++++
 arch/mips/netlogic/xlp/setup.c     |   22 ++++++-
 5 files changed, 158 insertions(+), 8 deletions(-)
 create mode 100644 arch/mips/netlogic/dts/xlp_svp.dts
arch/mips/netlogic/Kconfig +13 -4
index 3c05bf9..e0873a3 100644
@@ -2,13 +2,22 @@ if NLM_XLP_BOARD || NLM_XLR_BOARD
 
 if NLM_XLP_BOARD
 config DT_XLP_EVP
-	bool "Built-in device tree for XLP EVP/SVP boards"
+	bool "Built-in device tree for XLP EVP boards"
 	default y
 	help
-	  Add an FDT blob for XLP EVP and SVP boards into the kernel.
+	  Add an FDT blob for XLP EVP boards into the kernel.
 	  This DTB will be used if the firmware does not pass in a DTB
-          pointer to the kernel.  The corresponding DTS file is at
-          arch/mips/netlogic/dts/xlp_evp.dts
+	  pointer to the kernel.  The corresponding DTS file is at
+	  arch/mips/netlogic/dts/xlp_evp.dts
+
+config DT_XLP_SVP
+	bool "Built-in device tree for XLP SVP boards"
+	default y
+	help
+	  Add an FDT blob for XLP VP boards into the kernel.
+	  This DTB will be used if the firmware does not pass in a DTB
+	  pointer to the kernel.  The corresponding DTS file is at
+	  arch/mips/netlogic/dts/xlp_svp.dts
 
 config NLM_MULTINODE
 	bool "Support for multi-chip boards"
arch/mips/netlogic/dts/Makefile +1 -0
index d117d46..aecb6fa 100644
@@ -1 +1,2 @@
 obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
+obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o
arch/mips/netlogic/dts/xlp_evp.dts +1 -1
index 7628b54..e14f423 100644
@@ -20,7 +20,7 @@
 		#address-cells = <2>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
-		ranges = <0 0  0 0x18000000  0x04000000	  // PCIe CFG
+		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
 			  1 0  0 0x16000000  0x01000000>; // GBU chipselects
 
 		serial0: serial@30000 {
arch/mips/netlogic/dts/xlp_svp.dts new file +124 -0

124 lines not on this page · raw message

arch/mips/netlogic/xlp/setup.c +19 -3
index 4894d62..af31914 100644
@@ -56,7 +56,7 @@ uint64_t nlm_io_base;
 struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
 cpumask_t nlm_cpumask = CPU_MASK_CPU0;
 unsigned int nlm_threads_per_core;
-extern u32 __dtb_start[];
+extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[];
 
 static void nlm_linux_exit(void)
 {

@@ -82,8 +82,24 @@ void __init plat_mem_setup(void)
 	 * 64-bit, so convert pointer.
 	 */
 	fdtp = (void *)(long)fw_arg0;
-	if (!fdtp)
-		fdtp = __dtb_start;
+	if (!fdtp) {
+		switch (current_cpu_data.processor_id & 0xff00) {
+#ifdef CONFIG_DT_XLP_SVP
+		case PRID_IMP_NETLOGIC_XLP3XX:
+			fdtp = __dtb_xlp_svp_begin;
+			break;
+#endif
+#ifdef CONFIG_DT_XLP_EVP
+		case PRID_IMP_NETLOGIC_XLP8XX:
+			fdtp = __dtb_xlp_evp_begin;
+			break;
+#endif
+		default:
+			/* Pick a built-in if any, and hope for the best */
+			fdtp = __dtb_start;
+			break;
+		}
+	}
 	fdtp = phys_to_virt(__pa(fdtp));
 	early_init_devtree(fdtp);
 }
Signature · 1 line
1.7.9.5
author
#10 lore raw

PATCH 8/9 MIPS: Netlogic: Merge platform usb.h to usb-init.c

In reply to a message not in the archive

The definitions are not used anywhere else, and merging it will make adding the new USB definitions for XLPII series easier. While there, cleanup some whitespace in usb-init.c. There is no change to logic due to this commit.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/netlogic/xlp-hal/usb.h |   64 --------------------------
 arch/mips/netlogic/xlp/usb-init.c            |   49 ++++++++++++++------
 2 files changed, 36 insertions(+), 77 deletions(-)
 delete mode 100644 arch/mips/include/asm/netlogic/xlp-hal/usb.h
arch/mips/include/asm/netlogic/xlp-hal/usb.h deleted +0 -64
deleted file mode 100644
index a9cd350..0000000
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_USB_H__
-#define __NLM_HAL_USB_H__
-
-#define USB_CTL_0			0x01
-#define USB_PHY_0			0x0A
-#define USB_PHY_RESET			0x01
-#define USB_PHY_PORT_RESET_0		0x10
-#define USB_PHY_PORT_RESET_1		0x20
-#define USB_CONTROLLER_RESET		0x01
-#define USB_INT_STATUS			0x0E
-#define USB_INT_EN			0x0F
-#define USB_PHY_INTERRUPT_EN		0x01
-#define USB_OHCI_INTERRUPT_EN		0x02
-#define USB_OHCI_INTERRUPT1_EN		0x04
-#define USB_OHCI_INTERRUPT2_EN		0x08
-#define USB_CTRL_INTERRUPT_EN		0x10
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_usb_reg(b, r)			nlm_read_reg(b, r)
-#define nlm_write_usb_reg(b, r, v)		nlm_write_reg(b, r, v)
-#define nlm_get_usb_pcibase(node, inst)		\
-	nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
-#define nlm_get_usb_hcd_base(node, inst)	\
-	nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst))
-#define nlm_get_usb_regbase(node, inst)		\
-	(nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
-
-#endif
-#endif /* __NLM_HAL_USB_H__ */
arch/mips/netlogic/xlp/usb-init.c +36 -13

66 lines not on this page · raw message

Signature · 1 line
1.7.9.5
author
#11 lore raw

PATCH 9/9 MIPS: Netlogic: Fix oprofile compile on XLR uniprocessor

In reply to a message not in the archive

cpu_logical_map is only defined if CONFIG_SMP is set, so use it only when compiling for SMP.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/oprofile/op_model_mipsxx.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/oprofile/op_model_mipsxx.c +1 -1
index 1fd3614..e4b1140 100644
@@ -41,7 +41,7 @@ static int (*save_perf_irq)(void);
  * first hardware thread in the core for setup and init.
  * Skip CPUs with non-zero hardware thread id (4 hwt per core)
  */
-#ifdef CONFIG_CPU_XLR
+#if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
 #define oprofile_skip_cpu(c)	((cpu_logical_map(c) & 0x3) != 0)
 #else
 #define oprofile_skip_cpu(c)	0
Signature · 1 line
1.7.9.5
#12 lore raw

Re: [PATCH 9/9] MIPS: Netlogic: Fix oprofile compile on XLR uniprocessor

Quoted 4 lines · Jayachandran C

cpu_logical_map is only defined if CONFIG_SMP is set, so use it only when compiling for SMP.

Signed-off-by Jayachandran C<[email protected]>

Hi,

You might want to reference the commit that introduced the bug just for the sake of correctness. I recall that this code was only added recently.

John

author
#13 lore raw

PATCH 9/9 MIPS: Netlogic: Fix oprofile compile on XLR uniprocessor

The commit c783390a0ecef08df5c804f8c5f647431a04f502 [MIPS: oprofile:
Support for XLR/XLS processors] causes a compilation failure when oprofile is enabled and SMP is not configured.

arch/mips/oprofile/op_model_mipsxx.c: In function 'mipsxx_cpu_setup':
arch/mips/oprofile/op_model_mipsxx.c:181:2: error: implicit declaration of function 'cpu_logical_map'

To fix this, update oprofile_skip_cpu to not call cpu_logical_map when CONFIG_SMP is not defined.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/oprofile/op_model_mipsxx.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/oprofile/op_model_mipsxx.c +1 -1
index 1fd3614..e4b1140 100644
@@ -41,7 +41,7 @@ static int (*save_perf_irq)(void);
  * first hardware thread in the core for setup and init.
  * Skip CPUs with non-zero hardware thread id (4 hwt per core)
  */
-#ifdef CONFIG_CPU_XLR
+#if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
 #define oprofile_skip_cpu(c)	((cpu_logical_map(c) & 0x3) != 0)
 #else
 #define oprofile_skip_cpu(c)	0
Signature · 1 line
1.7.9.5