Skip to contentSkip to conversation

EXYNOS5: Add GPIO numbering feature

PATCH Superseded Rajeshwari Shinde 4 participants 9 messages Mar 21, 2013 – Apr 2, 2013

Subsystems (3)
Arm (32-bit) GPIO Arm Samsung Exynos

v4 of 5 Superseded Latest is v5 →

lore
Share & tools
lore

Rajeshwari Shinde

author
#0 lore raw

v4 cover EXYNOS5: Add GPIO numbering feature

Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass and supported same for EXYNOS5
Changes in V3:
- New patch added to rename S5P GPIO definitions to S5P_GPIO
- GPIO Table added to calculate the base address
of input gpio bank.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Function and table to support gpio command moved to s5p-gpio driver
- Rebased on latest u-boot-samsung tree

Rajeshwari Shinde (3):
EXYNOS5: Add gpio pin numbering feature
S5P: Rename GPIO definitions
EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5

 arch/arm/cpu/armv7/exynos/pinmux.c       |  206 +++++++---------
 arch/arm/include/asm/arch-exynos/cpu.h   |   10 +-
 arch/arm/include/asm/arch-exynos/gpio.h  |  410 ++++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-s5pc1xx/gpio.h |   26 +-
 board/samsung/goni/goni.c                |    4 +-
 board/samsung/origen/origen.c            |    8 +-
 board/samsung/smdk5250/smdk5250.c        |   24 +--
 board/samsung/smdkc100/smdkc100.c        |    2 +-
 board/samsung/smdkv310/smdkv310.c        |   10 +-
 board/samsung/trats/trats.c              |   16 +-
 board/samsung/universal_c210/universal.c |   36 ++--
 drivers/gpio/s5p_gpio.c                  |  134 +++++++++-
 include/configs/exynos5250-dt.h          |    1 +
 13 files changed, 669 insertions(+), 218 deletions(-)
Signature · 1 line
1.7.4.4
author
#1 lore raw

PATCH v4 1/3 EXYNOS5: Add gpio pin numbering feature

This patch adds support for gpio pin numbering support on EXYNOS5250
To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes in V2:
- none.
Changes in V3:
- none.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Combined previous patch 1 and 2 into single patch.

 arch/arm/cpu/armv7/exynos/pinmux.c      |  148 +++++-------
 arch/arm/include/asm/arch-exynos/cpu.h  |   10 +-
 arch/arm/include/asm/arch-exynos/gpio.h |  376 ++++++++++++++++++++++++++++++-
 board/samsung/smdk5250/smdk5250.c       |   24 +--
 drivers/gpio/s5p_gpio.c                 |   65 ++++++-
 5 files changed, 508 insertions(+), 115 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +60 -88
index bd499b4..02a4d88 100644
@@ -29,89 +29,77 @@
 
 static void exynos5_uart_config(int peripheral)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank;
 	int i, start, count;
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		bank = &gpio1->a0;
-		start = 0;
+		start = EXYNOS5_GPIO_A00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->d0;
-		start = 0;
+		start = EXYNOS5_GPIO_D00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:
-		bank = &gpio1->a1;
-		start = 0;
+		start = EXYNOS5_GPIO_A10;
 		count = 4;
 		break;
 	case PERIPH_ID_UART3:
-		bank = &gpio1->a1;
-		start = 4;
+		start = EXYNOS5_GPIO_A14;
 		count = 2;
 		break;
 	}
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, GPIO_PULL_NONE);
+		gpio_cfg_pin(i, GPIO_FUNC(0x2));
 	}
 }
 
 static int exynos5_mmc_config(int peripheral, int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank, *bank_ext;
-	int i, start = 0, gpio_func = 0;
+	int i, start, start_ext, gpio_func = 0;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		bank = &gpio1->c0;
-		bank_ext = &gpio1->c1;
-		start = 0;
+		start = EXYNOS5_GPIO_C00;
+		start_ext = EXYNOS5_GPIO_C10;
 		gpio_func = GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio1->c2;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C20;
+		start_ext = 0;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio1->c3;
-		bank_ext = &gpio1->c4;
-		start = 3;
+		start = EXYNOS5_GPIO_C30;
+		start_ext = EXYNOS5_GPIO_C43;
 		gpio_func = GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC3:
-		bank = &gpio1->c4;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C40;
+		start_ext = 0;
 		break;
 	}
-	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
 		debug("SDMMC device %d does not support 8bit mode",
 				peripheral);
 		return -1;
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = start; i <= (start + 3); i++) {
-			s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		for (i = start_ext; i <= (start_ext + 3); i++) {
+			gpio_cfg_pin(i, gpio_func);
+			gpio_set_pull(i, GPIO_PULL_UP);
+			gpio_set_drv(i, GPIO_DRV_4X);
 		}
 	}
 	for (i = 0; i < 2; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, GPIO_PULL_NONE);
+		gpio_set_drv(start + i, GPIO_DRV_4X);
 	}
 	for (i = 3; i <= 6; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, GPIO_PULL_UP);
+		gpio_set_drv(start + i, GPIO_DRV_4X);
 	}
 
 	return 0;

@@ -119,8 +107,6 @@ static int exynos5_mmc_config(int peripheral, int flags)
 
 static void exynos5_sromc_config(int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 	int i;
 
 	/*

@@ -138,13 +124,13 @@ static void exynos5_sromc_config(int flags)
 	 * GPY1[2]	SROM_WAIT(2)
 	 * GPY1[3]	EBI_DATA_RDn(2)
 	 */
-	s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
+	gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
 				GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y04, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y05, GPIO_FUNC(2));
 
 	for (i = 0; i < 4; i++)
-		s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, GPIO_FUNC(2));
 
 	/*
 	 * EBI: 8 Addrss Lines

@@ -179,55 +165,52 @@ static void exynos5_sromc_config(int flags)
 	 * GPY6[7]	EBI_DATA[15](2)
 	 */
 	for (i = 0; i < 8; i++) {
-		s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y30 + i, GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y50 + i, GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y60 + i, GPIO_PULL_UP);
 	}
 }
 
 static void exynos5_i2c_config(int peripheral, int flags)
 {
 
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B30, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B31, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B32, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B33, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A06, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A07, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A12, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A13, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A20, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A21, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A23, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B13, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B14, GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B23, GPIO_FUNC(0x3));
 		break;
 	}
 }

@@ -235,53 +218,42 @@ static void exynos5_i2c_config(int peripheral, int flags)
 static void exynos5_i2s_config(int peripheral)
 {
 	int i;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 
 	for (i = 0; i < 5; i++)
-		s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+		gpio_cfg_pin(EXYNOS5_GPIO_B00+i, GPIO_FUNC(0x02));
 }
 
 void exynos5_spi_config(int peripheral)
 {
 	int cfg = 0, pin = 0, i;
-	struct s5p_gpio_bank *bank = NULL;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct exynos5_gpio_part2 *gpio2 =
-		(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		bank = &gpio1->a2;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5_GPIO_A20;
 		break;
 	case PERIPH_ID_SPI1:
-		bank = &gpio1->a2;
 		cfg = GPIO_FUNC(0x2);
-		pin = 4;
+		pin = EXYNOS5_GPIO_A24;
 		break;
 	case PERIPH_ID_SPI2:
-		bank = &gpio1->b1;
 		cfg = GPIO_FUNC(0x5);
-		pin = 1;
+		pin = EXYNOS5_GPIO_B11;
 		break;
 	case PERIPH_ID_SPI3:
-		bank = &gpio2->f1;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5_GPIO_F10;
 		break;
 	case PERIPH_ID_SPI4:
 		for (i = 0; i < 2; i++) {
-			s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
-			s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, GPIO_FUNC(0x4));
 		}
 		break;
 	}
 	if (peripheral != PERIPH_ID_SPI4) {
 		for (i = pin; i < pin + 4; i++)
-			s5p_gpio_cfg_pin(bank, i, cfg);
+			gpio_cfg_pin(i, cfg);
 	}
 }
arch/arm/include/asm/arch-exynos/cpu.h +7 -3
index eb34422..5f08f11 100644
@@ -99,7 +99,7 @@
 /* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING		0x10000
 
-#define EXYNOS5_GPIO_PART4_BASE		0x03860000
+#define EXYNOS5_GPIO_PART8_BASE		0x03860000
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
 #define EXYNOS5_POWER_BASE		0x10040000

@@ -108,9 +108,13 @@
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_DMC_PHY0_BASE		0x10C00000
 #define EXYNOS5_DMC_PHY1_BASE		0x10C10000
-#define EXYNOS5_GPIO_PART3_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE		0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE		0x10D100C0
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_GPIO_PART2_BASE		0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE		0x11400C00
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
 #define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
 #define EXYNOS5_USBPHY_BASE		0x12130000

@@ -123,7 +127,7 @@
 #define EXYNOS5_I2S_BASE		0x12D60000
 #define EXYNOS5_PWMTIMER_BASE		0x12DD0000
 #define EXYNOS5_SPI_ISP_BASE		0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE		0x13400000
+#define EXYNOS5_GPIO_PART4_BASE		0x13400000
 #define EXYNOS5_FIMD_BASE		0x14400000
 #define EXYNOS5_DP_BASE			0x145B0000
arch/arm/include/asm/arch-exynos/gpio.h +369 -7

417 lines not on this page · raw message

board/samsung/smdk5250/smdk5250.c +8 -16
index 217c6df..f58237f 100644
@@ -73,11 +73,8 @@ static void boot_temp_check(void)
 #ifdef CONFIG_USB_EHCI_EXYNOS
 int board_usb_vbus_init(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable VBUS power switch */
-	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+	gpio_direction_output(EXYNOS5_GPIO_X26, 1);
 
 	/* VBUS turn ON time */
 	mdelay(3);

@@ -89,12 +86,9 @@ int board_usb_vbus_init(void)
 #ifdef CONFIG_SOUND_MAX98095
 static void  board_enable_audio_codec(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable MAX98095 Codec */
-	s5p_gpio_direction_output(&gpio1->x1, 7, 1);
-	s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+	gpio_set_pull(EXYNOS5_GPIO_X17, GPIO_PULL_NONE);
 }
 #endif
 

@@ -456,19 +450,17 @@ int board_early_init_f(void)
 #ifdef CONFIG_LCD
 void cfg_lcd_gpio(void)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 
 	/* For Backlight */
-	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_B20, GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 
 	/* LCD power on */
-	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_X15, GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5_GPIO_X07, GPIO_FUNC(0x3));
 }
 
 vidinfo_t panel_info = {
drivers/gpio/s5p_gpio.c +64 -1

86 lines not on this page · raw message

Signature · 1 line
1.7.4.4
#2 lore raw

PATCH v4 1/3 EXYNOS5: Add gpio pin numbering feature

Quoted 28 lines · Rajeshwari Shinde

This patch adds support for gpio pin numbering support on EXYNOS5250
To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes in V2:
- none.
Changes in V3:
- none.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Combined previous patch 1 and 2 into single patch.

 arch/arm/cpu/armv7/exynos/pinmux.c      |  148 +++++-------
 arch/arm/include/asm/arch-exynos/cpu.h  |   10 +-
 arch/arm/include/asm/arch-exynos/gpio.h |  376 ++++++++++++++++++++++++++++++-
 board/samsung/smdk5250/smdk5250.c       |   24 +--
 drivers/gpio/s5p_gpio.c                 |   65 ++++++-
 5 files changed, 508 insertions(+), 115 deletions(-)
drivers/gpio/s5p_gpio.c +0 -0
index 656bf4a..1b882cb 100644

drivers/gpio/s5p_gpio.c line 45

Quoted 10 lines
drivers/gpio/s5p_gpio.c +7 -0
@@ -36,6 +36,27 @@
 #define RATE_MASK(x)		(0x1 << (x + 16))
 #define RATE_SET(x)		(0x1 << (x + 16))
 
+
+struct gpio_info {
+	unsigned int reg_addr;	/* Address of register for this part */
+	unsigned int max_gpio;	/* Maximum GPIO in this part */
+};
+
+#ifdef CONFIG_EXYNOS5

I think, this ifdef is unnecessary.

drivers/gpio/s5p_gpio.c line 46

Quoted 1 line
drivers/gpio/s5p_gpio.c +1 -0
+static const struct gpio_info gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {

maybe it should be exynos5_gpio_data?

Quoted 17 lines
drivers/gpio/s5p_gpio.c +13 -0
+	{ EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
+	{ EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
+	{ EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
+	{ EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
+	{ EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
+	{ EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
+	{ EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
+};
+
+#define HAVE_GENERIC_GPIO
+#endif
+
 void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
 {
 	unsigned int value;

drivers/gpio/s5p_gpio.c void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) · line 166

Quoted 6 lines
drivers/gpio/s5p_gpio.c +2 -1
@@ -141,7 +162,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 
 	writel(value, &bank->drv);
 }
-
+#ifdef HAVE_GENERIC_GPIO
+static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)

please consider exynos4 also.

Quoted 46 lines
drivers/gpio/s5p_gpio.c +31 -0
+{
+	const struct gpio_info *data;
+	unsigned int upto;
+	int i;
+
+	for (i = upto = 0, data = gpio_data; i < EXYNOS5_GPIO_NUM_PARTS;
+			i++, upto = data->max_gpio, data++) {
+		debug("i=%d, upto=%d\n", i, upto);
+		if (gpio < data->max_gpio) {
+			struct s5p_gpio_bank *bank;
+			bank = (struct s5p_gpio_bank *)data->reg_addr;
+			bank += (gpio - upto) / GPIO_PER_BANK;
+			debug("   gpio=%d, bank=%p\n", gpio, bank);
+			return bank;
+		}
+	}
+#ifndef CONFIG_SPL_BUILD
+	assert(gpio < EXYNOS5_GPIO_MAX_PORT);	/* ...which it will not be */
+#endif
+	return NULL;
+}
+#else
 struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 {
 	int bank;

@@ -151,6 +195,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 	bank *= sizeof(struct s5p_gpio_bank);
 	return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
 }
+#endif
 
 int s5p_gpio_get_pin(unsigned gpio)
 {

@@ -196,3 +241,21 @@ int gpio_set_value(unsigned gpio, int value)
 
 	return 0;
 }
+
+void gpio_set_pull(int gpio, int mode)
+{
+	s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
+			s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_set_drv(int gpio, int mode)

drivers/gpio/s5p_gpio.c int gpio_set_value(unsigned gpio, int value) · line 261

Quoted 10 lines
drivers/gpio/s5p_gpio.c +10 -0
+{
+	s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
+			s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_cfg_pin(int gpio, int cfg)
+{
+	s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
+			s5p_gpio_get_pin(gpio), cfg);
+}

Thanks,
Minkyu Kang.

#3 lore raw

PATCH v4 1/3 EXYNOS5: Add gpio pin numbering feature

Hi Minkyu Kang,

Thank you for comments.

Quoted 32 lines · Minkyu Kang
Quoted 31 lines · Rajeshwari Shinde

This patch adds support for gpio pin numbering support on EXYNOS5250
To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes in V2:
- none.
Changes in V3:
- none.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Combined previous patch 1 and 2 into single patch.

 arch/arm/cpu/armv7/exynos/pinmux.c      |  148 +++++-------
 arch/arm/include/asm/arch-exynos/cpu.h  |   10 +-
 arch/arm/include/asm/arch-exynos/gpio.h |  376 ++++++++++++++++++++++++++++++-
 board/samsung/smdk5250/smdk5250.c       |   24 +--
 drivers/gpio/s5p_gpio.c                 |   65 ++++++-
 5 files changed, 508 insertions(+), 115 deletions(-)
drivers/gpio/s5p_gpio.c +0 -0
index 656bf4a..1b882cb 100644
@@ -36,6 +36,27 @@
 #define RATE_MASK(x)         (0x1 << (x + 16))
 #define RATE_SET(x)          (0x1 << (x + 16))
Quoted 9 lines

drivers/gpio/s5p_gpio.c line 45

Quoted 7 lines
drivers/gpio/s5p_gpio.c +7 -0
+
+struct gpio_info {
+     unsigned int reg_addr;  /* Address of register for this part */
+     unsigned int max_gpio;  /* Maximum GPIO in this part */
+};
+
+#ifdef CONFIG_EXYNOS5

I think, this ifdef is unnecessary.

I had put this #ifdef as EXYNOS4 will also have a gpio_data structure.

Quoted 4 lines

drivers/gpio/s5p_gpio.c line 46

Quoted 2 lines
drivers/gpio/s5p_gpio.c +1 -0
+static const struct gpio_info gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {

maybe it should be exynos5_gpio_data?

No kept it as gpio_data as it would b easy to call the same from s5p_gpio_get_bank function and exynos4 will also have a separate structure.

Quoted 19 lines
Quoted 19 lines
drivers/gpio/s5p_gpio.c +13 -0
+     { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
+     { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
+     { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
+     { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
+     { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
+     { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
+     { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
+     { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
+};
+
+#define HAVE_GENERIC_GPIO
+#endif
+
 void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
 {
      unsigned int value;

@@ -141,7 +162,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
Quoted 7 lines

drivers/gpio/s5p_gpio.c void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) · line 166

Quoted 5 lines
drivers/gpio/s5p_gpio.c +2 -1
      writel(value, &bank->drv);
 }
-
+#ifdef HAVE_GENERIC_GPIO
+static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)

please consider exynos4 also.

Yes will update the same for exynos4 and send as soon as possible.

Quoted 64 lines
Quoted 47 lines
drivers/gpio/s5p_gpio.c +31 -0
+{
+     const struct gpio_info *data;
+     unsigned int upto;
+     int i;
+
+     for (i = upto = 0, data = gpio_data; i < EXYNOS5_GPIO_NUM_PARTS;
+                     i++, upto = data->max_gpio, data++) {
+             debug("i=%d, upto=%d\n", i, upto);
+             if (gpio < data->max_gpio) {
+                     struct s5p_gpio_bank *bank;
+                     bank = (struct s5p_gpio_bank *)data->reg_addr;
+                     bank += (gpio - upto) / GPIO_PER_BANK;
+                     debug("   gpio=%d, bank=%p\n", gpio, bank);
+                     return bank;
+             }
+     }
+#ifndef CONFIG_SPL_BUILD
+     assert(gpio < EXYNOS5_GPIO_MAX_PORT);   /* ...which it will not be */
+#endif
+     return NULL;
+}
+#else
 struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 {
      int bank;

@@ -151,6 +195,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
      bank *= sizeof(struct s5p_gpio_bank);
      return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
 }
+#endif
 
 int s5p_gpio_get_pin(unsigned gpio)
 {

@@ -196,3 +241,21 @@ int gpio_set_value(unsigned gpio, int value)
 
      return 0;
 }
+
+void gpio_set_pull(int gpio, int mode)
+{
+     s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
+                     s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_set_drv(int gpio, int mode)

drivers/gpio/s5p_gpio.c int gpio_set_value(unsigned gpio, int value) · line 261

Quoted 10 lines
drivers/gpio/s5p_gpio.c +10 -0
+{
+     s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
+                     s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_cfg_pin(int gpio, int cfg)
+{
+     s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
+                     s5p_gpio_get_pin(gpio), cfg);
+}

Thanks,
Minkyu Kang.
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Signature · 2 lines
Regards,
Rajeshwari Shinde
#4 lore raw

PATCH v4 1/3 EXYNOS5: Add gpio pin numbering feature

Dear Rajeshwari Birje,

Quoted 46 lines · Rajeshwari Birje

Hi Minkyu Kang,

Thank you for comments.

Quoted 32 lines · Minkyu Kang
Quoted 31 lines · Rajeshwari Shinde

This patch adds support for gpio pin numbering support on EXYNOS5250
To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes in V2:
- none.
Changes in V3:
- none.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Combined previous patch 1 and 2 into single patch.

 arch/arm/cpu/armv7/exynos/pinmux.c      |  148 +++++-------
 arch/arm/include/asm/arch-exynos/cpu.h  |   10 +-
 arch/arm/include/asm/arch-exynos/gpio.h |  376 ++++++++++++++++++++++++++++++-
 board/samsung/smdk5250/smdk5250.c       |   24 +--
 drivers/gpio/s5p_gpio.c                 |   65 ++++++-
 5 files changed, 508 insertions(+), 115 deletions(-)
drivers/gpio/s5p_gpio.c +0 -0
index 656bf4a..1b882cb 100644
@@ -36,6 +36,27 @@
 #define RATE_MASK(x)         (0x1 << (x + 16))
 #define RATE_SET(x)          (0x1 << (x + 16))
Quoted 9 lines

drivers/gpio/s5p_gpio.c line 45

Quoted 7 lines
drivers/gpio/s5p_gpio.c +7 -0
+
+struct gpio_info {
+     unsigned int reg_addr;  /* Address of register for this part */
+     unsigned int max_gpio;  /* Maximum GPIO in this part */
+};
+
+#ifdef CONFIG_EXYNOS5

I think, this ifdef is unnecessary.

Quoted 1 line

I had put this #ifdef as EXYNOS4 will also have a gpio_data structure.

Exynos doesn't allow ifdefs on own drivers.
Please don't use it.

Quoted 7 lines
Quoted 4 lines

drivers/gpio/s5p_gpio.c line 46

Quoted 2 lines
drivers/gpio/s5p_gpio.c +1 -0
+static const struct gpio_info gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {

maybe it should be exynos5_gpio_data?

No kept it as gpio_data as it would b easy to call the same from s5p_gpio_get_bank function and exynos4 will also have a separate structure.

I suggest that make two structure exynos5_gpio_data and exynos4_gpio_data, and please remove ifdef.

Quoted 19 lines
Quoted 19 lines
Quoted 19 lines
drivers/gpio/s5p_gpio.c +13 -0
+     { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
+     { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
+     { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
+     { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
+     { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
+     { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
+     { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
+     { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
+};
+
+#define HAVE_GENERIC_GPIO
+#endif
+
 void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
 {
      unsigned int value;

@@ -141,7 +162,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
Quoted 8 lines
Quoted 7 lines

drivers/gpio/s5p_gpio.c void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) · line 166

Quoted 5 lines
drivers/gpio/s5p_gpio.c +2 -1
      writel(value, &bank->drv);
 }
-
+#ifdef HAVE_GENERIC_GPIO
+static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)

please consider exynos4 also.

Yes will update the same for exynos4 and send as soon as possible.

So, please modify this function and resend.

Quoted 7 lines
Quoted 7 lines

drivers/gpio/s5p_gpio.c void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) · line 172

Quoted 7 lines
drivers/gpio/s5p_gpio.c +6 -0
+{
+     const struct gpio_info *data;
+     unsigned int upto;
+     int i;
+
+     for (i = upto = 0, data = gpio_data; i < EXYNOS5_GPIO_NUM_PARTS;

here. EXYNOS5 stuff.

Quoted 49 lines
Quoted 49 lines
Quoted 49 lines
drivers/gpio/s5p_gpio.c +35 -0
+                     i++, upto = data->max_gpio, data++) {
+             debug("i=%d, upto=%d\n", i, upto);
+             if (gpio < data->max_gpio) {
+                     struct s5p_gpio_bank *bank;
+                     bank = (struct s5p_gpio_bank *)data->reg_addr;
+                     bank += (gpio - upto) / GPIO_PER_BANK;
+                     debug("   gpio=%d, bank=%p\n", gpio, bank);
+                     return bank;
+             }
+     }
+#ifndef CONFIG_SPL_BUILD
+     assert(gpio < EXYNOS5_GPIO_MAX_PORT);   /* ...which it will not be */
+#endif
+     return NULL;
+}
+#else
 struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 {
      int bank;

@@ -151,6 +195,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
      bank *= sizeof(struct s5p_gpio_bank);
      return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
 }
+#endif
 
 int s5p_gpio_get_pin(unsigned gpio)
 {

@@ -196,3 +241,21 @@ int gpio_set_value(unsigned gpio, int value)
 
      return 0;
 }
+
+void gpio_set_pull(int gpio, int mode)
+{
+     s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
+                     s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_set_drv(int gpio, int mode)
+{
+     s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
+                     s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_cfg_pin(int gpio, int cfg)
+{
+     s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
+                     s5p_gpio_get_pin(gpio), cfg);
+}
Quoted 9 lines
Quoted 8 lines
Quoted 1 line

Thanks,
Minkyu Kang.
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Thanks,
Minkyu Kang.

author
#5 lore raw

PATCH v4 2/3 S5P: Rename GPIO definitions

In reply to Rajeshwari Shinde

This patch rename GPIO definitions from GPIO_... to S5P_GPIO_... This changes was done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation.

Build tested for s5p_goni, origen, smdk5250, s5pc210_universal, trats, smdkc100, smdkv310 config files.

Signed-off-by Rajeshwari Shinde <[email protected]>

---
Chnages in V3:
- New Patch
Changes in V4:
- None

 arch/arm/cpu/armv7/exynos/pinmux.c       |  134 +++++++++++++++---------------
 arch/arm/include/asm/arch-exynos/gpio.h  |   26 +++---
 arch/arm/include/asm/arch-s5pc1xx/gpio.h |   26 +++---
 board/samsung/goni/goni.c                |    4 +-
 board/samsung/origen/origen.c            |    8 +-
 board/samsung/smdk5250/smdk5250.c        |    8 +-
 board/samsung/smdkc100/smdkc100.c        |    2 +-
 board/samsung/smdkv310/smdkv310.c        |   10 +-
 board/samsung/trats/trats.c              |   16 ++--
 board/samsung/universal_c210/universal.c |   36 ++++----
 drivers/gpio/s5p_gpio.c                  |   20 ++--
 11 files changed, 145 insertions(+), 145 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +67 -67
index 02a4d88..1e7d14c 100644
@@ -50,8 +50,8 @@ static void exynos5_uart_config(int peripheral)
 		break;
 	}
 	for (i = start; i < start + count; i++) {
-		gpio_set_pull(i, GPIO_PULL_NONE);
-		gpio_cfg_pin(i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
 	}
 }
 

@@ -63,7 +63,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	case PERIPH_ID_SDMMC0:
 		start = EXYNOS5_GPIO_C00;
 		start_ext = EXYNOS5_GPIO_C10;
-		gpio_func = GPIO_FUNC(0x2);
+		gpio_func = S5P_GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SDMMC1:
 		start = EXYNOS5_GPIO_C20;

@@ -72,7 +72,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	case PERIPH_ID_SDMMC2:
 		start = EXYNOS5_GPIO_C30;
 		start_ext = EXYNOS5_GPIO_C43;
-		gpio_func = GPIO_FUNC(0x3);
+		gpio_func = S5P_GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC3:
 		start = EXYNOS5_GPIO_C40;

@@ -87,19 +87,19 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = start_ext; i <= (start_ext + 3); i++) {
 			gpio_cfg_pin(i, gpio_func);
-			gpio_set_pull(i, GPIO_PULL_UP);
-			gpio_set_drv(i, GPIO_DRV_4X);
+			gpio_set_pull(i, S5P_GPIO_PULL_UP);
+			gpio_set_drv(i, S5P_GPIO_DRV_4X);
 		}
 	}
 	for (i = 0; i < 2; i++) {
-		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
-		gpio_set_pull(start + i, GPIO_PULL_NONE);
-		gpio_set_drv(start + i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
+		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
 	}
 	for (i = 3; i <= 6; i++) {
-		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
-		gpio_set_pull(start + i, GPIO_PULL_UP);
-		gpio_set_drv(start + i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, S5P_GPIO_PULL_UP);
+		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
 	}
 
 	return 0;

@@ -125,12 +125,12 @@ static void exynos5_sromc_config(int flags)
 	 * GPY1[3]	EBI_DATA_RDn(2)
 	 */
 	gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
-				GPIO_FUNC(2));
-	gpio_cfg_pin(EXYNOS5_GPIO_Y04, GPIO_FUNC(2));
-	gpio_cfg_pin(EXYNOS5_GPIO_Y05, GPIO_FUNC(2));
+				S5P_GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
 
 	for (i = 0; i < 4; i++)
-		gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
 
 	/*
 	 * EBI: 8 Addrss Lines

@@ -165,14 +165,14 @@ static void exynos5_sromc_config(int flags)
 	 * GPY6[7]	EBI_DATA[15](2)
 	 */
 	for (i = 0; i < 8; i++) {
-		gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, GPIO_FUNC(2));
-		gpio_set_pull(EXYNOS5_GPIO_Y30 + i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
 
-		gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, GPIO_FUNC(2));
-		gpio_set_pull(EXYNOS5_GPIO_Y50 + i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
 
-		gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, GPIO_FUNC(2));
-		gpio_set_pull(EXYNOS5_GPIO_Y60 + i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
 	}
 }
 

@@ -181,36 +181,36 @@ static void exynos5_i2c_config(int peripheral, int flags)
 
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		gpio_cfg_pin(EXYNOS5_GPIO_B30, GPIO_FUNC(0x2));
-		gpio_cfg_pin(EXYNOS5_GPIO_B31, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		gpio_cfg_pin(EXYNOS5_GPIO_B32, GPIO_FUNC(0x2));
-		gpio_cfg_pin(EXYNOS5_GPIO_B33, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		gpio_cfg_pin(EXYNOS5_GPIO_A06, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_A07, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		gpio_cfg_pin(EXYNOS5_GPIO_A12, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_A13, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		gpio_cfg_pin(EXYNOS5_GPIO_A20, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_A21, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		gpio_cfg_pin(EXYNOS5_GPIO_A22, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_A23, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		gpio_cfg_pin(EXYNOS5_GPIO_B13, GPIO_FUNC(0x4));
-		gpio_cfg_pin(EXYNOS5_GPIO_B14, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		gpio_cfg_pin(EXYNOS5_GPIO_B22, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_B23, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
 		break;
 	}
 }

@@ -220,7 +220,7 @@ static void exynos5_i2s_config(int peripheral)
 	int i;
 
 	for (i = 0; i < 5; i++)
-		gpio_cfg_pin(EXYNOS5_GPIO_B00+i, GPIO_FUNC(0x02));
+		gpio_cfg_pin(EXYNOS5_GPIO_B00+i, S5P_GPIO_FUNC(0x02));
 }
 
 void exynos5_spi_config(int peripheral)

@@ -229,25 +229,25 @@ void exynos5_spi_config(int peripheral)
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		cfg = GPIO_FUNC(0x2);
+		cfg = S5P_GPIO_FUNC(0x2);
 		pin = EXYNOS5_GPIO_A20;
 		break;
 	case PERIPH_ID_SPI1:
-		cfg = GPIO_FUNC(0x2);
+		cfg = S5P_GPIO_FUNC(0x2);
 		pin = EXYNOS5_GPIO_A24;
 		break;
 	case PERIPH_ID_SPI2:
-		cfg = GPIO_FUNC(0x5);
+		cfg = S5P_GPIO_FUNC(0x5);
 		pin = EXYNOS5_GPIO_B11;
 		break;
 	case PERIPH_ID_SPI3:
-		cfg = GPIO_FUNC(0x2);
+		cfg = S5P_GPIO_FUNC(0x2);
 		pin = EXYNOS5_GPIO_F10;
 		break;
 	case PERIPH_ID_SPI4:
 		for (i = 0; i < 2; i++) {
-			gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, GPIO_FUNC(0x4));
-			gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
 		}
 		break;
 	}

@@ -309,36 +309,36 @@ static void exynos4_i2c_config(int peripheral, int flags)
 
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 0, S5P_GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 1, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 2, S5P_GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 3, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a0, 6, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a0, 7, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a1, 2, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a1, 3, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 2, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 3, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 6, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 7, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+		s5p_gpio_cfg_pin(&gpio1->c1, 3, S5P_GPIO_FUNC(0x4));
+		s5p_gpio_cfg_pin(&gpio1->c1, 4, S5P_GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->d0, 2, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->d0, 3, S5P_GPIO_FUNC(0x3));
 		break;
 	}
 }

@@ -365,15 +365,15 @@ static int exynos4_mmc_config(int peripheral, int flags)
 	for (i = 0; i < 7; i++) {
 		if (i == 2)
 			continue;
-		s5p_gpio_cfg_pin(bank, i,  GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		s5p_gpio_cfg_pin(bank, i,  S5P_GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, S5P_GPIO_PULL_NONE);
+		s5p_gpio_set_drv(bank, i, S5P_GPIO_DRV_4X);
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = 3; i < 7; i++) {
-			s5p_gpio_cfg_pin(bank_ext, i,  GPIO_FUNC(0x3));
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+			s5p_gpio_cfg_pin(bank_ext, i,  S5P_GPIO_FUNC(0x3));
+			s5p_gpio_set_pull(bank_ext, i, S5P_GPIO_PULL_NONE);
+			s5p_gpio_set_drv(bank_ext, i, S5P_GPIO_DRV_4X);
 		}
 	}
arch/arm/include/asm/arch-exynos/gpio.h +13 -13
index e1e59f1..0b8e35e 100644
@@ -676,21 +676,21 @@ int gpio_set_value(unsigned gpio, int value);
 #endif
 
 /* Pin configurations */
-#define GPIO_INPUT	0x0
-#define GPIO_OUTPUT	0x1
-#define GPIO_IRQ	0xf
-#define GPIO_FUNC(x)	(x)
+#define S5P_GPIO_INPUT	0x0
+#define S5P_GPIO_OUTPUT	0x1
+#define S5P_GPIO_IRQ	0xf
+#define S5P_GPIO_FUNC(x)	(x)
 
 /* Pull mode */
-#define GPIO_PULL_NONE	0x0
-#define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x3
+#define S5P_GPIO_PULL_NONE	0x0
+#define S5P_GPIO_PULL_DOWN	0x1
+#define S5P_GPIO_PULL_UP	0x3
 
 /* Drive Strength level */
-#define GPIO_DRV_1X	0x0
-#define GPIO_DRV_3X	0x1
-#define GPIO_DRV_2X	0x2
-#define GPIO_DRV_4X	0x3
-#define GPIO_DRV_FAST	0x0
-#define GPIO_DRV_SLOW	0x1
+#define S5P_GPIO_DRV_1X	0x0
+#define S5P_GPIO_DRV_3X	0x1
+#define S5P_GPIO_DRV_2X	0x2
+#define S5P_GPIO_DRV_4X	0x3
+#define S5P_GPIO_DRV_FAST	0x0
+#define S5P_GPIO_DRV_SLOW	0x1
 #endif
arch/arm/include/asm/arch-s5pc1xx/gpio.h +13 -13
index 00e498d..e0605a2 100644
@@ -155,22 +155,22 @@ static inline unsigned int s5p_gpio_part_max(int nr)
 #endif
 
 /* Pin configurations */
-#define GPIO_INPUT	0x0
-#define GPIO_OUTPUT	0x1
-#define GPIO_IRQ	0xf
-#define GPIO_FUNC(x)	(x)
+#define S5P_GPIO_INPUT	0x0
+#define S5P_GPIO_OUTPUT	0x1
+#define S5P_GPIO_IRQ	0xf
+#define S5P_GPIO_FUNC(x)	(x)
 
 /* Pull mode */
-#define GPIO_PULL_NONE	0x0
-#define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x2
+#define S5P_GPIO_PULL_NONE	0x0
+#define S5P_GPIO_PULL_DOWN	0x1
+#define S5P_GPIO_PULL_UP	0x2
 
 /* Drive Strength level */
-#define GPIO_DRV_1X	0x0
-#define GPIO_DRV_3X	0x1
-#define GPIO_DRV_2X	0x2
-#define GPIO_DRV_4X	0x3
-#define GPIO_DRV_FAST	0x0
-#define GPIO_DRV_SLOW	0x1
+#define S5P_GPIO_DRV_1X	0x0
+#define S5P_GPIO_DRV_3X	0x1
+#define S5P_GPIO_DRV_2X	0x2
+#define S5P_GPIO_DRV_4X	0x3
+#define S5P_GPIO_DRV_FAST	0x0
+#define S5P_GPIO_DRV_SLOW	0x1
 
 #endif
board/samsung/goni/goni.c +2 -2
index ff76963..daa0faa 100644
@@ -102,9 +102,9 @@ int board_mmc_init(bd_t *bis)
 		/* GPG0[0:6] special function 2 */
 		s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
 		/* GPG0[0:6] pull disable */
-		s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&s5pc110_gpio->g0, i, S5P_GPIO_PULL_NONE);
 		/* GPG0[0:6] drv 4x */
-		s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
+		s5p_gpio_set_drv(&s5pc110_gpio->g0, i, S5P_GPIO_DRV_4X);
 	}
 
 	return s5p_mmc_init(0, 4);
board/samsung/origen/origen.c +4 -4
index 638e7b1..1c82ac6 100644
@@ -88,19 +88,19 @@ int board_mmc_init(bd_t *bis)
 	 */
 	for (i = 0; i < 7; i++) {
 		/* GPK2[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio2->k2, i, S5P_GPIO_FUNC(0x2));
 
 		/* GPK2[0:6] drv 4x */
-		s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+		s5p_gpio_set_drv(&gpio2->k2, i, S5P_GPIO_DRV_4X);
 
 		/* GPK2[0:1] pull disable */
 		if (i == 0 || i == 1) {
-			s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+			s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_NONE);
 			continue;
 		}
 
 		/* GPK2[2:6] pull up */
-		s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
+		s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_UP);
 	}
 
 	err = s5p_mmc_init(2, 4);
board/samsung/smdk5250/smdk5250.c +4 -4
index f58237f..61e721b 100644
@@ -88,7 +88,7 @@ static void  board_enable_audio_codec(void)
 {
 	/* Enable MAX98095 Codec */
 	gpio_direction_output(EXYNOS5_GPIO_X17, 1);
-	gpio_set_pull(EXYNOS5_GPIO_X17, GPIO_PULL_NONE);
+	gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
 }
 #endif
 

@@ -452,15 +452,15 @@ void cfg_lcd_gpio(void)
 {
 
 	/* For Backlight */
-	gpio_cfg_pin(EXYNOS5_GPIO_B20, GPIO_OUTPUT);
+	gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
 	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 
 	/* LCD power on */
-	gpio_cfg_pin(EXYNOS5_GPIO_X15, GPIO_OUTPUT);
+	gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
 	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	gpio_cfg_pin(EXYNOS5_GPIO_X07, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
 }
 
 vidinfo_t panel_info = {
board/samsung/smdkc100/smdkc100.c +1 -1
index c41e610..87a8f5a 100644
@@ -41,7 +41,7 @@ static void smc9115_pre_init(void)
 		(struct s5pc100_gpio *)samsung_get_base_gpio();
 
 	/* gpio configuration GPK0CON */
-	s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+	s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
 
 	/* Ethernet needs bus width of 16 bits */
 	smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
board/samsung/smdkv310/smdkv310.c +5 -5
index 81ac8f6..24e8f18 100644
@@ -37,7 +37,7 @@ static void smc9115_pre_init(void)
 	u32 smc_bw_conf, smc_bc_conf;
 
 	/* gpio configuration GPK0CON */
-	s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+	s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
 
 	/* Ethernet needs bus width of 16 bits */
 	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);

@@ -119,19 +119,19 @@ int board_mmc_init(bd_t *bis)
 	 */
 	for (i = 0; i < 7; i++) {
 		/* GPK2[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio2->k2, i, S5P_GPIO_FUNC(0x2));
 
 		/* GPK2[0:6] drv 4x */
-		s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+		s5p_gpio_set_drv(&gpio2->k2, i, S5P_GPIO_DRV_4X);
 
 		/* GPK2[0:1] pull disable */
 		if (i == 0 || i == 1) {
-			s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+			s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_NONE);
 			continue;
 		}
 
 		/* GPK2[2:6] pull up */
-		s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
+		s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_UP);
 	}
 	err = s5p_mmc_init(2, 4);
 	return err;
board/samsung/trats/trats.c +8 -8
index 88d193d..13f4930 100644
@@ -390,8 +390,8 @@ static unsigned int get_hw_revision(void)
 
 	/* hw_rev[3:0] == GPE1[3:0] */
 	for (i = 0; i < 4; i++) {
-		s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
-		s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(&gpio->e1, i, S5P_GPIO_INPUT);
+		s5p_gpio_set_pull(&gpio->e1, i, S5P_GPIO_PULL_NONE);
 	}
 
 	udelay(1);

@@ -430,7 +430,7 @@ int board_mmc_init(bd_t *bis)
 
 	/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 	s5p_gpio_direction_output(&gpio->k0, 2, 1);
-	s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
+	s5p_gpio_set_pull(&gpio->k0, 2, S5P_GPIO_PULL_NONE);
 
 	/*
 	 * MMC device init

@@ -445,7 +445,7 @@ int board_mmc_init(bd_t *bis)
 
 	/* T-flash detect */
 	s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
-	s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
+	s5p_gpio_set_pull(&gpio->x3, 4, S5P_GPIO_PULL_UP);
 
 	/*
 	 * Check the T-flash  detect pin

@@ -522,7 +522,7 @@ static void pmic_reset(void)
 		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 
 	s5p_gpio_direction_output(&gpio->x0, 7, 1);
-	s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
+	s5p_gpio_set_pull(&gpio->x2, 7, S5P_GPIO_PULL_NONE);
 }
 
 static void board_clock_init(void)

@@ -614,12 +614,12 @@ static void board_uart_init(void)
 	 */
 
 	for (i = 0; i < 4; i++) {
-		s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
+		s5p_gpio_set_pull(&gpio1->a1, i, S5P_GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(&gpio1->a1, i, S5P_GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 	}
 
 	/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
-	s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
+	s5p_gpio_set_pull(&gpio2->y4, 7, S5P_GPIO_PULL_UP);
 	s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 }
board/samsung/universal_c210/universal.c +18 -18
index e742707..6ade3f2 100644
@@ -216,7 +216,7 @@ int board_mmc_init(bd_t *bis)
 
 	/* T-flash detect */
 	s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
-	s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
+	s5p_gpio_set_pull(&gpio2->x3, 4, S5P_GPIO_PULL_UP);
 
 	/*
 	 * Check the T-flash  detect pin

@@ -390,35 +390,35 @@ static void lcd_cfg_gpio(void)
 
 	for (i = 0; i < 8; i++) {
 		/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
-		s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
-		s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
-		s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f0, i, S5P_GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f1, i, S5P_GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f2, i, S5P_GPIO_FUNC(2));
 		/* pull-up/down disable */
-		s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
-		s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
-		s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f0, i, S5P_GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f1, i, S5P_GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f2, i, S5P_GPIO_PULL_NONE);
 
 		/* drive strength to max (24bit) */
-		s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
-		s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
-		s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+		s5p_gpio_set_drv(&gpio1->f0, i, S5P_GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f0, i, S5P_GPIO_DRV_SLOW);
+		s5p_gpio_set_drv(&gpio1->f1, i, S5P_GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f1, i, S5P_GPIO_DRV_SLOW);
+		s5p_gpio_set_drv(&gpio1->f2, i, S5P_GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f0, i, S5P_GPIO_DRV_SLOW);
 	}
 
 	for (i = 0; i < f3_end; i++) {
 		/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
-		s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f3, i, S5P_GPIO_FUNC(2));
 		/* pull-up/down disable */
-		s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f3, i, S5P_GPIO_PULL_NONE);
 		/* drive strength to max (24bit) */
-		s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+
+		s5p_gpio_set_rate(&gpio1->f3, i, S5P_GPIO_DRV_SLOW);
 	}
 
 	/* gpio pad configuration for LCD reset. */
-	s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+	s5p_gpio_cfg_pin(&gpio2->y4, 5, S5P_GPIO_OUTPUT);
 
 	spi_init();
 }
drivers/gpio/s5p_gpio.c +10 -10
index 1b882cb..a503137 100644
@@ -71,7 +71,7 @@ void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en)
 {
 	unsigned int value;
 
-	s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
+	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
 
 	value = readl(&bank->dat);
 	value &= ~DAT_MASK(gpio);

@@ -82,7 +82,7 @@ void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en)
 
 void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
 {
-	s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT);
+	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
 }
 
 void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)

@@ -112,8 +112,8 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
 	value &= ~PULL_MASK(gpio);
 
 	switch (mode) {
-	case GPIO_PULL_DOWN:
-	case GPIO_PULL_UP:
+	case S5P_GPIO_PULL_DOWN:
+	case S5P_GPIO_PULL_UP:
 		value |= PULL_MODE(gpio, mode);
 		break;
 	default:

@@ -131,10 +131,10 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
 	value &= ~DRV_MASK(gpio);
 
 	switch (mode) {
-	case GPIO_DRV_1X:
-	case GPIO_DRV_2X:
-	case GPIO_DRV_3X:
-	case GPIO_DRV_4X:
+	case S5P_GPIO_DRV_1X:
+	case S5P_GPIO_DRV_2X:
+	case S5P_GPIO_DRV_3X:
+	case S5P_GPIO_DRV_4X:
 		value |= DRV_SET(gpio, mode);
 		break;
 	default:

@@ -152,8 +152,8 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 	value &= ~RATE_MASK(gpio);
 
 	switch (mode) {
-	case GPIO_DRV_FAST:
-	case GPIO_DRV_SLOW:
+	case S5P_GPIO_DRV_FAST:
+	case S5P_GPIO_DRV_SLOW:
 		value |= RATE_SET(gpio);
 		break;
 	default:
Signature · 1 line
1.7.4.4
author
#6 lore raw

PATCH v4 3/3 EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5

In reply to Rajeshwari Shinde

This patch enables GPIO Command for EXYNOS5. Function has been added to asm/gpio.h to decode the input gpio name to gpio number.
example: gpio set gpa00

Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes in V2:
- New patch
Changes in V3:
- Created a table to know the base address of input bank.
Changes in V4:
- Moved the function name_to_gpio to s5p gpio driver and renamed to s5p_name_to_gpio.

 arch/arm/include/asm/arch-exynos/gpio.h |    8 +++++
 drivers/gpio/s5p_gpio.c                 |   49 +++++++++++++++++++++++++++++++
 include/configs/exynos5250-dt.h         |    1 +
 3 files changed, 58 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-exynos/gpio.h +8 -0
index 0b8e35e..7c0df0b 100644
@@ -668,6 +668,14 @@ static inline unsigned int s5p_gpio_part_max(int nr)
 	return 0;
 }
 
+struct gpio_name_num_table {
+	char bank;
+	unsigned int base;
+};
+
+int s5p_name_to_gpio(const char *name);
+#define name_to_gpio(n) s5p_name_to_gpio(n)
+
 void gpio_cfg_pin(int gpio, int cfg);
 void gpio_set_pull(int gpio, int mode);
 void gpio_set_drv(int gpio, int mode);
drivers/gpio/s5p_gpio.c +49 -0

58 lines not on this page · raw message

include/configs/exynos5250-dt.h +1 -0
index 9fab0fb..5a8a2fb 100644
@@ -115,6 +115,7 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_NET
+#define CONFIG_CMD_GPIO
 
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
Signature · 1 line
1.7.4.4
#7 lore raw

v4 cover EXYNOS5: Add GPIO numbering feature

In reply to Rajeshwari Shinde

Hi Rajeshwari,

Quoted 14 lines · Rajeshwari Shinde

Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass and supported same for EXYNOS5
Changes in V3:
- New patch added to rename S5P GPIO definitions to S5P_GPIO
- GPIO Table added to calculate the base address
of input gpio bank.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Function and table to support gpio command moved to s5p-gpio driver
- Rebased on latest u-boot-samsung tree

Quoted 4 lines

Rajeshwari Shinde (3):
EXYNOS5: Add gpio pin numbering feature
S5P: Rename GPIO definitions
EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5

I tested this on snow, using:

# turn on backlight
i2c dev 4; i2c mw 48 f 1; i2c mw 48 15 1; i2c md 48 0 20
gpio set gpx30
gpio set gpb20

This seems to work fine.

I also tested that the cros_ec keyboard works, using interrupt 182 instead of 174) in the FDT:

ec-interrupt = <&gpio 182 1>;

So it all looks good to me, thank you.

Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>
Quoted 16 lines
 arch/arm/cpu/armv7/exynos/pinmux.c       |  206 +++++++---------
 arch/arm/include/asm/arch-exynos/cpu.h   |   10 +-
 arch/arm/include/asm/arch-exynos/gpio.h  |  410 ++++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-s5pc1xx/gpio.h |   26 +-
 board/samsung/goni/goni.c                |    4 +-
 board/samsung/origen/origen.c            |    8 +-
 board/samsung/smdk5250/smdk5250.c        |   24 +--
 board/samsung/smdkc100/smdkc100.c        |    2 +-
 board/samsung/smdkv310/smdkv310.c        |   10 +-
 board/samsung/trats/trats.c              |   16 +-
 board/samsung/universal_c210/universal.c |   36 ++--
 drivers/gpio/s5p_gpio.c                  |  134 +++++++++-
 include/configs/exynos5250-dt.h          |    1 +
 13 files changed, 669 insertions(+), 218 deletions(-)
Quoted 3 lines

--
1.7.4.4

Regards,
Simon

#8 lore raw

v4 cover EXYNOS5: Add GPIO numbering feature

Hi Minkyu Kang,

Please do review the patch set and do let me know if any comments.

Regards,
Rajeshwari Shinde

Quoted 68 lines · Simon Glass

Hi Rajeshwari,

Quoted 14 lines · Rajeshwari Shinde

Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass and supported same for EXYNOS5
Changes in V3:
- New patch added to rename S5P GPIO definitions to S5P_GPIO
- GPIO Table added to calculate the base address
of input gpio bank.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Function and table to support gpio command moved to s5p-gpio driver
- Rebased on latest u-boot-samsung tree

Quoted 4 lines

Rajeshwari Shinde (3):
EXYNOS5: Add gpio pin numbering feature
S5P: Rename GPIO definitions
EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5

I tested this on snow, using:

# turn on backlight
i2c dev 4; i2c mw 48 f 1; i2c mw 48 15 1; i2c md 48 0 20
gpio set gpx30
gpio set gpb20

This seems to work fine.

I also tested that the cros_ec keyboard works, using interrupt 182 instead of 174) in the FDT:

ec-interrupt = <&gpio 182 1>;

So it all looks good to me, thank you.

Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>
Quoted 16 lines
 arch/arm/cpu/armv7/exynos/pinmux.c       |  206 +++++++---------
 arch/arm/include/asm/arch-exynos/cpu.h   |   10 +-
 arch/arm/include/asm/arch-exynos/gpio.h  |  410 ++++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-s5pc1xx/gpio.h |   26 +-
 board/samsung/goni/goni.c                |    4 +-
 board/samsung/origen/origen.c            |    8 +-
 board/samsung/smdk5250/smdk5250.c        |   24 +--
 board/samsung/smdkc100/smdkc100.c        |    2 +-
 board/samsung/smdkv310/smdkv310.c        |   10 +-
 board/samsung/trats/trats.c              |   16 +-
 board/samsung/universal_c210/universal.c |   36 ++--
 drivers/gpio/s5p_gpio.c                  |  134 +++++++++-
 include/configs/exynos5250-dt.h          |    1 +
 13 files changed, 669 insertions(+), 218 deletions(-)
Quoted 3 lines

--
1.7.4.4

Regards,
Simon
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot