EXYNOS5: Enable DWMMC, add FDT support for DWMMC and

This patch enumerates dwmci and set auto stop command during dwmci initialisation.
EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence modified the fifo size computation to resolve EMMC read write issues.

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header file.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:

	1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of
	the hard coded value (1 << 10).

Changes since V4:
1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1).

Changes since V5:
1)Updated in response to review comments.

Changes since V6:
No change.

Changes since V7:

	1)Updated the function dwmci_setup_bus() to return 0 if (freq == 0). 
	This is to avoid the run time exception "raise:Signal # 8 caught".

 drivers/mmc/dw_mmc.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

drivers/mmc/dw_mmc.c +18 -10

index 4070d4e..963a515 100644
@@ -129,13 +129,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	unsigned int timeout = 100000;
 	u32 retry = 10000;
 	u32 mask, ctrl;
+	ulong start = get_timer(0);
 
 	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
-		if (timeout == 0) {
+		if (get_timer(start) > timeout) {
 			printf("Timeout on data busy\n");
 			return TIMEOUT;
 		}
-		timeout--;
 	}
 
 	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

@@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	if (data)
 		dwmci_prepare_data(host, data);
 
-
 	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 
 	if (data)

@@ -231,9 +230,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 	int timeout = 10000;
 	unsigned long sclk;
 
-	if (freq == host->clock)
+	if ((freq == host->clock) || (freq == 0))
 		return 0;
-
 	/*
 	 * If host->mmc_clk didn't define,
 	 * then assume that host->bus_hz is source clock value.

@@ -314,7 +312,7 @@ static void dwmci_set_ios(struct mmc *mmc)
 static int dwmci_init(struct mmc *mmc)
 {
 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
-	u32 fifo_size, fifoth_val;
+	u32 fifo_size, fifoth_val, ier;
 
 	dwmci_writel(host, DWMCI_PWREN, 1);
 

@@ -323,6 +321,14 @@ static int dwmci_init(struct mmc *mmc)
 		return -1;
 	}
 
+	/* Enumerate at 400KHz */
+	dwmci_setup_bus(host, mmc->f_min);
+
+	/* Set auto stop command */
+	ier = dwmci_readl(host, DWMCI_CTRL);
+	ier |= DWMCI_CTRL_SEND_AS_CCSD;
+	dwmci_writel(host, DWMCI_CTRL, ier);
+
 	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 	dwmci_writel(host, DWMCI_INTMASK, 0);
 

@@ -332,11 +338,13 @@ static int dwmci_init(struct mmc *mmc)
 	dwmci_writel(host, DWMCI_BMOD, 1);
 
 	fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
-	if (host->fifoth_val)
+	fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
+	if (host->fifoth_val) {
 		fifoth_val = host->fifoth_val;
-	else
-		fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
-			TX_WMARK(fifo_size/2);
+	} else {
+		fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+			TX_WMARK(fifo_size / 2);
+	}
 	dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
 
 	dwmci_writel(host, DWMCI_CLKENA, 0);

Hi Amar,

I'm not sure that need to enable the auto-stop command feature. why do you enable this feature? Is there any benefit? Is it related with read/write issue?

Best Regards,
Jaehoon Chung

Quoted 10 lines · Amar

This patch enumerates dwmci and set auto stop command during dwmci initialisation.
EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence modified the fifo size computation to resolve EMMC read write issues.

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header

file.

Quoted 12 lines

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10).

Changes since V4:
1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1).

Quoted 8 lines

Changes since V5:
1)Updated in response to review comments.

Changes since V6:
No change.

Changes since V7:

      1)Updated the function dwmci_setup_bus() to return 0 if (freq ==

0).

drivers/mmc/dw_mmc.c static int dwmci_send_cmd(struct mmc *mmc, struct

Quoted 10 lines

This is to avoid the run time exception "raise:Signal # 8 caught".

 drivers/mmc/dw_mmc.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

drivers/mmc/dw_mmc.c +0 -0

index 4070d4e..963a515 100644
@@ -129,13 +129,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct

mmc_cmd *cmd,

drivers/mmc/dw_mmc.c static int dwmci_send_cmd(struct mmc *mmc, struct

Quoted 16 lines

drivers/mmc/dw_mmc.c +2 -2

      unsigned int timeout = 100000;
      u32 retry = 10000;
      u32 mask, ctrl;
+     ulong start = get_timer(0);
 
      while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
-             if (timeout == 0) {
+             if (get_timer(start) > timeout) {
                      printf("Timeout on data busy\n");
                      return TIMEOUT;
              }
-             timeout--;
      }
 
      dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

@@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct

mmc_cmd *cmd,

drivers/mmc/dw_mmc.c static int dwmci_setup_bus(struct dwmci_host *host,

Quoted 8 lines

drivers/mmc/dw_mmc.c +0 -1

      if (data)
              dwmci_prepare_data(host, data);
 
-
      dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 
      if (data)

@@ -231,9 +230,8 @@ static int dwmci_setup_bus(struct dwmci_host *host,

u32 freq)

Quoted 43 lines

drivers/mmc/dw_mmc.c +12 -4

      int timeout = 10000;
      unsigned long sclk;
 
-     if (freq == host->clock)
+     if ((freq == host->clock) || (freq == 0))
              return 0;
-
      /*
       * If host->mmc_clk didn't define,
       * then assume that host->bus_hz is source clock value.

@@ -314,7 +312,7 @@ static void dwmci_set_ios(struct mmc *mmc)
 static int dwmci_init(struct mmc *mmc)
 {
      struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
-     u32 fifo_size, fifoth_val;
+     u32 fifo_size, fifoth_val, ier;
 
      dwmci_writel(host, DWMCI_PWREN, 1);
 

@@ -323,6 +321,14 @@ static int dwmci_init(struct mmc *mmc)
              return -1;
      }
 
+     /* Enumerate at 400KHz */
+     dwmci_setup_bus(host, mmc->f_min);
+
+     /* Set auto stop command */
+     ier = dwmci_readl(host, DWMCI_CTRL);
+     ier |= DWMCI_CTRL_SEND_AS_CCSD;
+     dwmci_writel(host, DWMCI_CTRL, ier);
+
      dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
      dwmci_writel(host, DWMCI_INTMASK, 0);
 

@@ -332,11 +338,13 @@ static int dwmci_init(struct mmc *mmc)
      dwmci_writel(host, DWMCI_BMOD, 1);
 
      fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
-     if (host->fifoth_val)
+     fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
+     if (host->fifoth_val) {
              fifoth_val = host->fifoth_val;

drivers/mmc/dw_mmc.c static int dwmci_init(struct mmc *mmc) · line 350

Quoted 10 lines

drivers/mmc/dw_mmc.c +4 -3

-     else
-             fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
-                     TX_WMARK(fifo_size/2);
+     } else {
+             fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+                     TX_WMARK(fifo_size / 2);
+     }
      dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
 
      dwmci_writel(host, DWMCI_CLKENA, 0);

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This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 2)Computation of FSYS block clock divisor (pre-ratio) is added.

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int bus_width)" with int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will use exynos_dwmmc_add_port() for every channel enabled in device node.
2)Changed the computation method of mmc clock divisor.
3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within the function.

Changes since V5:
1)Updated in response to review comments and changed the mmc clock value from 50MHz to 52MHz.

Changes since V6:
No change.

Changes since V7:
No change.

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127 ++++++++++++++++++++++++++++---
 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -7

index 8acdf9b..3b147b8 100644
@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x)	((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)	((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-	unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-	return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);

drivers/mmc/exynos_dw_mmc.c +3 -1

index 72a31b7..4238dd9 100644
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>

drivers/mmc/exynos_dw_mmc.c +108 -8

+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-	u32 val;
-	val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-		DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
+	dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-	dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+	return get_mmc_clk(dev_index);
 }
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -	mmc channel number.
+ * regbase -	register base address of mmc channel specified in 'index'.
+ * bus_width -	operating bus width of mmc channel specified in 'index'.
+ * clksel -	value to be written into CLKSEL register in case of FDT.
+ *		NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
 {
 	struct dwmci_host *host = NULL;
+	unsigned int div;
+	unsigned long freq, sclk;
 	host = malloc(sizeof(struct dwmci_host));
 	if (!host) {
 		printf("dwmci_host malloc fail!\n");
 		return 1;
 	}
+	/* request mmc clock vlaue of 52MHz.  */
+	freq = 52000000;
+	sclk = get_mmc_clk(index);
+	div = DIV_ROUND_UP(sclk, freq);
+	/* set the clock divisor for mmc */
+	set_mmc_clk(index, div);
 
-	host->name = EXYNOS_NAME;
+	host->name = "EXYNOS DWMMC";
 	host->ioaddr = (void *)regbase;
 	host->buswidth = bus_width;
+
+	if (clksel) {
+		host->clksel_val = clksel;
+	} else {
+		if (0 == index)
+			host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+		if (2 == index)
+			host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+	}
+
 	host->clksel = exynos_dwmci_clksel;
 	host->dev_index = index;
+	host->mmc_clk = exynos_dwmci_get_clk;
+	/* Add the mmc channel to be registered with mmc core */
+	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+		debug("dwmmc%d registration failed\n", index);
+		return -1;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+	int index, bus_width;
+	int node_list[DWMMC_MAX_CH_NUM];
+	int err = 0, dev_id, flag, count, i;
+	u32 clksel_val, base, timing[3];
+
+	count = fdtdec_find_aliases_for_id(blob, "mmc",
+				COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+				DWMMC_MAX_CH_NUM);
+
+	for (i = 0; i < count; i++) {
+		int node = node_list[i];
+
+		if (node <= 0)
+			continue;
 
-	add_dwmci(host, 52000000, 400000);
+		/* Extract device id for each mmc channel */
+		dev_id = pinmux_decode_periph_id(blob, node);
 
+		/* Get the bus width from the device node */
+		bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+		if (bus_width <= 0) {
+			debug("DWMMC: Can't get bus-width\n");
+			return -1;
+		}
+		if (8 == bus_width)
+			flag = PINMUX_FLAG_8BIT_MODE;
+		else
+			flag = PINMUX_FLAG_NONE;
+
+		/* config pinmux for each mmc channel */
+		err = exynos_pinmux_config(dev_id, flag);
+		if (err) {
+			debug("DWMMC not configured\n");
+			return err;
+		}
+
+		index = dev_id - PERIPH_ID_SDMMC0;
+
+		/* Get the base address from the device node */
+		base = fdtdec_get_addr(blob, node, "reg");
+		if (!base) {
+			debug("DWMMC: Can't get base address\n");
+			return -1;
+		}
+		/* Extract the timing info from the node */
+		err = fdtdec_get_int_array(blob, node, "samsung,timing",
+					timing, 3);
+		if (err) {
+			debug("Can't get sdr-timings for divider\n");
+			return -1;
+		}
+
+		clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+				DWMCI_SET_DRV_CLK(timing[1]) |
+				DWMCI_SET_DIV_RATIO(timing[2]));
+		/* Initialise each mmc channel */
+		err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
+		if (err)
+			debug("dwmmc Channel-%d init failed\n", index);
+	}
 	return 0;
 }
-
+#endif

include/dwmmc.h +3 -0

index c8b1d40..e142f3e 100644
@@ -123,6 +123,8 @@
 #define MSIZE(x)		((x) << 28)
 #define RX_WMARK(x)		((x) << 16)
 #define TX_WMARK(x)		(x)
+#define RX_WMARK_SHIFT		16
+#define RX_WMARK_MASK		(0xfff << RX_WMARK_SHIFT)
 
 #define DWMCI_IDMAC_OWN		(1 << 31)
 #define DWMCI_IDMAC_CH		(1 << 4)

@@ -144,6 +146,7 @@ struct dwmci_host {
 	unsigned int bus_hz;
 	int dev_index;
 	int buswidth;
+	u32 clksel_val;
 	u32 fifoth_val;
 	struct mmc *mmc;
 

Quoted 19 lines · Amar

This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Quoted 7 lines

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 2)Computation of FSYS block clock divisor (pre-ratio) is added.

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int

bus_width)" with

Quoted 3 lines

int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will

use

Quoted 1 line

exynos_dwmmc_add_port() for every channel enabled in

device node.

Quoted 2 lines

2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within

the function.

Quoted 3 lines

Changes since V5:
1)Updated in response to review comments and changed the mmc clock

value

Quoted 10 lines

from 50MHz to 52MHz.

Changes since V6:
No change.

Changes since V7:
No change.

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127

++++++++++++++++++++++++++++---

Review

Quoted 4 lines

 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/dwmmc.h

Quoted 8 lines

index 8acdf9b..3b147b8 100644

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -1

@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)       ((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);

arch/arm/include/asm/arch-exynos/dwmmc.h line 33

Quoted 10 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -6

-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-     unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-     return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel);

Quoted 13 lines

drivers/mmc/exynos_dw_mmc.c +3 -1

index 72a31b7..4238dd9 100644
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>

drivers/mmc/exynos_dw_mmc.c line 34

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +6 -1

 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define      DWMMC_MAX_CH_NUM                4
+#define      DWMMC_MAX_FREQ                  52000000
+#define      DWMMC_MIN_FREQ                  400000
+#define      DWMMC_MMC0_CLKSEL_VAL           0x03030001
+#define      DWMMC_MMC2_CLKSEL_VAL           0x03020001

I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.

Best Regards,
Jaehoon Chung

Quoted 15 lines

drivers/mmc/exynos_dw_mmc.c +7 -4

+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-     u32 val;
-     val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-             DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
+     dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-     dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +7 -1

+{
+     return get_mmc_clk(dev_index);
 }
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -   mmc channel number.
+ * regbase - register base address of mmc channel specified in 'index'.
+ * bus_width -       operating bus width of mmc channel specified in

'index'.

drivers/mmc/exynos_dw_mmc.c

Quoted 4 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+ * clksel -  value to be written into CLKSEL register in case of FDT.
+ *           NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel)

Quoted 55 lines

drivers/mmc/exynos_dw_mmc.c +42 -1

 {
      struct dwmci_host *host = NULL;
+     unsigned int div;
+     unsigned long freq, sclk;
      host = malloc(sizeof(struct dwmci_host));
      if (!host) {
              printf("dwmci_host malloc fail!\n");
              return 1;
      }
+     /* request mmc clock vlaue of 52MHz.  */
+     freq = 52000000;
+     sclk = get_mmc_clk(index);
+     div = DIV_ROUND_UP(sclk, freq);
+     /* set the clock divisor for mmc */
+     set_mmc_clk(index, div);
 
-     host->name = EXYNOS_NAME;
+     host->name = "EXYNOS DWMMC";
      host->ioaddr = (void *)regbase;
      host->buswidth = bus_width;
+
+     if (clksel) {
+             host->clksel_val = clksel;
+     } else {
+             if (0 == index)
+                     host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+             if (2 == index)
+                     host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+     }
+
      host->clksel = exynos_dwmci_clksel;
      host->dev_index = index;
+     host->mmc_clk = exynos_dwmci_get_clk;
+     /* Add the mmc channel to be registered with mmc core */
+     if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+             debug("dwmmc%d registration failed\n", index);
+             return -1;
+     }
+     return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+     int index, bus_width;
+     int node_list[DWMMC_MAX_CH_NUM];
+     int err = 0, dev_id, flag, count, i;
+     u32 clksel_val, base, timing[3];
+
+     count = fdtdec_find_aliases_for_id(blob, "mmc",
+                             COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+                             DWMMC_MAX_CH_NUM);
+
+     for (i = 0; i < count; i++) {
+             int node = node_list[i];

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +7 -1

+
+             if (node <= 0)
+                     continue;
 
-     add_dwmci(host, 52000000, 400000);
+             /* Extract device id for each mmc channel */
+             dev_id = pinmux_decode_periph_id(blob, node);
 
+             /* Get the bus width from the device node */
+             bus_width = fdtdec_get_int(blob, node,

"samsung,bus-width", 0);

Quoted 27 lines

drivers/mmc/exynos_dw_mmc.c +27 -0

+             if (bus_width <= 0) {
+                     debug("DWMMC: Can't get bus-width\n");
+                     return -1;
+             }
+             if (8 == bus_width)
+                     flag = PINMUX_FLAG_8BIT_MODE;
+             else
+                     flag = PINMUX_FLAG_NONE;
+
+             /* config pinmux for each mmc channel */
+             err = exynos_pinmux_config(dev_id, flag);
+             if (err) {
+                     debug("DWMMC not configured\n");
+                     return err;
+             }
+
+             index = dev_id - PERIPH_ID_SDMMC0;
+
+             /* Get the base address from the device node */
+             base = fdtdec_get_addr(blob, node, "reg");
+             if (!base) {
+                     debug("DWMMC: Can't get base address\n");
+                     return -1;
+             }
+             /* Extract the timing info from the node */
+             err = fdtdec_get_int_array(blob, node, "samsung,timing",
+                                     timing, 3);

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +10 -0

+             if (err) {
+                     debug("Can't get sdr-timings for divider\n");
+                     return -1;
+             }
+
+             clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+                             DWMCI_SET_DRV_CLK(timing[1]) |
+                             DWMCI_SET_DIV_RATIO(timing[2]));
+             /* Initialise each mmc channel */
+             err = exynos_dwmci_add_port(index, base, bus_width,

clksel_val);

Quoted 22 lines

drivers/mmc/exynos_dw_mmc.c +4 -1

+             if (err)
+                     debug("dwmmc Channel-%d init failed\n", index);
+     }
      return 0;
 }
-
+#endif

include/dwmmc.h +2 -0

index c8b1d40..e142f3e 100644
@@ -123,6 +123,8 @@
 #define MSIZE(x)             ((x) << 28)
 #define RX_WMARK(x)          ((x) << 16)
 #define TX_WMARK(x)          (x)
+#define RX_WMARK_SHIFT               16
+#define RX_WMARK_MASK                (0xfff << RX_WMARK_SHIFT)
 
 #define DWMCI_IDMAC_OWN              (1 << 31)
 #define DWMCI_IDMAC_CH               (1 << 4)

include/dwmmc.h struct dwmci_host { · line 152

Quoted 7 lines

include/dwmmc.h +1 -0

@@ -144,6 +146,7 @@ struct dwmci_host {
      unsigned int bus_hz;
      int dev_index;
      int buswidth;
+     u32 clksel_val;
      u32 fifoth_val;
      struct mmc *mmc;
 

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Hi Jaehoon,

Please find my responses below.

Thanks & Regards
Amarendra Reddy

Quoted 102 lines · Jaehoon Chung

Quoted 19 lines · Amar

This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Quoted 7 lines

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 2)Computation of FSYS block clock divisor (pre-ratio) is added.

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int

bus_width)" with

Quoted 3 lines

int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will

use

Quoted 1 line

exynos_dwmmc_add_port() for every channel enabled in

device node.

Quoted 2 lines

2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within

the function.

Quoted 3 lines

Changes since V5:
1)Updated in response to review comments and changed the mmc clock

value

Quoted 10 lines

from 50MHz to 52MHz.

Changes since V6:
No change.

Changes since V7:
No change.

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127

++++++++++++++++++++++++++++---

Review

Quoted 4 lines

 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/dwmmc.h

Quoted 8 lines

index 8acdf9b..3b147b8 100644

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -1

@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)       ((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);

arch/arm/include/asm/arch-exynos/dwmmc.h line 33

Quoted 10 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -6

-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-     unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-     return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel);

Quoted 13 lines

drivers/mmc/exynos_dw_mmc.c +3 -1

index 72a31b7..4238dd9 100644
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>

drivers/mmc/exynos_dw_mmc.c line 34

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +6 -1

 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define      DWMMC_MAX_CH_NUM                4
+#define      DWMMC_MAX_FREQ                  52000000
+#define      DWMMC_MIN_FREQ                  400000
+#define      DWMMC_MMC0_CLKSEL_VAL           0x03030001
+#define      DWMMC_MMC2_CLKSEL_VAL           0x03020001

I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.

Quoted 3 lines

Best Regards,
Jaehoon Chung

The above values of CLKSEL work fine for Exynos5 (5250 & 5410) and is tested.

The above CLKSEL values donot hold good for Exynos4 series. Exynos4 has "Mobile Storage Host" with only one port.
But this file 'drivers/mmc/exynos_dw_mmc.c' is specific to Exynos5 series and gets compiled only when CONFIG_EXYNOS_DWMMC is defined.

Quoted 154 lines

Quoted 16 lines

drivers/mmc/exynos_dw_mmc.c +7 -4

+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-     u32 val;
-     val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-             DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
+     dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-     dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +7 -1

+{
+     return get_mmc_clk(dev_index);
 }
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -   mmc channel number.
+ * regbase - register base address of mmc channel specified in 'index'.
+ * bus_width -       operating bus width of mmc channel specified in

'index'.

drivers/mmc/exynos_dw_mmc.c

Quoted 4 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+ * clksel -  value to be written into CLKSEL register in case of FDT.
+ *           NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel)

Quoted 55 lines

drivers/mmc/exynos_dw_mmc.c +42 -1

 {
      struct dwmci_host *host = NULL;
+     unsigned int div;
+     unsigned long freq, sclk;
      host = malloc(sizeof(struct dwmci_host));
      if (!host) {
              printf("dwmci_host malloc fail!\n");
              return 1;
      }
+     /* request mmc clock vlaue of 52MHz.  */
+     freq = 52000000;
+     sclk = get_mmc_clk(index);
+     div = DIV_ROUND_UP(sclk, freq);
+     /* set the clock divisor for mmc */
+     set_mmc_clk(index, div);
 
-     host->name = EXYNOS_NAME;
+     host->name = "EXYNOS DWMMC";
      host->ioaddr = (void *)regbase;
      host->buswidth = bus_width;
+
+     if (clksel) {
+             host->clksel_val = clksel;
+     } else {
+             if (0 == index)
+                     host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+             if (2 == index)
+                     host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+     }
+
      host->clksel = exynos_dwmci_clksel;
      host->dev_index = index;
+     host->mmc_clk = exynos_dwmci_get_clk;
+     /* Add the mmc channel to be registered with mmc core */
+     if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+             debug("dwmmc%d registration failed\n", index);
+             return -1;
+     }
+     return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+     int index, bus_width;
+     int node_list[DWMMC_MAX_CH_NUM];
+     int err = 0, dev_id, flag, count, i;
+     u32 clksel_val, base, timing[3];
+
+     count = fdtdec_find_aliases_for_id(blob, "mmc",
+                             COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+                             DWMMC_MAX_CH_NUM);
+
+     for (i = 0; i < count; i++) {
+             int node = node_list[i];

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +7 -1

+
+             if (node <= 0)
+                     continue;
 
-     add_dwmci(host, 52000000, 400000);
+             /* Extract device id for each mmc channel */
+             dev_id = pinmux_decode_periph_id(blob, node);
 
+             /* Get the bus width from the device node */
+             bus_width = fdtdec_get_int(blob, node,

"samsung,bus-width", 0);

Quoted 27 lines

drivers/mmc/exynos_dw_mmc.c +27 -0

+             if (bus_width <= 0) {
+                     debug("DWMMC: Can't get bus-width\n");
+                     return -1;
+             }
+             if (8 == bus_width)
+                     flag = PINMUX_FLAG_8BIT_MODE;
+             else
+                     flag = PINMUX_FLAG_NONE;
+
+             /* config pinmux for each mmc channel */
+             err = exynos_pinmux_config(dev_id, flag);
+             if (err) {
+                     debug("DWMMC not configured\n");
+                     return err;
+             }
+
+             index = dev_id - PERIPH_ID_SDMMC0;
+
+             /* Get the base address from the device node */
+             base = fdtdec_get_addr(blob, node, "reg");
+             if (!base) {
+                     debug("DWMMC: Can't get base address\n");
+                     return -1;
+             }
+             /* Extract the timing info from the node */
+             err = fdtdec_get_int_array(blob, node, "samsung,timing",
+                                     timing, 3);

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +10 -0

+             if (err) {
+                     debug("Can't get sdr-timings for divider\n");
+                     return -1;
+             }
+
+             clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+                             DWMCI_SET_DRV_CLK(timing[1]) |
+                             DWMCI_SET_DIV_RATIO(timing[2]));
+             /* Initialise each mmc channel */
+             err = exynos_dwmci_add_port(index, base, bus_width,

clksel_val);

Quoted 18 lines

drivers/mmc/exynos_dw_mmc.c +4 -1

+             if (err)
+                     debug("dwmmc Channel-%d init failed\n", index);
+     }
      return 0;
 }
-
+#endif

include/dwmmc.h +2 -0

index c8b1d40..e142f3e 100644
@@ -123,6 +123,8 @@
 #define MSIZE(x)             ((x) << 28)
 #define RX_WMARK(x)          ((x) << 16)
 #define TX_WMARK(x)          (x)
+#define RX_WMARK_SHIFT               16
+#define RX_WMARK_MASK                (0xfff << RX_WMARK_SHIFT)
 

Quoted 17 lines

include/dwmmc.h struct dwmci_host { · line 152

Quoted 11 lines

include/dwmmc.h +1 -0

 #define DWMCI_IDMAC_OWN              (1 << 31)
 #define DWMCI_IDMAC_CH               (1 << 4)

@@ -144,6 +146,7 @@ struct dwmci_host {
      unsigned int bus_hz;
      int dev_index;
      int buswidth;
+     u32 clksel_val;
      u32 fifoth_val;
      struct mmc *mmc;
 

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Quoted 32 lines · Amarendra Reddy

Hi Jaehoon,

Please find my responses below.

Thanks & Regards
Amarendra Reddy

Quoted 23 lines · Jaehoon Chung

Quoted 22 lines · Amar

This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the

purpose.

Quoted 9 lines

Quoted 9 lines

Quoted 4 lines

2)Computation of FSYS block clock divisor (pre-ratio) is added.

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int

bus_width)" with

Quoted 3 lines

int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will

use

Quoted 8 lines

Quoted 8 lines

Quoted 1 line

exynos_dwmmc_add_port() for every channel enabled in

device node.

Quoted 2 lines

2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within

the function.

Quoted 3 lines

Changes since V5:
1)Updated in response to review comments and changed the mmc

clock

Quoted 66 lines

Quoted 62 lines

value

Quoted 10 lines

from 50MHz to 52MHz.

Changes since V6:
No change.

Changes since V7:
No change.

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127

++++++++++++++++++++++++++++---

Review

Quoted 4 lines

 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/dwmmc.h

Quoted 8 lines

index 8acdf9b..3b147b8 100644

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -1

@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)       ((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);

arch/arm/include/asm/arch-exynos/dwmmc.h line 33

Quoted 10 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -6

-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-     unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-     return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel);

Quoted 13 lines

drivers/mmc/exynos_dw_mmc.c +3 -1

index 72a31b7..4238dd9 100644
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>

drivers/mmc/exynos_dw_mmc.c line 34

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +6 -1

 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define      DWMMC_MAX_CH_NUM                4
+#define      DWMMC_MAX_FREQ                  52000000
+#define      DWMMC_MIN_FREQ                  400000
+#define      DWMMC_MMC0_CLKSEL_VAL           0x03030001
+#define      DWMMC_MMC2_CLKSEL_VAL           0x03020001

I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.

Quoted 3 lines

Best Regards,
Jaehoon Chung

Quoted 7 lines

The above values of CLKSEL work fine for Exynos5 (5250 & 5410) and is tested.

The above CLKSEL values donot hold good for Exynos4 series. Exynos4 has "Mobile Storage Host" with only one port.
But this file 'drivers/mmc/exynos_dw_mmc.c' is specific to Exynos5 series and gets compiled only when CONFIG_EXYNOS_DWMMC is defined.

No, driver/mmc/exynos_dw_mmc.c isn't specific to Exynos5 series. We can use this controller at the exynos4.
Then we need to consider how get the clksel value according to SoC.

Best Regards,
Jaehoon Chung

Quoted 11 lines

Quoted 11 lines

drivers/mmc/exynos_dw_mmc.c

Quoted 11 lines

drivers/mmc/exynos_dw_mmc.c +4 -3

+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-     u32 val;
-     val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-             DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) |

DWMCI_SET_DIV_RATIO(0);

Quoted 9 lines

Quoted 9 lines

Quoted 9 lines

drivers/mmc/exynos_dw_mmc.c +5 -1

+     dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-     dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+     return get_mmc_clk(dev_index);
 }
 

Quoted 5 lines

Quoted 5 lines

drivers/mmc/exynos_dw_mmc.c

Quoted 5 lines

drivers/mmc/exynos_dw_mmc.c +4 -1

-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -   mmc channel number.
+ * regbase - register base address of mmc channel specified in

'index'.

Quoted 154 lines

Quoted 129 lines

drivers/mmc/exynos_dw_mmc.c line 53

Quoted 1 line

drivers/mmc/exynos_dw_mmc.c +1 -0

+ * bus_width -       operating bus width of mmc channel specified in

'index'.

drivers/mmc/exynos_dw_mmc.c

Quoted 4 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+ * clksel -  value to be written into CLKSEL register in case of FDT.
+ *           NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel)

Quoted 55 lines

drivers/mmc/exynos_dw_mmc.c +42 -1

 {
      struct dwmci_host *host = NULL;
+     unsigned int div;
+     unsigned long freq, sclk;
      host = malloc(sizeof(struct dwmci_host));
      if (!host) {
              printf("dwmci_host malloc fail!\n");
              return 1;
      }
+     /* request mmc clock vlaue of 52MHz.  */
+     freq = 52000000;
+     sclk = get_mmc_clk(index);
+     div = DIV_ROUND_UP(sclk, freq);
+     /* set the clock divisor for mmc */
+     set_mmc_clk(index, div);
 
-     host->name = EXYNOS_NAME;
+     host->name = "EXYNOS DWMMC";
      host->ioaddr = (void *)regbase;
      host->buswidth = bus_width;
+
+     if (clksel) {
+             host->clksel_val = clksel;
+     } else {
+             if (0 == index)
+                     host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+             if (2 == index)
+                     host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+     }
+
      host->clksel = exynos_dwmci_clksel;
      host->dev_index = index;
+     host->mmc_clk = exynos_dwmci_get_clk;
+     /* Add the mmc channel to be registered with mmc core */
+     if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+             debug("dwmmc%d registration failed\n", index);
+             return -1;
+     }
+     return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+     int index, bus_width;
+     int node_list[DWMMC_MAX_CH_NUM];
+     int err = 0, dev_id, flag, count, i;
+     u32 clksel_val, base, timing[3];
+
+     count = fdtdec_find_aliases_for_id(blob, "mmc",
+                             COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+                             DWMMC_MAX_CH_NUM);
+
+     for (i = 0; i < count; i++) {
+             int node = node_list[i];

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +7 -1

+
+             if (node <= 0)
+                     continue;
 
-     add_dwmci(host, 52000000, 400000);
+             /* Extract device id for each mmc channel */
+             dev_id = pinmux_decode_periph_id(blob, node);
 
+             /* Get the bus width from the device node */
+             bus_width = fdtdec_get_int(blob, node,

"samsung,bus-width", 0);

Quoted 27 lines

drivers/mmc/exynos_dw_mmc.c +27 -0

+             if (bus_width <= 0) {
+                     debug("DWMMC: Can't get bus-width\n");
+                     return -1;
+             }
+             if (8 == bus_width)
+                     flag = PINMUX_FLAG_8BIT_MODE;
+             else
+                     flag = PINMUX_FLAG_NONE;
+
+             /* config pinmux for each mmc channel */
+             err = exynos_pinmux_config(dev_id, flag);
+             if (err) {
+                     debug("DWMMC not configured\n");
+                     return err;
+             }
+
+             index = dev_id - PERIPH_ID_SDMMC0;
+
+             /* Get the base address from the device node */
+             base = fdtdec_get_addr(blob, node, "reg");
+             if (!base) {
+                     debug("DWMMC: Can't get base address\n");
+                     return -1;
+             }
+             /* Extract the timing info from the node */
+             err = fdtdec_get_int_array(blob, node, "samsung,timing",
+                                     timing, 3);

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +10 -0

+             if (err) {
+                     debug("Can't get sdr-timings for divider\n");
+                     return -1;
+             }
+
+             clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+                             DWMCI_SET_DRV_CLK(timing[1]) |
+                             DWMCI_SET_DIV_RATIO(timing[2]));
+             /* Initialise each mmc channel */
+             err = exynos_dwmci_add_port(index, base, bus_width,

clksel_val);

Quoted 18 lines

drivers/mmc/exynos_dw_mmc.c +4 -1

+             if (err)
+                     debug("dwmmc Channel-%d init failed\n", index);
+     }
      return 0;
 }
-
+#endif

include/dwmmc.h +2 -0

index c8b1d40..e142f3e 100644
@@ -123,6 +123,8 @@
 #define MSIZE(x)             ((x) << 28)
 #define RX_WMARK(x)          ((x) << 16)
 #define TX_WMARK(x)          (x)
+#define RX_WMARK_SHIFT               16
+#define RX_WMARK_MASK                (0xfff << RX_WMARK_SHIFT)
 

Quoted 17 lines

include/dwmmc.h struct dwmci_host { · line 152

Quoted 11 lines

include/dwmmc.h +1 -0

 #define DWMCI_IDMAC_OWN              (1 << 31)
 #define DWMCI_IDMAC_CH               (1 << 4)

@@ -144,6 +146,7 @@ struct dwmci_host {
      unsigned int bus_hz;
      int dev_index;
      int buswidth;
+     u32 clksel_val;
      u32 fifoth_val;
      struct mmc *mmc;
 

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Hi Jaehoon,

Please find my response below.

Thanks & Regards
Amarendra Reddy

Quoted 125 lines · Jaehoon Chung

Quoted 32 lines · Amarendra Reddy

Hi Jaehoon,

Please find my responses below.

Thanks & Regards
Amarendra Reddy

Quoted 23 lines · Jaehoon Chung

Quoted 22 lines · Amar

This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the

purpose.

Quoted 9 lines

Quoted 9 lines

Quoted 4 lines

2)Computation of FSYS block clock divisor (pre-ratio) is added.

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int

bus_width)" with

Quoted 3 lines

int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will

use

Quoted 8 lines

Quoted 8 lines

Quoted 1 line

exynos_dwmmc_add_port() for every channel enabled in

device node.

Quoted 2 lines

2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within

the function.

Quoted 3 lines

Changes since V5:
1)Updated in response to review comments and changed the mmc

clock

Quoted 66 lines

Quoted 62 lines

value

Quoted 10 lines

from 50MHz to 52MHz.

Changes since V6:
No change.

Changes since V7:
No change.

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127

++++++++++++++++++++++++++++---

Review

Quoted 4 lines

 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/dwmmc.h

Quoted 8 lines

index 8acdf9b..3b147b8 100644

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -1

@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)       ((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);

arch/arm/include/asm/arch-exynos/dwmmc.h line 33

Quoted 10 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -6

-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-     unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-     return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel);

Quoted 13 lines

drivers/mmc/exynos_dw_mmc.c +3 -1

index 72a31b7..4238dd9 100644
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>

drivers/mmc/exynos_dw_mmc.c line 34

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +6 -1

 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define      DWMMC_MAX_CH_NUM                4
+#define      DWMMC_MAX_FREQ                  52000000
+#define      DWMMC_MIN_FREQ                  400000
+#define      DWMMC_MMC0_CLKSEL_VAL           0x03030001
+#define      DWMMC_MMC2_CLKSEL_VAL           0x03020001

I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.

Quoted 3 lines

Best Regards,
Jaehoon Chung

Quoted 7 lines

The above values of CLKSEL work fine for Exynos5 (5250 & 5410) and is tested.

The above CLKSEL values donot hold good for Exynos4 series. Exynos4 has "Mobile Storage Host" with only one port.
But this file 'drivers/mmc/exynos_dw_mmc.c' is specific to Exynos5 series and gets compiled only when CONFIG_EXYNOS_DWMMC is defined.

Quoted 7 lines

No, driver/mmc/exynos_dw_mmc.c isn't specific to Exynos5 series. We can use this controller at the exynos4.
Then we need to consider how get the clksel value according to SoC.

Best Regards,
Jaehoon Chung

OK. Then I shall add the macro for supporting exynos4 also as shown below

#define EXYNOS4_DWMMC_MMC0_CLKSEL_VAL           0x00000000 (reset value)
#define EXYNOS5_DWMMC_MMC0_CLKSEL_VAL           0x03030001
#define EXYNOS5_DWMMC_MMC2_CLKSEL_VAL           0x03020001

In Exynos4, Mobile Storage Host has only one channel.

The the below function will be updated as below
int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) {
......
......

        if (clksel) {
                host->clksel_val = clksel;
        } else {
                if (0 == index) {
                        if(cpu_is_exynos5())
                                     host->clksel_val =
EXYNOS5_DWMMC_MMC0_CLKSEL_VAL;
                        else
                                     host->clksel_val =

EXYNOS4_DWMMC_MMC0_CLKSEL_VAL; /* Exynos4 MSH has only one channel */

                }

                if (2 == index)
                        host->clksel_val = EXYNOS5_DWMMC_MMC2_CLKSEL_VAL;
        }

........
........
}

Is it OK. Please comment on the above.

Thanks & Regards
Amarendra Reddy

Quoted 21 lines

Quoted 11 lines

Quoted 11 lines

drivers/mmc/exynos_dw_mmc.c

Quoted 11 lines

drivers/mmc/exynos_dw_mmc.c +4 -3

+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-     u32 val;
-     val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-             DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) |

DWMCI_SET_DIV_RATIO(0);

Quoted 9 lines

Quoted 9 lines

Quoted 9 lines

drivers/mmc/exynos_dw_mmc.c +5 -1

+     dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-     dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+     return get_mmc_clk(dev_index);
 }
 

Quoted 162 lines

Quoted 5 lines

Quoted 5 lines

drivers/mmc/exynos_dw_mmc.c

Quoted 5 lines

drivers/mmc/exynos_dw_mmc.c +4 -1

-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -   mmc channel number.
+ * regbase - register base address of mmc channel specified in

'index'.

Quoted 154 lines

Quoted 129 lines

drivers/mmc/exynos_dw_mmc.c line 53

Quoted 1 line

drivers/mmc/exynos_dw_mmc.c +1 -0

+ * bus_width -       operating bus width of mmc channel specified in

'index'.

drivers/mmc/exynos_dw_mmc.c

Quoted 4 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+ * clksel -  value to be written into CLKSEL register in case of FDT.
+ *           NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel)

Quoted 55 lines

drivers/mmc/exynos_dw_mmc.c +42 -1

 {
      struct dwmci_host *host = NULL;
+     unsigned int div;
+     unsigned long freq, sclk;
      host = malloc(sizeof(struct dwmci_host));
      if (!host) {
              printf("dwmci_host malloc fail!\n");
              return 1;
      }
+     /* request mmc clock vlaue of 52MHz.  */
+     freq = 52000000;
+     sclk = get_mmc_clk(index);
+     div = DIV_ROUND_UP(sclk, freq);
+     /* set the clock divisor for mmc */
+     set_mmc_clk(index, div);
 
-     host->name = EXYNOS_NAME;
+     host->name = "EXYNOS DWMMC";
      host->ioaddr = (void *)regbase;
      host->buswidth = bus_width;
+
+     if (clksel) {
+             host->clksel_val = clksel;
+     } else {
+             if (0 == index)
+                     host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+             if (2 == index)
+                     host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+     }
+
      host->clksel = exynos_dwmci_clksel;
      host->dev_index = index;
+     host->mmc_clk = exynos_dwmci_get_clk;
+     /* Add the mmc channel to be registered with mmc core */
+     if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+             debug("dwmmc%d registration failed\n", index);
+             return -1;
+     }
+     return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+     int index, bus_width;
+     int node_list[DWMMC_MAX_CH_NUM];
+     int err = 0, dev_id, flag, count, i;
+     u32 clksel_val, base, timing[3];
+
+     count = fdtdec_find_aliases_for_id(blob, "mmc",
+                             COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+                             DWMMC_MAX_CH_NUM);
+
+     for (i = 0; i < count; i++) {
+             int node = node_list[i];

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +7 -1

+
+             if (node <= 0)
+                     continue;
 
-     add_dwmci(host, 52000000, 400000);
+             /* Extract device id for each mmc channel */
+             dev_id = pinmux_decode_periph_id(blob, node);
 
+             /* Get the bus width from the device node */
+             bus_width = fdtdec_get_int(blob, node,

"samsung,bus-width", 0);

Quoted 27 lines

drivers/mmc/exynos_dw_mmc.c +27 -0

+             if (bus_width <= 0) {
+                     debug("DWMMC: Can't get bus-width\n");
+                     return -1;
+             }
+             if (8 == bus_width)
+                     flag = PINMUX_FLAG_8BIT_MODE;
+             else
+                     flag = PINMUX_FLAG_NONE;
+
+             /* config pinmux for each mmc channel */
+             err = exynos_pinmux_config(dev_id, flag);
+             if (err) {
+                     debug("DWMMC not configured\n");
+                     return err;
+             }
+
+             index = dev_id - PERIPH_ID_SDMMC0;
+
+             /* Get the base address from the device node */
+             base = fdtdec_get_addr(blob, node, "reg");
+             if (!base) {
+                     debug("DWMMC: Can't get base address\n");
+                     return -1;
+             }
+             /* Extract the timing info from the node */
+             err = fdtdec_get_int_array(blob, node, "samsung,timing",
+                                     timing, 3);

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +10 -0

+             if (err) {
+                     debug("Can't get sdr-timings for divider\n");
+                     return -1;
+             }
+
+             clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+                             DWMCI_SET_DRV_CLK(timing[1]) |
+                             DWMCI_SET_DIV_RATIO(timing[2]));
+             /* Initialise each mmc channel */
+             err = exynos_dwmci_add_port(index, base, bus_width,

clksel_val);

Quoted 18 lines

drivers/mmc/exynos_dw_mmc.c +4 -1

+             if (err)
+                     debug("dwmmc Channel-%d init failed\n", index);
+     }
      return 0;
 }
-
+#endif

include/dwmmc.h +2 -0

index c8b1d40..e142f3e 100644
@@ -123,6 +123,8 @@
 #define MSIZE(x)             ((x) << 28)
 #define RX_WMARK(x)          ((x) << 16)
 #define TX_WMARK(x)          (x)
+#define RX_WMARK_SHIFT               16
+#define RX_WMARK_MASK                (0xfff << RX_WMARK_SHIFT)
 

Quoted 17 lines

include/dwmmc.h struct dwmci_host { · line 152

Quoted 11 lines

include/dwmmc.h +1 -0

 #define DWMCI_IDMAC_OWN              (1 << 31)
 #define DWMCI_IDMAC_CH               (1 << 4)

@@ -144,6 +146,7 @@ struct dwmci_host {
      unsigned int bus_hz;
      int dev_index;
      int buswidth;
+     u32 clksel_val;
      u32 fifoth_val;
      struct mmc *mmc;
 

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Quoted 38 lines · Amarendra Reddy

Hi Jaehoon,

Please find my response below.

Thanks & Regards
Amarendra Reddy

Quoted 29 lines · Jaehoon Chung

Quoted 28 lines · Amarendra Reddy

Hi Jaehoon,

Please find my responses below.

Thanks & Regards
Amarendra Reddy

Quoted 19 lines · Jaehoon Chung

Quoted 18 lines · Amar

This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes since V1:
1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.

Changes since V2:
1)Updation of commit message and resubmition of proper patch

set.

Quoted 4 lines

Quoted 4 lines

Quoted 4 lines

Quoted 4 lines

Quoted 4 lines

Changes since V3:
1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the

Quoted 8 lines

Quoted 8 lines

purpose.

Quoted 7 lines

Quoted 7 lines

Quoted 4 lines

2)Computation of FSYS block clock divisor (pre-ratio) is added.

Changes since V4:
1)Replaced "unsigned int exynos_dwmmc_init(int index, int

bus_width)" with

Quoted 2 lines

int exynos_dwmci_add_port(int, u32, inth, u32)
i)exynos_dwmmc_add_port() will be used by non-FDT

boards.

Quoted 1 line

Quoted 1 line

Quoted 1 line

Quoted 1 line

Quoted 1 line

ii)In FDT case, exynos_dwmmc_init(const void *blob)

will

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

use

Quoted 1 line

exynos_dwmmc_add_port() for every channel enabled in

device node.

Quoted 2 lines

2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val'

within

Quoted 29 lines

Quoted 29 lines

Quoted 4 lines

Quoted 4 lines

the function.

Quoted 3 lines

Changes since V5:
1)Updated in response to review comments and changed the mmc

clock

Quoted 24 lines

Quoted 24 lines

value

Quoted 10 lines

from 50MHz to 52MHz.

Changes since V6:
No change.

Changes since V7:
No change.

 arch/arm/include/asm/arch-exynos/dwmmc.h |  11 +--
 drivers/mmc/exynos_dw_mmc.c              | 127

++++++++++++++++++++++++++++---

Review

Quoted 4 lines

 include/dwmmc.h                          |   3 +
 3 files changed, 124 insertions(+), 17 deletions(-)

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/dwmmc.h

Quoted 7 lines

index 8acdf9b..3b147b8 100644

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -0

@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)       ((x) << 24)
 

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

arch/arm/include/asm/arch-exynos/dwmmc.h

Quoted 3 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +0 -3

-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-
-static inline unsigned int exynos_dwmmc_init(int index, int

bus_width)

Quoted 10 lines

Quoted 10 lines

Quoted 10 lines

Quoted 10 lines

arch/arm/include/asm/arch-exynos/dwmmc.h

Quoted 8 lines

arch/arm/include/asm/arch-exynos/dwmmc.h +4 -4

-{
-     unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-     return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel);

Review

Quoted 1 line

(quoted diff) +0 -0

b/drivers/mmc/exynos_dw_mmc.c

Quoted 29 lines

Quoted 29 lines

Quoted 29 lines

Quoted 28 lines

Quoted 12 lines

index 72a31b7..4238dd9 100644

drivers/mmc/exynos_dw_mmc.c +3 -1

@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>

drivers/mmc/exynos_dw_mmc.c line 34

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +6 -1

 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define      DWMMC_MAX_CH_NUM                4
+#define      DWMMC_MAX_FREQ                  52000000
+#define      DWMMC_MIN_FREQ                  400000
+#define      DWMMC_MMC0_CLKSEL_VAL           0x03030001
+#define      DWMMC_MMC2_CLKSEL_VAL           0x03020001

I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.

Best Regards,
Jaehoon Chung

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The above values of CLKSEL work fine for Exynos5 (5250 & 5410) and is tested.

The above CLKSEL values donot hold good for Exynos4 series. Exynos4 has "Mobile Storage Host" with only one port.
But this file 'drivers/mmc/exynos_dw_mmc.c' is specific to Exynos5

series

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and gets compiled only when CONFIG_EXYNOS_DWMMC is defined.

No, driver/mmc/exynos_dw_mmc.c isn't specific to Exynos5 series. We can use this controller at the exynos4.
Then we need to consider how get the clksel value according to SoC.

Best Regards,
Jaehoon Chung

OK. Then I shall add the macro for supporting exynos4 also as shown below

Quoted 8 lines

#define EXYNOS4_DWMMC_MMC0_CLKSEL_VAL           0x00000000 (reset value)
#define EXYNOS5_DWMMC_MMC0_CLKSEL_VAL           0x03030001
#define EXYNOS5_DWMMC_MMC2_CLKSEL_VAL           0x03020001

In Exynos4, Mobile Storage Host has only one channel.

The the below function will be updated as below
int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel)

Quoted 13 lines

{
......
......

        if (clksel) {
                host->clksel_val = clksel;
        } else {
                if (0 == index) {
                        if(cpu_is_exynos5())
                                     host->clksel_val =
EXYNOS5_DWMMC_MMC0_CLKSEL_VAL;
                        else
                                     host->clksel_val =

Quoted 1 line

EXYNOS4_DWMMC_MMC0_CLKSEL_VAL; /* Exynos4 MSH has only one channel

*/

Quoted 10 lines

                }

                if (2 == index)
                        host->clksel_val = EXYNOS5_DWMMC_MMC2_CLKSEL_VAL;
        }

........
........
}

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Is it OK. Please comment on the above.

Well...if you want to set the CLKSEL,i will modify for exynos4 in future. How about this? (I think you're only working for the exynos5)

Ok fine, that will be really good. Hence right now I will not set CLKSEL

Jaehoon Chung

Quoted 25 lines

Thanks & Regards
Amarendra Reddy

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drivers/mmc/exynos_dw_mmc.c

Quoted 11 lines

drivers/mmc/exynos_dw_mmc.c +4 -3

+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-     u32 val;
-     val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-             DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) |

DWMCI_SET_DIV_RATIO(0);

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drivers/mmc/exynos_dw_mmc.c +5 -1

+     dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-     dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+     return get_mmc_clk(dev_index);
 }
 

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drivers/mmc/exynos_dw_mmc.c

Quoted 3 lines

drivers/mmc/exynos_dw_mmc.c +2 -1

-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc

core.

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drivers/mmc/exynos_dw_mmc.c line 52

Quoted 2 lines

drivers/mmc/exynos_dw_mmc.c +2 -0

+ * index -   mmc channel number.
+ * regbase - register base address of mmc channel specified in

'index'.

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drivers/mmc/exynos_dw_mmc.c line 53

Quoted 1 line

drivers/mmc/exynos_dw_mmc.c +1 -0

+ * bus_width -       operating bus width of mmc channel specified in

'index'.

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drivers/mmc/exynos_dw_mmc.c +1 -0

+ * clksel -  value to be written into CLKSEL register in case of

FDT.

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drivers/mmc/exynos_dw_mmc.c

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drivers/mmc/exynos_dw_mmc.c +3 -0

+ *           NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32

clksel)

Quoted 43 lines

drivers/mmc/exynos_dw_mmc.c +30 -1

 {
      struct dwmci_host *host = NULL;
+     unsigned int div;
+     unsigned long freq, sclk;
      host = malloc(sizeof(struct dwmci_host));
      if (!host) {
              printf("dwmci_host malloc fail!\n");
              return 1;
      }
+     /* request mmc clock vlaue of 52MHz.  */
+     freq = 52000000;
+     sclk = get_mmc_clk(index);
+     div = DIV_ROUND_UP(sclk, freq);
+     /* set the clock divisor for mmc */
+     set_mmc_clk(index, div);
 
-     host->name = EXYNOS_NAME;
+     host->name = "EXYNOS DWMMC";
      host->ioaddr = (void *)regbase;
      host->buswidth = bus_width;
+
+     if (clksel) {
+             host->clksel_val = clksel;
+     } else {
+             if (0 == index)
+                     host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+             if (2 == index)
+                     host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+     }
+
      host->clksel = exynos_dwmci_clksel;
      host->dev_index = index;
+     host->mmc_clk = exynos_dwmci_get_clk;
+     /* Add the mmc channel to be registered with mmc core */
+     if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+             debug("dwmmc%d registration failed\n", index);
+             return -1;
+     }
+     return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)

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drivers/mmc/exynos_dw_mmc.c

Quoted 8 lines

drivers/mmc/exynos_dw_mmc.c +8 -0

+{
+     int index, bus_width;
+     int node_list[DWMMC_MAX_CH_NUM];
+     int err = 0, dev_id, flag, count, i;
+     u32 clksel_val, base, timing[3];
+
+     count = fdtdec_find_aliases_for_id(blob, "mmc",
+                             COMPAT_SAMSUNG_EXYNOS5_DWMMC,

node_list,

Quoted 33 lines

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Quoted 4 lines

drivers/mmc/exynos_dw_mmc.c +4 -0

+                             DWMMC_MAX_CH_NUM);
+
+     for (i = 0; i < count; i++) {
+             int node = node_list[i];

drivers/mmc/exynos_dw_mmc.c

Quoted 10 lines

drivers/mmc/exynos_dw_mmc.c +7 -1

+
+             if (node <= 0)
+                     continue;
 
-     add_dwmci(host, 52000000, 400000);
+             /* Extract device id for each mmc channel */
+             dev_id = pinmux_decode_periph_id(blob, node);
 
+             /* Get the bus width from the device node */
+             bus_width = fdtdec_get_int(blob, node,

"samsung,bus-width", 0);

Quoted 18 lines

drivers/mmc/exynos_dw_mmc.c +18 -0

+             if (bus_width <= 0) {
+                     debug("DWMMC: Can't get bus-width\n");
+                     return -1;
+             }
+             if (8 == bus_width)
+                     flag = PINMUX_FLAG_8BIT_MODE;
+             else
+                     flag = PINMUX_FLAG_NONE;
+
+             /* config pinmux for each mmc channel */
+             err = exynos_pinmux_config(dev_id, flag);
+             if (err) {
+                     debug("DWMMC not configured\n");
+                     return err;
+             }
+
+             index = dev_id - PERIPH_ID_SDMMC0;
+

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drivers/mmc/exynos_dw_mmc.c

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drivers/mmc/exynos_dw_mmc.c +8 -0

+             /* Get the base address from the device node */
+             base = fdtdec_get_addr(blob, node, "reg");
+             if (!base) {
+                     debug("DWMMC: Can't get base address\n");
+                     return -1;
+             }
+             /* Extract the timing info from the node */
+             err = fdtdec_get_int_array(blob, node,

"samsung,timing",

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drivers/mmc/exynos_dw_mmc.c

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drivers/mmc/exynos_dw_mmc.c +11 -0

+                                     timing, 3);
+             if (err) {
+                     debug("Can't get sdr-timings for divider\n");
+                     return -1;
+             }
+
+             clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+                             DWMCI_SET_DRV_CLK(timing[1]) |
+                             DWMCI_SET_DIV_RATIO(timing[2]));
+             /* Initialise each mmc channel */
+             err = exynos_dwmci_add_port(index, base, bus_width,

clksel_val);

Quoted 22 lines

drivers/mmc/exynos_dw_mmc.c +4 -1

+             if (err)
+                     debug("dwmmc Channel-%d init failed\n", index);
+     }
      return 0;
 }
-
+#endif

include/dwmmc.h +2 -0

index c8b1d40..e142f3e 100644
@@ -123,6 +123,8 @@
 #define MSIZE(x)             ((x) << 28)
 #define RX_WMARK(x)          ((x) << 16)
 #define TX_WMARK(x)          (x)
+#define RX_WMARK_SHIFT               16
+#define RX_WMARK_MASK                (0xfff << RX_WMARK_SHIFT)
 
 #define DWMCI_IDMAC_OWN              (1 << 31)
 #define DWMCI_IDMAC_CH               (1 << 4)

include/dwmmc.h struct dwmci_host { · line 152

Quoted 7 lines

include/dwmmc.h +1 -0

@@ -144,6 +146,7 @@ struct dwmci_host {
      unsigned int bus_hz;
      int dev_index;
      int buswidth;
+     u32 clksel_val;
      u32 fifoth_val;
      struct mmc *mmc;
 

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Quoted 7 lines

Quoted 5 lines

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk().

Signed-off-by Amar <[email protected]>

Acked-by Simon Glass <[email protected]>

---
Changes since V1:
1)Updated the function exynos5_mmc_set_clk_div() to receive 'device_i'd as input parameter instead of 'index'.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
1)Removed the new API exynos5_mmc_set_clk_div() from clock.c, because existing API set_mmc_clk() can be used to set mmc clock.

Changes since V4:
1)Updated the subject line to reflect the changes present in this patch. 2)Changes of the file arch/arm/include/asm/arch-exynos/clk.h which were present in this patch, have been moved out of this patch.

Changes since V5:
No change.

Changes since V6:
No change.

Changes since V7:
No change.

 arch/arm/cpu/armv7/exynos/clock.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +2 -2

index 223660a..cf3247a 100644
@@ -613,7 +613,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
 		(struct exynos4_clock *)samsung_get_base_clock();
 	unsigned long uclk, sclk;
 	unsigned int sel, ratio, pre_ratio;
-	int shift;
+	int shift = 0;
 
 	sel = readl(&clk->src_fsys);
 	sel = (sel >> (dev_index << 2)) & 0xf;

@@ -662,7 +662,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned long uclk, sclk;
 	unsigned int sel, ratio, pre_ratio;
-	int shift;
+	int shift = 0;
 
 	sel = readl(&clk->src_fsys);
 	sel = (sel >> (dev_index << 2)) & 0xf;

This patch adds commands to access(open/close) and resize boot partitions on EMMC.

Signed-off-by Amar <[email protected]>

---
Changes since V1:
1)Combined the common piece of code between 'open' and 'close' operations.

Changes since V2:
1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
No change.

Changes since V4:
1)Added a new funtion boot_part_access() to combine the common parts of 'mmc open' and 'mmc close' functionalities.
2)Used the generic function "mmc_boot_part_access()" instead of two functions "mmc_boot_open()" and "mmc_boot_close()". By doing so user can specify which boot partition to be accessed (opened / closed).

Changes since V5:
1)Updated minor nits in response to review comments.

Changes since V6:
No change.

Changes since V7:
1)The piece of code involved in open/close and resize of EMMC boot partition has been made conditional and is enabled only if the macro CONFIG_SUPPORT_EMMC_BOOT is defined.

 common/cmd_mmc.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 108 insertions(+), 2 deletions(-)

common/cmd_mmc.c +0 -0

index 8c53a10..c5f60a2 100644

common/cmd_mmc.c +46 -1

+{
+	int err;
+	err = mmc_boot_part_access(mmc, ack, part_num, access);
+
+	if ((err == 0) && (access != 0)) {
+		printf("\t\t\t!!!Notice!!!\n");
+
+		printf("!You must close EMMC boot Partition");
+		printf("after all images are written\n");
+
+		printf("!EMMC boot partition has continuity");
+		printf("at image writing time.\n");
+
+		printf("!So, do not close the boot partition");
+		printf("before all images are written.\n");
+		return 0;
+	} else if ((err == 0) && (access == 0))
+		return 0;
+	else if ((err != 0) && (access != 0)) {
+		printf("EMMC boot partition-%d OPEN Failed.\n", part_num);
+		return 1;
+	} else {
+		printf("EMMC boot partition-%d CLOSE Failed.\n", part_num);
+		return 1;
+	}
+}
+#endif
+
 static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	enum mmc_state state;

@@ -248,8 +278,75 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				curr_device, mmc->part_num);
 
 		return 0;
-	}
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	} else if ((strcmp(argv[1], "open") == 0) ||
+			(strcmp(argv[1], "close") == 0)) {
+		int dev;
+		struct mmc *mmc;
+		u32 ack, part_num, access = 0;
+
+		if (argc == 4) {
+			dev = simple_strtoul(argv[2], NULL, 10);
+			part_num = simple_strtoul(argv[3], NULL, 10);
+		} else {
+			return CMD_RET_USAGE;
+		}
 
+		mmc = find_mmc_device(dev);
+		if (!mmc) {
+			printf("no mmc device at slot %x\n", dev);
+			return 1;
+		}