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Preparatory GIC patches for arm64 support

PATCH Superseded Catalin Marinas 2 participants 7 messages Mar 19, 2013 – Apr 30, 2013

Subsystems (21)
Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape Staging +17 more subsystems
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Catalin Marinas

author
#0 lore raw

v3 cover Preparatory GIC patches for arm64 support

Hi,

That's the third version of the GIC clean-up patches required to support arm64. This is based on 3.9-rc3 and covers new platform code that has been merged into 3.9-rc1.

The patches touch mostly SoC code, drivers/ and arch/arm/ functions moved out into include/linux/.

Russell, what's your preferred way of getting these patches upstream? Ack'ing them and me sending pull request to arm-soc or you would rather merge them via your tree? Either way works for me at the moment since the code is based on mainline.

Thanks.

Catalin Marinas (4):
arm: Move the set_handle_irq and handle_arch_irq declarations to
asm/irq.h
arm: Move chained_irq_(enter|exit) to a generic file
irqchip: gic: Call handle_bad_irq() directly
irqchip: gic: Perform the gic_secondary_init() call via CPU notifier

 arch/arm/include/asm/irq.h                  |  5 +++
 arch/arm/include/asm/mach/irq.h             | 36 --------------------
 arch/arm/mach-at91/gpio.c                   |  3 +-
 arch/arm/mach-exynos/common.c               |  1 +
 arch/arm/mach-exynos/platsmp.c              |  8 -----
 arch/arm/mach-highbank/platsmp.c            |  7 ----
 arch/arm/mach-imx/platsmp.c                 | 12 -------
 arch/arm/mach-msm/platsmp.c                 |  8 -----
 arch/arm/mach-omap2/omap-smp.c              |  7 ----
 arch/arm/mach-prima2/platsmp.c              |  8 -----
 arch/arm/mach-s3c24xx/irq.c                 |  1 +
 arch/arm/mach-shmobile/smp-emev2.c          |  7 ----
 arch/arm/mach-shmobile/smp-r8a7779.c        |  7 ----
 arch/arm/mach-shmobile/smp-sh73a0.c         |  7 ----
 arch/arm/mach-socfpga/platsmp.c             | 12 -------
 arch/arm/mach-spear13xx/platsmp.c           |  8 -----
 arch/arm/mach-tegra/platsmp.c               |  8 -----
 arch/arm/mach-ux500/platsmp.c               |  8 -----
 arch/arm/mach-virt/platsmp.c                |  8 -----
 arch/arm/plat-samsung/irq-vic-timer.c       |  3 +-
 arch/arm/plat-samsung/s5p-irq-gpioint.c     |  3 +-
 arch/arm/plat-versatile/platsmp.c           |  8 -----
 drivers/gpio/gpio-msm-v2.c                  |  3 +-
 drivers/gpio/gpio-mxc.c                     |  2 +-
 drivers/gpio/gpio-omap.c                    |  3 +-
 drivers/gpio/gpio-pl061.c                   |  2 +-
 drivers/gpio/gpio-pxa.c                     |  3 +-
 drivers/gpio/gpio-tegra.c                   |  3 +-
 drivers/irqchip/exynos-combiner.c           |  1 +
 drivers/irqchip/irq-gic.c                   | 32 +++++++++++++-----
 drivers/irqchip/irq-vic.c                   |  2 +-
 drivers/pinctrl/pinctrl-at91.c              |  3 +-
 drivers/pinctrl/pinctrl-exynos.c            |  3 +-
 drivers/pinctrl/pinctrl-nomadik.c           |  2 +-
 drivers/pinctrl/pinctrl-sirf.c              |  2 +-
 drivers/pinctrl/spear/pinctrl-plgpio.c      |  2 +-
 drivers/staging/imx-drm/ipu-v3/ipu-common.c |  2 +-
 include/linux/irqchip/arm-gic.h             |  1 -
 include/linux/irqchip/chained_irq.h         | 52 +++++++++++++++++++++++++++++
 39 files changed, 99 insertions(+), 194 deletions(-)
 create mode 100644 include/linux/irqchip/chained_irq.h
author
#1 lore raw

PATCH v3 1/4 arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h

This patch prepares the removal of <asm/mach/irq.h> include in the GIC and VIC irqchip drivers.

Signed-off-by Catalin Marinas <[email protected]>
Cc Russell King <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
---
 arch/arm/include/asm/irq.h      | 5 +++++
 arch/arm/include/asm/mach/irq.h | 5 -----
 drivers/irqchip/irq-vic.c       | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)
arch/arm/include/asm/irq.h +5 -0
index 35c21c3..53c15de 100644
@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *);
 void handle_IRQ(unsigned int, struct pt_regs *);
 void init_IRQ(void);
 
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+extern void (*handle_arch_irq)(struct pt_regs *);
+extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
+#endif
+
 #endif
 
 #endif
arch/arm/include/asm/mach/irq.h +0 -5
index 18c8830..749d505 100644
@@ -20,11 +20,6 @@ struct seq_file;
 extern void init_FIQ(int);
 extern int show_fiq_list(struct seq_file *, int);
 
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-extern void (*handle_arch_irq)(struct pt_regs *);
-extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
-#endif
-
 /*
  * This is for easy migration, but should be changed in the source
  */
drivers/irqchip/irq-vic.c +1 -1
index 3cf97aa..e38cb00 100644
@@ -33,7 +33,7 @@
 #include <linux/irqchip/arm-vic.h>
 
 #include <asm/exception.h>
-#include <asm/mach/irq.h>
+#include <asm/irq.h>
 
 #include "irqchip.h"
#2 lore raw

PATCH v3 1/4 arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h

Hi Catalin,

Quoted 2 lines · Catalin Marinas

This patch prepares the removal of <asm/mach/irq.h> include in the GIC and VIC irqchip drivers.

[...]

drivers/irqchip/irq-vic.c line 38

Quoted 12 lines
drivers/irqchip/irq-vic.c +1 -1
index 3cf97aa..e38cb00 100644
@@ -33,7 +33,7 @@
 #include <linux/irqchip/arm-vic.h>
 
 #include <asm/exception.h>
-#include <asm/mach/irq.h>
+#include <asm/irq.h>
 
 #include "irqchip.h"

I'm seeing implicit declaration of function issues using your soc-armv8-model branch that seem to be caused by this change.

drivers/irqchip/irq-vic.c: In function ?vic_irqdomain_map?:
drivers/irqchip/irq-vic.c:200:2: error: implicit declaration of function ?irq_set_chip_and_handler? [-Werror=implicit-function-declaration] drivers/irqchip/irq-vic.c:200:43: error: ?handle_level_irq? undeclared (first use in this function)

etc.

Explicitly including linux/irq.h fixed the issue for me.

Regards,
Christopher

Signature · 3 lines
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.
author
#3 lore raw

PATCH v3 2/4 arm: Move chained_irq_(enter|exit) to a generic file

In reply to Catalin Marinas

These functions have been introduced by commit 10a8c383 (irq: introduce entry and exit functions for chained handlers) in asm/mach/irq.h. This patch moves them to linux/irqchip/chained_irq.h so that generic irqchip drivers do not rely on architecture specific header files.

Signed-off-by Catalin Marinas <[email protected]>
Cc Russell King <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
---
 arch/arm/include/asm/mach/irq.h             | 31 -----------------
 arch/arm/mach-at91/gpio.c                   |  3 +-
 arch/arm/mach-exynos/common.c               |  1 +
 arch/arm/mach-s3c24xx/irq.c                 |  1 +
 arch/arm/plat-samsung/irq-vic-timer.c       |  3 +-
 arch/arm/plat-samsung/s5p-irq-gpioint.c     |  3 +-
 drivers/gpio/gpio-msm-v2.c                  |  3 +-
 drivers/gpio/gpio-mxc.c                     |  2 +-
 drivers/gpio/gpio-omap.c                    |  3 +-
 drivers/gpio/gpio-pl061.c                   |  2 +-
 drivers/gpio/gpio-pxa.c                     |  3 +-
 drivers/gpio/gpio-tegra.c                   |  3 +-
 drivers/irqchip/exynos-combiner.c           |  1 +
 drivers/irqchip/irq-gic.c                   |  1 +
 drivers/pinctrl/pinctrl-at91.c              |  3 +-
 drivers/pinctrl/pinctrl-exynos.c            |  3 +-
 drivers/pinctrl/pinctrl-nomadik.c           |  2 +-
 drivers/pinctrl/pinctrl-sirf.c              |  2 +-
 drivers/pinctrl/spear/pinctrl-plgpio.c      |  2 +-
 drivers/staging/imx-drm/ipu-v3/ipu-common.c |  2 +-
 include/linux/irqchip/chained_irq.h         | 52 +++++++++++++++++++++++++++++
 21 files changed, 71 insertions(+), 55 deletions(-)
 create mode 100644 include/linux/irqchip/chained_irq.h
arch/arm/include/asm/mach/irq.h +0 -31
index 749d505..2092ee1 100644
@@ -30,35 +30,4 @@ do {							\
 	raw_spin_unlock(&desc->lock);			\
 } while(0)
 
-#ifndef __ASSEMBLY__
-/*
- * Entry/exit functions for chained handlers where the primary IRQ chip
- * may implement either fasteoi or level-trigger flow control.
- */
-static inline void chained_irq_enter(struct irq_chip *chip,
-				     struct irq_desc *desc)
-{
-	/* FastEOI controllers require no action on entry. */
-	if (chip->irq_eoi)
-		return;
-
-	if (chip->irq_mask_ack) {
-		chip->irq_mask_ack(&desc->irq_data);
-	} else {
-		chip->irq_mask(&desc->irq_data);
-		if (chip->irq_ack)
-			chip->irq_ack(&desc->irq_data);
-	}
-}
-
-static inline void chained_irq_exit(struct irq_chip *chip,
-				    struct irq_desc *desc)
-{
-	if (chip->irq_eoi)
-		chip->irq_eoi(&desc->irq_data);
-	else
-		chip->irq_unmask(&desc->irq_data);
-}
-#endif
-
 #endif
arch/arm/mach-at91/gpio.c +1 -2
index c5d7e1e..a5afcf7 100644
@@ -22,10 +22,9 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/of_address.h>
 
-#include <asm/mach/irq.h>
-
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
arch/arm/mach-exynos/common.c +1 -0
index d63d399..7bc0f9a 100644
@@ -26,6 +26,7 @@
 #include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/chained_irq.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
arch/arm/mach-s3c24xx/irq.c +1 -0
index cb9f5e0..b6fac28 100644
@@ -25,6 +25,7 @@
 #include <linux/ioport.h>
 #include <linux/device.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 
 #include <asm/mach/irq.h>
arch/arm/plat-samsung/irq-vic-timer.c +1 -2
index f980cf3..5d205e7 100644
@@ -16,6 +16,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 
 #include <mach/map.h>

@@ -23,8 +24,6 @@
 #include <plat/irq-vic-timer.h>
 #include <plat/regs-timer.h>
 
-#include <asm/mach/irq.h>
-
 static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_get_chip(irq);
arch/arm/plat-samsung/s5p-irq-gpioint.c +1 -2
index bae5613..fafdb05 100644
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/slab.h>

@@ -22,8 +23,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 
-#include <asm/mach/irq.h>
-
 #define GPIO_BASE(chip)		((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
 
 #define CON_OFFSET		0x700
drivers/gpio/gpio-msm-v2.c +1 -2
index 55a7e77..dd2edde 100644
@@ -23,13 +23,12 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/irq.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 
-#include <asm/mach/irq.h>
-
 #include <mach/msm_gpiomux.h>
 #include <mach/msm_iomap.h>
drivers/gpio/gpio-mxc.c +1 -1
index 7877335..7176743 100644
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>

@@ -32,7 +33,6 @@
 #include <linux/of_device.h>
 #include <linux/module.h>
 #include <asm-generic/bug.h>
-#include <asm/mach/irq.h>
 
 enum mxc_gpio_hwtype {
 	IMX1_GPIO,	/* runs on i.mx1 */
drivers/gpio/gpio-omap.c +1 -2
index 159f5c5..a612ea1 100644
@@ -25,11 +25,10 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
 
-#include <asm/mach/irq.h>
-
 #define OFF_MODE	1
 
 static LIST_HEAD(omap_gpio_list);
drivers/gpio/gpio-pl061.c +1 -1
index b820869..2976336 100644
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/bitops.h>
 #include <linux/workqueue.h>
 #include <linux/gpio.h>

@@ -23,7 +24,6 @@
 #include <linux/amba/pl061.h>
 #include <linux/slab.h>
 #include <linux/pm.h>
-#include <asm/mach/irq.h>
 
 #define GPIODIR 0x400
 #define GPIOIS  0x404
drivers/gpio/gpio-pxa.c +1 -2
index 9cc108d..7523b6d 100644
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_device.h>

@@ -26,8 +27,6 @@
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
-#include <asm/mach/irq.h>
-
 #include <mach/irqs.h>
 
 /*
drivers/gpio/gpio-tegra.c +1 -2
index 414ad91..8e21555 100644
@@ -27,11 +27,10 @@
 #include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pm.h>
 
-#include <asm/mach/irq.h>
-
 #define GPIO_BANK(x)		((x) >> 5)
 #define GPIO_PORT(x)		(((x) >> 3) & 0x3)
 #define GPIO_BIT(x)		((x) & 0x7)
drivers/irqchip/exynos-combiner.c +1 -0
index 04d86a9..6a52013 100644
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <asm/mach/irq.h>
drivers/irqchip/irq-gic.c +1 -0
index a32e0d5..0b1c0af 100644
@@ -38,6 +38,7 @@
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
 #include <linux/slab.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/irqchip/arm-gic.h>
 
 #include <asm/irq.h>
drivers/pinctrl/pinctrl-at91.c +1 -2
index 75933a6..5cbadc9 100644
@@ -18,6 +18,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/pinctrl/machine.h>

@@ -27,8 +28,6 @@
 /* Since we request GPIOs from ourself */
 #include <linux/pinctrl/consumer.h>
 
-#include <asm/mach/irq.h>
-
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
drivers/pinctrl/pinctrl-exynos.c +1 -2
index 538b9dd..7265e55 100644
@@ -23,13 +23,12 @@
 #include <linux/interrupt.h>
 #include <linux/irqdomain.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/of_irq.h>
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/err.h>
 
-#include <asm/mach/irq.h>
-
 #include "pinctrl-samsung.h"
 #include "pinctrl-exynos.h"
drivers/pinctrl/pinctrl-nomadik.c +1 -1
index 36d2029..93eba97 100644
@@ -23,6 +23,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/slab.h>
 #include <linux/of_device.h>
 #include <linux/of_address.h>

@@ -33,7 +34,6 @@
 /* Since we request GPIOs from ourself */
 #include <linux/pinctrl/consumer.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
-#include <asm/mach/irq.h>
 #include "pinctrl-nomadik.h"
 #include "core.h"
drivers/pinctrl/pinctrl-sirf.c +1 -1
index d02498b..ab26b4b 100644
@@ -14,6 +14,7 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/consumer.h>

@@ -25,7 +26,6 @@
 #include <linux/bitops.h>
 #include <linux/gpio.h>
 #include <linux/of_gpio.h>
-#include <asm/mach/irq.h>
 
 #define DRIVER_NAME "pinmux-sirf"
drivers/pinctrl/spear/pinctrl-plgpio.c +1 -1
index 295b349..a4908ec 100644
@@ -15,12 +15,12 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/module.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/spinlock.h>
-#include <asm/mach/irq.h>
 
 #define MAX_GPIO_PER_REG		32
 #define PIN_OFFSET(pin)			(pin % MAX_GPIO_PER_REG)
drivers/staging/imx-drm/ipu-v3/ipu-common.c +1 -1
index 366f259..6efe4e1 100644
@@ -25,8 +25,8 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/of_device.h>
-#include <asm/mach/irq.h>
 
 #include "imx-ipu-v3.h"
 #include "ipu-prv.h"
include/linux/irqchip/chained_irq.h new file +52 -0

52 lines not on this page · raw message

author
#4 lore raw

PATCH v3 3/4 irqchip: gic: Call handle_bad_irq() directly

In reply to Catalin Marinas

Previously, the gic_handle_cascade_irq() function was calling the ARM-specific do_bad_IRQ() function which calls handle_bad_irq() after acquiring the desk->lock. Locking the cascaded IRQ desc is not needed for error reporting, so just call handle_bad_irq() directly.

Signed-off-by Catalin Marinas <[email protected]>
Cc Russell King <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
---
 drivers/irqchip/irq-gic.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/irqchip/irq-gic.c +1 -2
index 0b1c0af..974f77c 100644
@@ -44,7 +44,6 @@
 #include <asm/irq.h>
 #include <asm/exception.h>
 #include <asm/smp_plat.h>
-#include <asm/mach/irq.h>
 
 #include "irqchip.h"
 

@@ -324,7 +323,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 
 	cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
 	if (unlikely(gic_irq < 32 || gic_irq > 1020))
-		do_bad_IRQ(cascade_irq, desc);
+		handle_bad_irq(cascade_irq, desc);
 	else
 		generic_handle_irq(cascade_irq);
author
#5 lore raw

PATCH v3 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier

In reply to Catalin Marinas

All the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.

Signed-off-by Catalin Marinas <[email protected]>
Acked-by Stephen Warren <[email protected]>
Acked-by Viresh Kumar <[email protected]>
Acked-by Santosh Shilimkar <[email protected]>
Acked-by Rob Herring <[email protected]>
Acked-by Simon Horman <[email protected]>
Tested-by Simon Horman <[email protected]>
Acked-by Srinidhi Kasagar <[email protected]>
Tested-by Dinh Nguyen <[email protected]>
Acked-by Nicolas Pitre <[email protected]>
Cc Russell King <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Kukjin Kim <[email protected]>
Cc Sascha Hauer <[email protected]>
Cc David Brown <[email protected]>
Cc Bryan Huntsman <[email protected]>
Cc Tony Lindgren <[email protected]>
Cc Magnus Damm <[email protected]>
Cc Shiraz Hashim <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Will Deacon <[email protected]>
Cc Kukjin Kim <[email protected]>
Cc Barry Song <[email protected]>
---
 arch/arm/mach-exynos/platsmp.c       |  8 --------
 arch/arm/mach-highbank/platsmp.c     |  7 -------
 arch/arm/mach-imx/platsmp.c          | 12 ------------
 arch/arm/mach-msm/platsmp.c          |  8 --------
 arch/arm/mach-omap2/omap-smp.c       |  7 -------
 arch/arm/mach-prima2/platsmp.c       |  8 --------
 arch/arm/mach-shmobile/smp-emev2.c   |  7 -------
 arch/arm/mach-shmobile/smp-r8a7779.c |  7 -------
 arch/arm/mach-shmobile/smp-sh73a0.c  |  7 -------
 arch/arm/mach-socfpga/platsmp.c      | 12 ------------
 arch/arm/mach-spear13xx/platsmp.c    |  8 --------
 arch/arm/mach-tegra/platsmp.c        |  8 --------
 arch/arm/mach-ux500/platsmp.c        |  8 --------
 arch/arm/mach-virt/platsmp.c         |  8 --------
 arch/arm/plat-versatile/platsmp.c    |  8 --------
 drivers/irqchip/irq-gic.c            | 28 +++++++++++++++++++++-------
 include/linux/irqchip/arm-gic.h      |  1 -
 17 files changed, 21 insertions(+), 131 deletions(-)
arch/arm/mach-exynos/platsmp.c +0 -8
index 60f7c5b..95e04bd 100644
@@ -20,7 +20,6 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>

@@ -76,13 +75,6 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit exynos_secondary_init(unsigned int cpu)
 {
 	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
arch/arm/mach-highbank/platsmp.c +0 -7
index 8797a70..a984573 100644
@@ -17,7 +17,6 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/smp_scu.h>
 

@@ -25,11 +24,6 @@
 
 extern void secondary_startup(void);
 
-static void __cpuinit highbank_secondary_init(unsigned int cpu)
-{
-	gic_secondary_init(0);
-}
-
 static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	highbank_set_cpu_jump(cpu, secondary_startup);

@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
 struct smp_operations highbank_smp_ops __initdata = {
 	.smp_init_cpus		= highbank_smp_init_cpus,
 	.smp_prepare_cpus	= highbank_smp_prepare_cpus,
-	.smp_secondary_init	= highbank_secondary_init,
 	.smp_boot_secondary	= highbank_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_die		= highbank_cpu_die,
arch/arm/mach-imx/platsmp.c +0 -12
index 7c0b03f..77e9a25 100644
@@ -12,7 +12,6 @@
 
 #include <linux/init.h>
 #include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>

@@ -52,16 +51,6 @@ void imx_scu_standby_enable(void)
 	writel_relaxed(val, scu_base);
 }
 
-static void __cpuinit imx_secondary_init(unsigned int cpu)
-{
-	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-}
-
 static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	imx_set_cpu_jump(cpu, v7_secondary_startup);

@@ -96,7 +85,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
 struct smp_operations  imx_smp_ops __initdata = {
 	.smp_init_cpus		= imx_smp_init_cpus,
 	.smp_prepare_cpus	= imx_smp_prepare_cpus,
-	.smp_secondary_init	= imx_secondary_init,
 	.smp_boot_secondary	= imx_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_die		= imx_cpu_die,
arch/arm/mach-msm/platsmp.c +0 -8
index 42932865..00cdb0a 100644
@@ -15,7 +15,6 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>

@@ -42,13 +41,6 @@ static inline int get_core_count(void)
 static void __cpuinit msm_secondary_init(unsigned int cpu)
 {
 	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
arch/arm/mach-omap2/omap-smp.c +0 -7
index d972721..e7a4497 100644
@@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
 							4, 0, 0, 0, 0, 0);
 
 	/*
-	 * If any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
arch/arm/mach-prima2/platsmp.c +0 -8
index 4b78831..c7c92e7 100644
@@ -11,7 +11,6 @@
 #include <linux/delay.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/smp_plat.h>

@@ -49,13 +48,6 @@ void __init sirfsoc_map_scu(void)
 static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
 {
 	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
arch/arm/mach-shmobile/smp-emev2.c +0 -7
index 953eb1f..384e27d 100644
@@ -23,7 +23,6 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/emev2.h>
 #include <asm/smp_plat.h>

@@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
 }
 
 
-static void __cpuinit emev2_secondary_init(unsigned int cpu)
-{
-	gic_secondary_init(0);
-}
-
 static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	cpu = cpu_logical_map(cpu);

@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)
 struct smp_operations emev2_smp_ops __initdata = {
 	.smp_init_cpus		= emev2_smp_init_cpus,
 	.smp_prepare_cpus	= emev2_smp_prepare_cpus,
-	.smp_secondary_init	= emev2_secondary_init,
 	.smp_boot_secondary	= emev2_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_kill		= emev2_cpu_kill,
arch/arm/mach-shmobile/smp-r8a7779.c +0 -7
index 3a4acf2..9949065 100644
@@ -23,7 +23,6 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
 #include <asm/smp_plat.h>

@@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
 }
 
 
-static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
-{
-	gic_secondary_init(0);
-}
-
 static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	struct r8a7779_pm_ch *ch = NULL;

@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)
 struct smp_operations r8a7779_smp_ops  __initdata = {
 	.smp_init_cpus		= r8a7779_smp_init_cpus,
 	.smp_prepare_cpus	= r8a7779_smp_prepare_cpus,
-	.smp_secondary_init	= r8a7779_secondary_init,
 	.smp_boot_secondary	= r8a7779_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_kill		= r8a7779_cpu_kill,
arch/arm/mach-shmobile/smp-sh73a0.c +0 -7
index acb46a9..d0f9aca 100644
@@ -23,7 +23,6 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>

@@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)
 	return scu_get_core_count(scu_base);
 }
 
-static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
-{
-	gic_secondary_init(0);
-}
-
 static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	cpu = cpu_logical_map(cpu);

@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)
 struct smp_operations sh73a0_smp_ops __initdata = {
 	.smp_init_cpus		= sh73a0_smp_init_cpus,
 	.smp_prepare_cpus	= sh73a0_smp_prepare_cpus,
-	.smp_secondary_init	= sh73a0_secondary_init,
 	.smp_boot_secondary	= sh73a0_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_kill		= sh73a0_cpu_kill,
arch/arm/mach-socfpga/platsmp.c +0 -12
index 84c60fa..ca14d1d 100644
@@ -22,7 +22,6 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_scu.h>

@@ -33,16 +32,6 @@
 extern void __iomem *sys_manager_base_addr;
 extern void __iomem *rst_manager_base_addr;
 
-static void __cpuinit socfpga_secondary_init(unsigned int cpu)
-{
-	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-}
-
 static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;

@@ -109,7 +98,6 @@ static void socfpga_cpu_die(unsigned int cpu)
 struct smp_operations socfpga_smp_ops __initdata = {
 	.smp_init_cpus		= socfpga_smp_init_cpus,
 	.smp_prepare_cpus	= socfpga_smp_prepare_cpus,
-	.smp_secondary_init	= socfpga_secondary_init,
 	.smp_boot_secondary	= socfpga_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_die		= socfpga_cpu_die,
arch/arm/mach-spear13xx/platsmp.c +0 -8
index af4ade6..551c69c 100644
@@ -15,7 +15,6 @@
 #include <linux/jiffies.h>
 #include <linux/io.h>
 #include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
 #include <mach/spear.h>

@@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
 static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
 {
 	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
arch/arm/mach-tegra/platsmp.c +0 -8
index 2c6b3d5..9348d3c 100644
@@ -18,7 +18,6 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 #include <linux/clk/tegra.h>
 
 #include <asm/cacheflush.h>

@@ -44,13 +43,6 @@ static cpumask_t tegra_cpu_init_mask;
 
 static void __cpuinit tegra_secondary_init(unsigned int cpu)
 {
-	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
 	cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
 }
arch/arm/mach-ux500/platsmp.c +0 -8
index 18f7af3..152b130 100644
@@ -16,7 +16,6 @@
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>

@@ -58,13 +57,6 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit ux500_secondary_init(unsigned int cpu)
 {
 	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
arch/arm/mach-virt/platsmp.c +0 -8
index 8badaab..f4143f5 100644
@@ -21,8 +21,6 @@
 #include <linux/smp.h>
 #include <linux/of.h>
 
-#include <linux/irqchip/arm-gic.h>
-
 #include <asm/psci.h>
 #include <asm/smp_plat.h>
 

@@ -45,14 +43,8 @@ static int __cpuinit virt_boot_secondary(unsigned int cpu,
 	return -ENODEV;
 }
 
-static void __cpuinit virt_secondary_init(unsigned int cpu)
-{
-	gic_secondary_init(0);
-}
-
 struct smp_operations __initdata virt_smp_ops = {
 	.smp_init_cpus		= virt_smp_init_cpus,
 	.smp_prepare_cpus	= virt_smp_prepare_cpus,
-	.smp_secondary_init	= virt_secondary_init,
 	.smp_boot_secondary	= virt_boot_secondary,
 };
arch/arm/plat-versatile/platsmp.c +0 -8
index f2ac155..1e1b2d7 100644
@@ -14,7 +14,6 @@
 #include <linux/device.h>
 #include <linux/jiffies.h>
 #include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>

@@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);
 void __cpuinit versatile_secondary_init(unsigned int cpu)
 {
 	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * let the primary processor know we're out of the
 	 * pen, then head off into the C entry point
 	 */
drivers/irqchip/irq-gic.c +21 -7
index 974f77c..add1fd8 100644
@@ -28,6 +28,7 @@
 #include <linux/module.h>
 #include <linux/list.h>
 #include <linux/smp.h>
+#include <linux/cpu.h>
 #include <linux/cpu_pm.h>
 #include <linux/cpumask.h>
 #include <linux/io.h>

@@ -699,6 +700,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
 	return 0;
 }
 
+#ifdef CONFIG_SMP
+static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
+					unsigned long action, void *hcpu)
+{
+	if (action == CPU_STARTING)
+		gic_cpu_init(&gic_data[0]);
+	return NOTIFY_OK;
+}
+
+/*
+ * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
+ * priority because the GIC needs to be up before the ARM generic timers.
+ */
+static struct notifier_block __cpuinitdata gic_cpu_notifier = {
+	.notifier_call = gic_secondary_init,
+	.priority = 100,
+};
+#endif
+
 const struct irq_domain_ops gic_irq_domain_ops = {
 	.map = gic_irq_domain_map,
 	.xlate = gic_irq_domain_xlate,

@@ -789,6 +809,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 
 #ifdef CONFIG_SMP
 	set_smp_cross_call(gic_raise_softirq);
+	register_cpu_notifier(&gic_cpu_notifier);
 #endif
 
 	set_handle_irq(gic_handle_irq);

@@ -799,13 +820,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 	gic_pm_init(gic);
 }
 
-void __cpuinit gic_secondary_init(unsigned int gic_nr)
-{
-	BUG_ON(gic_nr >= MAX_GIC_NR);
-
-	gic_cpu_init(&gic_data[gic_nr]);
-}
-
 #ifdef CONFIG_OF
 static int gic_cnt __initdata = 0;
include/linux/irqchip/arm-gic.h +0 -1
index 3fd8e42..3e203eb 100644
@@ -65,7 +65,6 @@ extern struct irq_chip gic_arch_extn;
 
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
 		    u32 offset, struct device_node *);
-void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 
 static inline void gic_init(unsigned int nr, int start,
author
#6 lore raw

v3 cover Preparatory GIC patches for arm64 support

In reply to Catalin Marinas

Hi Russell,

Quoted 11 lines · Catalin Marinas

That's the third version of the GIC clean-up patches required to support arm64. This is based on 3.9-rc3 and covers new platform code that has been merged into 3.9-rc1.

The patches touch mostly SoC code, drivers/ and arch/arm/ functions moved out into include/linux/.

Russell, what's your preferred way of getting these patches upstream? Ack'ing them and me sending pull request to arm-soc or you would rather merge them via your tree? Either way works for me at the moment since the code is based on mainline.

Do you have any preferred path for getting these patches upstream? I plan to send a pull request soon and I would like to know where to. FYI, the detail/diffstat are below.

Thanks.

The following changes since commit a937536b868b8369b98967929045f1df54234323:

Linux 3.9-rc3 (2013-03-17 15:59:32 -0700)

are available in the git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git gic

for you to fetch changes up to c0114709ed85a5693eb74acdfa03d94f7f12e5b8:

irqchip: gic: Perform the gic_secondary_init() call via CPU notifier (2013-03-26 16:12:02 +0000)

----------------------------------------------------------------
Catalin Marinas (4):
arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h
arm: Move chained_irq_(enter|exit) to a generic file
irqchip: gic: Call handle_bad_irq() directly
irqchip: gic: Perform the gic_secondary_init() call via CPU notifier

 arch/arm/include/asm/irq.h                  |  5 +++
 arch/arm/include/asm/mach/irq.h             | 36 --------------------
 arch/arm/mach-at91/gpio.c                   |  3 +-
 arch/arm/mach-exynos/common.c               |  1 +
 arch/arm/mach-exynos/platsmp.c              |  8 -----
 arch/arm/mach-highbank/platsmp.c            |  7 ----
 arch/arm/mach-imx/platsmp.c                 | 12 -------
 arch/arm/mach-msm/platsmp.c                 |  8 -----
 arch/arm/mach-omap2/omap-smp.c              |  7 ----
 arch/arm/mach-prima2/platsmp.c              |  8 -----
 arch/arm/mach-s3c24xx/irq.c                 |  1 +
 arch/arm/mach-shmobile/smp-emev2.c          |  7 ----
 arch/arm/mach-shmobile/smp-r8a7779.c        |  7 ----
 arch/arm/mach-shmobile/smp-sh73a0.c         |  7 ----
 arch/arm/mach-socfpga/platsmp.c             | 12 -------
 arch/arm/mach-spear13xx/platsmp.c           |  8 -----
 arch/arm/mach-tegra/platsmp.c               |  8 -----
 arch/arm/mach-ux500/platsmp.c               |  8 -----
 arch/arm/mach-virt/platsmp.c                |  8 -----
 arch/arm/plat-samsung/irq-vic-timer.c       |  3 +-
 arch/arm/plat-samsung/s5p-irq-gpioint.c     |  3 +-
 arch/arm/plat-versatile/platsmp.c           |  8 -----
 drivers/gpio/gpio-msm-v2.c                  |  3 +-
 drivers/gpio/gpio-mxc.c                     |  2 +-
 drivers/gpio/gpio-omap.c                    |  3 +-
 drivers/gpio/gpio-pl061.c                   |  2 +-
 drivers/gpio/gpio-pxa.c                     |  3 +-
 drivers/gpio/gpio-tegra.c                   |  3 +-
 drivers/irqchip/exynos-combiner.c           |  1 +
 drivers/irqchip/irq-gic.c                   | 32 +++++++++++++-----
 drivers/irqchip/irq-vic.c                   |  2 +-
 drivers/pinctrl/pinctrl-at91.c              |  3 +-
 drivers/pinctrl/pinctrl-exynos.c            |  3 +-
 drivers/pinctrl/pinctrl-nomadik.c           |  2 +-
 drivers/pinctrl/pinctrl-sirf.c              |  2 +-
 drivers/pinctrl/spear/pinctrl-plgpio.c      |  2 +-
 drivers/staging/imx-drm/ipu-v3/ipu-common.c |  2 +-
 include/linux/irqchip/arm-gic.h             |  1 -
 include/linux/irqchip/chained_irq.h         | 52 +++++++++++++++++++++++++++++
 39 files changed, 99 insertions(+), 194 deletions(-)
 create mode 100644 include/linux/irqchip/chained_irq.h