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clk: tegra114: Fix msenc clock register

PATCH New Mikko Perttunen 3 participants 4 messages Jun 4, 2013 – Jun 5, 2013

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Common clk Tegra architecture support Tegra clock driver
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Mikko Perttunen

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#0 lore raw

PATCH 1/1 clk: tegra114: Fix msenc clock register

The msenc clock's register was set to the usb3 clock's register.

Signed-off-by Mikko Perttunen <[email protected]>
Acked-by Peter De Schrijver <[email protected]>
---
 drivers/clk/tegra/clk-tegra114.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/tegra/clk-tegra114.c +1 -1
index d78e16e..c4f2e0a 100644
@@ -1747,7 +1747,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
 	TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
 	TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
 	TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
-	TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_h_regs, TEGRA_PERIPH_WAR_1005168, msenc),
+	TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, msenc),
 	TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
 	TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
 	TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
Signature · 1 line
1.8.1.5
#1 lore raw

PATCH 1/1 clk: tegra114: Fix msenc clock register

Quoted 1 line · Mikko Perttunen

The msenc clock's register was set to the usb3 clock's register.

drivers/clk changes should be sent to Mike Turquette (CC'd here). See the output of ./scripts/get_maintainer.pl and/or the MAINTAINERS file.

Hopefully he can pick this up from the ARM mailing list - if not, I'm sure he'll let you know to resend it.

author
#2 lore raw

PATCH 1/1 clk: tegra114: Fix msenc clock register

Ah, sorry about that. I did actually use get_maintainer.pl, and it listed you
on the first line :) It looks like only drivers/clk/clk-* is assigned to Mike
according to MAINTAINERS, and the tegra/ subdirectory isn't.

Quoted 8 lines · Stephen Warren
Quoted 1 line · Mikko Perttunen

The msenc clock's register was set to the usb3 clock's register.

drivers/clk changes should be sent to Mike Turquette (CC'd here). See the output of ./scripts/get_maintainer.pl and/or the MAINTAINERS file.

Hopefully he can pick this up from the ARM mailing list - if not, I'm sure he'll let you know to resend it.

#3 lore raw

PATCH 1/1 clk: tegra114: Fix msenc clock register

In reply to Mikko Perttunen

Quoting Mikko Perttunen (2013-06-04 04:25:43)

Quoted 4 lines

The msenc clock's register was set to the usb3 clock's register.

Signed-off-by Mikko Perttunen <[email protected]>
Acked-by Peter De Schrijver <[email protected]>

Pulled into clk-next.

Thanks,
Mike

Quoted 25 lines
---
 drivers/clk/tegra/clk-tegra114.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/tegra/clk-tegra114.c +1 -1
index d78e16e..c4f2e0a 100644
@@ -1747,7 +1747,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
        TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
        TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
        TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
-       TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_h_regs, TEGRA_PERIPH_WAR_1005168, msenc),
+       TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, msenc),
        TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
        TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
        TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
Signature · 7 lines
1.8.1.5


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