ARM: MPIDR linearization

RFC PATCH Superseded Lorenzo Pieralisi 5 participants 21 messages Jun 6, 2013 – Jun 20, 2013

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Lorenzo Pieralisi

author

2013-06-06 15:22 UTC #0 lore raw

v2 cover ARM: MPIDR linearization

This patchset is v2 of a previous posting:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/172873.html

v2 changes:

- rescheduled registers usage in compute_mpidr_hash macro

Cores in ARM SMP systems are identified through coprocessor registers, so that every core, by executing a coprocessor read, can detect its own identifier. The CPU identifier evolved from a simple CPU ID on ARM 11 MPcore SMP, where the CPU ID was split in two subfields (CPU ID and CLUSTER ID) to the v7 MPIDR, where the MPIDR[23:0] bits define three affinity levels that can describe thread, core, cluster topology identifiers. According to the ARM 11 MPcore TRM and for architecture versions later than v7 (MPIDR), to the ARM ARM, the identifier registers format is as follows:

NR: non-relevant for identification

ARM11 MPCORE: CPU ID register

31 12 11 8 7 4 3 0
---------------------------------------------------------------------------
| NR | CLUSTER ID | NR | CPU ID |
--------------------------------------------------------------------------

ARM v7: MPIDR

31 24 23 16 15 8 7 0
---------------------------------------------------------------------------
| NR | AFFINITY 2 | AFFINITY 1 | AFFINITY 0 |
---------------------------------------------------------------------------

The split of CPU identifiers in multiple affinity levels implies that the CPU ID, and later the MPIDR, cannot be used as simple indexes, since the bit representation can contain holes:

eg 4 CPUs, in two separate clusters with two CPUs each:

CPU0: MPIDR = 0x0
CPU1: MPIDR = 0x1
CPU2: MPIDR = 0x100
CPU3: MPIDR = 0x101

In order to carry out operations that rely on the HW CPUID/MPIDR (CCI disabling, context save/restore) the association of the CPU ID, or MPIDR to an index is needed so that the CPU can be associated with a set of resources. Resources look-up through the HW CPU ID is carried out in code paths usually executed in power down procedures, that have to be fast and look-up should be performed with few instructions that may be executing in physical address space, with the MMU off.
In order to provide a fast conversion from [CPU ID, MPIDR] values to indexes this set provides methods to build a simple collision-free hash function based on shifting and OR'ing of CPU ID values, with shifts precomputed at boot by scanning the cpu_logical_map entries (that contain the CPUID/MPIDR) of possible CPUs.

By scanning the cpu_logical_map, the boot code detects how many bits are really required to represent HW identifiers in the system and map them to a set of buckets that actually represent the given index a HW id correspond to. The hashing algorithm inherently takes advantage of a-priori knowledge of the CPUIDs/MPIDRs allowed bits layout and it can be executed with few instructions even in code paths where caching and the MMU are turned off (e.g resuming from idle, S2R, hibernation).

One drawback of the current hashing algorithm is that it may result in a big number of buckets if the recommendations on the CPUID/MPIDR layout are not respected in the CPUID/MPIDR configuration; code warns on hash table sizes bigger than 4 times the number of possible CPUs, which is a symptom of a weird CPUID/MPIDR HW configuration and should be the exception not the rule.

The first patch in the series provides a function that precomputes all required hashing parameters by scanning the cpu_logical_map (that contains HW identifiers), computes and stashes the hash parameters in a structure exported to all kernel components for further usage.

The second patch fixes the current cpu_{suspend}/{resume} functionality, so that all levels of CPUID/MPIDR are supported and cpu_{suspend}/{resume} can be used on systems where affinity levels 1 and 2 are actually populated. The fix carries out dynamic allocation of the array used to save the context pointers, with size equal to the number of precomputed CPUID/MPIDR hash buckets. To access the array, the CPUID/MPIDR values are hashed through the algorithm built in patch 1 so that a hash value is retrieved and the array can be indexed properly through it.

Context pointer array is allocated through kmalloc, so that it is made up of a contiguous chunk of memory whose virtual address can be safely converted to physical address (used in the MMU off path) through a static mapping translation valid for all pages (if more than one) making up the context pointer array. Context pointer array base address is stashed in a structure easily retrieved in assembly through a pc relative load that provides both virtual and physical address so that address translation is not needed in the cpu_resume path, saving a few instructions.

Code will be improved later through dynamic patching so that the mask and shifts in the hashing algorithm will be embedded in the assembly instructions as immediates, removing the need for multiple loads to memory to retrieve them at every given cpu_{suspend}/{resume} cycle.

Tested on TC2 (dual cluster 2x3 A15/A7 system) through CPU idle deep C-states allowing A15 and A7 shutdown modes on both SMP and UP configurations.

Lorenzo Pieralisi (2):
ARM: kernel: build MPIDR hash function data structure
ARM: kernel: implement stack pointer save array through MPIDR hashing

 arch/arm/include/asm/smp_plat.h | 18 ++++++++
 arch/arm/include/asm/suspend.h  |  5 +++
 arch/arm/kernel/asm-offsets.c   |  6 +++
 arch/arm/kernel/setup.c         | 67 ++++++++++++++++++++++++++++
 arch/arm/kernel/sleep.S         | 97 +++++++++++++++++++++++++++++++++--------
 arch/arm/kernel/suspend.c       | 20 +++++++++
 6 files changed, 195 insertions(+), 18 deletions(-)

Signature · 1 line

1.8.2.2

Lorenzo Pieralisi

author

2013-06-06 15:22 UTC #1 lore raw

RFC PATCH v2 1/2 ARM: kernel: build MPIDR hash function data structure

On ARM SMP systems, cores are identified by their MPIDR register. The MPIDR guidelines in the ARM ARM do not provide strict enforcement of MPIDR layout, only recommendations that, if followed, split the MPIDR on ARM 32 bit platforms in three affinity levels. In multi-cluster systems like big.LITTLE, if the affinity guidelines are followed, the MPIDR can not be considered an index anymore. This means that the association between logical CPU in the kernel and the HW CPU identifier becomes somewhat more complicated requiring methods like hashing to associate a given MPIDR to a CPU logical index, in order for the look-up to be carried out in an efficient and scalable way.

This patch provides a function in the kernel that starting from the cpu_logical_map, implement collision-free hashing of MPIDR values by checking all significative bits of MPIDR affinity level bitfields. The hashing can then be carried out through bits shifting and ORing; the resulting hash algorithm is a collision-free though not minimal hash that can be executed with few assembly instructions. The mpidr is filtered through a mpidr mask that is built by checking all bits that toggle in the set of MPIDRs corresponding to possible CPUs. Bits that do not toggle do not carry information so they do not contribute to the resulting hash.

Pseudo code:

/* check all bits that toggle, so they are required */ for (i = 1, mpidr_mask = 0; i < num_possible_cpus(); i++)

	mpidr_mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));

/*
* Build shifts to be applied to aff0, aff1, aff2 values to hash the mpidr
* fls() returns the last bit set in a word, 0 if none
* ffs() returns the first bit set in a word, 0 if none
*/
fs0 = mpidr_mask[7:0] ? ffs(mpidr_mask[7:0]) - 1 : 0;
fs1 = mpidr_mask[15:8] ? ffs(mpidr_mask[15:8]) - 1 : 0;
fs2 = mpidr_mask[23:16] ? ffs(mpidr_mask[23:16]) - 1 : 0;
ls0 = fls(mpidr_mask[7:0]);
ls1 = fls(mpidr_mask[15:8]);
ls2 = fls(mpidr_mask[23:16]);
bits0 = ls0 - fs0;
bits1 = ls1 - fs1;
bits2 = ls2 - fs2;
aff0_shift = fs0;
aff1_shift = 8 + fs1 - bits0;
aff2_shift = 16 + fs2 - (bits0 + bits1);

u32 hash(u32 mpidr) {
	u32 l0, l1, l2;
	u32 mpidr_masked = mpidr & mpidr_mask;
	l0 = mpidr_masked & 0xff;
	l1 = mpidr_masked & 0xff00;
	l2 = mpidr_masked & 0xff0000;
	return (l0 >> aff0_shift | l1 >> aff1_shift | l2 >> aff2_shift);
}

The hashing algorithm relies on the inherent properties set in the ARM ARM recommendations for the MPIDR. Exotic configurations, where for instance the MPIDR values at a given affinity level have large holes, can end up requiring big hash tables since the compression of values that can be achieved through shifting is somewhat crippled when holes are present. Kernel warns if the number of buckets of the resulting hash table exceeds the number of possible CPUs by a factor of 4, which is a symptom of a very sparse HW MPIDR configuration.

The hash algorithm is quite simple and can easily be implemented in assembly code, to be used in code paths where the kernel virtual address space is not set-up (ie cpu_resume) and instruction and data fetches are strongly ordered so code must be compact and must carry out few data accesses.

Cc Will Deacon <[email protected]>

Cc Catalin Marinas <[email protected]>

Cc Russell King <[email protected]>

Cc Colin Cross <[email protected]>

Cc Santosh Shilimkar <[email protected]>

Cc Daniel Lezcano <[email protected]>

Cc Amit Kucheria <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

Reviewed-by Dave Martin <[email protected]>

Reviewed-by Nicolas Pitre <[email protected]>

---
 arch/arm/include/asm/smp_plat.h | 12 ++++++++
 arch/arm/kernel/setup.c         | 67 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

arch/arm/include/asm/smp_plat.h +12 -0

index aaa61b6..d933b03 100644
@@ -66,4 +66,16 @@ static inline int get_logical_index(u32 mpidr)
 	return -EINVAL;
 }
 
+struct mpidr_hash {
+	u32	mask;
+	u32	shift_aff[3];
+	u32	bits;
+};
+
+extern struct mpidr_hash mpidr_hash;
+
+static inline u32 mpidr_hash_size(void)
+{
+	return 1 << mpidr_hash.bits;
+}
 #endif

arch/arm/kernel/setup.c +67 -0

79 lines not on this page · raw message

Signature · 1 line

1.8.2.2

Lorenzo Pieralisi

author

2013-06-06 15:22 UTC #2 lore raw

RFC PATCH v2 2/2 ARM: kernel: implement stack pointer save array through MPIDR hashing

In reply to Lorenzo Pieralisi

Current implementation of cpu_{suspend}/cpu_{resume} relies on the MPIDR to index the array of pointers where the context is saved and restored. The current approach works as long as the MPIDR can be considered a linear index, so that the pointers array can simply be dereferenced by using the MPIDR[7:0] value.
On ARM multi-cluster systems, where the MPIDR may not be a linear index, to properly dereference the stack pointer array, a mapping function should be applied to it so that it can be used for arrays look-ups.

This patch adds code in the cpu_{suspend}/cpu_{resume} implementation that relies on shifting and ORing hashing method to map a MPIDR value to a set of buckets precomputed at boot to have a collision free mapping from MPIDR to context pointers.

The hashing algorithm must be simple, fast, and implementable with few instructions since in the cpu_resume path the mapping is carried out with the MMU off and the I-cache off, hence code and data are fetched from DRAM with no-caching available. Simplicity is counterbalanced with a little increase of memory (allocated dynamically) for stack pointers buckets, that should be anyway fairly limited on most systems.

Memory for context pointers is allocated in a early_initcall with size precomputed and stashed previously in kernel data structures. Memory for context pointers is allocated through kmalloc; this guarantees contiguous physical addresses for the allocated memory which is fundamental to the correct functioning of the resume mechanism that relies on the context pointer array to be a chunk of contiguous physical memory. Virtual to physical address conversion for the context pointer array base is carried out at boot to avoid fiddling with virt_to_phys conversions in the cpu_resume path which is quite fragile and should be optimized to execute as few instructions as possible.
Virtual and physical context pointer base array addresses are stashed in a struct that is accessible from assembly using values generated through the asm-offsets.c mechanism.

Cc Will Deacon <[email protected]>

Cc Catalin Marinas <[email protected]>

Cc Russell King <[email protected]>

Cc Colin Cross <[email protected]>

Cc Santosh Shilimkar <[email protected]>

Cc Daniel Lezcano <[email protected]>

Cc Amit Kucheria <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

Reviewed-by Dave Martin <[email protected]>

Reviewed-by Nicolas Pitre <[email protected]>

---
 arch/arm/include/asm/smp_plat.h | 10 ++++-
 arch/arm/include/asm/suspend.h  |  5 +++
 arch/arm/kernel/asm-offsets.c   |  6 +++
 arch/arm/kernel/sleep.S         | 97 +++++++++++++++++++++++++++++++++--------
 arch/arm/kernel/suspend.c       | 20 +++++++++
 5 files changed, 118 insertions(+), 20 deletions(-)

arch/arm/include/asm/smp_plat.h +8 -2

index d933b03..f15eb6e 100644
@@ -66,9 +66,15 @@ static inline int get_logical_index(u32 mpidr)
 	return -EINVAL;
 }
 
+/*
+ * NOTE ! Assembly code relies on the following
+ * structure memory layout in order to carry out load
+ * multiple from its base address. For more
+ * information check arch/arm/kernel/sleep.S
+ */
 struct mpidr_hash {
-	u32	mask;
-	u32	shift_aff[3];
+	u32	mask; /* used by sleep.S */
+	u32	shift_aff[3]; /* used by sleep.S */
 	u32	bits;
 };

arch/arm/include/asm/suspend.h +5 -0

index 1c0a551..cd20029 100644
@@ -1,6 +1,11 @@
 #ifndef __ASM_ARM_SUSPEND_H
 #define __ASM_ARM_SUSPEND_H
 
+struct sleep_save_sp {
+	u32 *save_ptr_stash;
+	u32 save_ptr_stash_phys;
+};
+
 extern void cpu_resume(void);
 extern int cpu_suspend(unsigned long, int (*)(unsigned long));

arch/arm/kernel/asm-offsets.c +6 -0

index ee68cce..ded0417 100644
@@ -23,6 +23,7 @@
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/procinfo.h>
+#include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <linux/kbuild.h>

@@ -145,6 +146,11 @@ int main(void)
 #ifdef MULTI_CACHE
   DEFINE(CACHE_FLUSH_KERN_ALL,	offsetof(struct cpu_cache_fns, flush_kern_all));
 #endif
+#ifdef CONFIG_ARM_CPU_SUSPEND
+  DEFINE(SLEEP_SAVE_SP_SZ,	sizeof(struct sleep_save_sp));
+  DEFINE(SLEEP_SAVE_SP_PHYS,	offsetof(struct sleep_save_sp, save_ptr_stash_phys));
+  DEFINE(SLEEP_SAVE_SP_VIRT,	offsetof(struct sleep_save_sp, save_ptr_stash));
+#endif
   BLANK();
   DEFINE(DMA_BIDIRECTIONAL,	DMA_BIDIRECTIONAL);
   DEFINE(DMA_TO_DEVICE,		DMA_TO_DEVICE);

arch/arm/kernel/sleep.S +79 ~~-18~~

119 lines not on this page · raw message

arch/arm/kernel/suspend.c +20 -0

index c59c97e..17d02f6 100644
@@ -1,9 +1,12 @@
 #include <linux/init.h>
+#include <linux/slab.h>
 
+#include <asm/cacheflush.h>
 #include <asm/idmap.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/memory.h>
+#include <asm/smp_plat.h>
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>

@@ -74,3 +77,20 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
 
 	return ret;
 }
+
+extern struct sleep_save_sp sleep_save_sp;
+
+static int cpu_suspend_alloc_sp(void)
+{
+	void *ctx_ptr;
+	/* ctx_ptr is an array of physical addresses */
+	ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(u32), GFP_KERNEL);
+
+	if (WARN_ON(!ctx_ptr))
+		return -ENOMEM;
+	sleep_save_sp.save_ptr_stash = ctx_ptr;
+	sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr);
+	sync_cache_w(&sleep_save_sp);
+	return 0;
+}
+early_initcall(cpu_suspend_alloc_sp);

Signature · 1 line

1.8.2.2

Lorenzo Pieralisi

author

2013-06-11 09:58 UTC #3 lore raw

v2 cover ARM: MPIDR linearization

In reply to Lorenzo Pieralisi

Hi Russell, all,

even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.

I pushed out a branch:

git://linux-arm.org/linux-2.6-lp.git mpidr-linearization

if anyone has time to test the set that would be really great, thank you very much.

Comments and further review appreciated.

Thanks a lot,
Lorenzo

Quoted 118 lines · Lorenzo Pieralisi

This patchset is v2 of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/172873.html
v2 changes:
- rescheduled registers usage in compute_mpidr_hash macro
Cores in ARM SMP systems are identified through coprocessor registers, so that every core, by executing a coprocessor read, can detect its own identifier. The CPU identifier evolved from a simple CPU ID on ARM 11 MPcore SMP, where the CPU ID was split in two subfields (CPU ID and CLUSTER ID) to the v7 MPIDR, where the MPIDR[23:0] bits define three affinity levels that can describe thread, core, cluster topology identifiers. According to the ARM 11 MPcore TRM and for architecture versions later than v7 (MPIDR), to the ARM ARM, the identifier registers format is as follows:
NR: non-relevant for identification
ARM11 MPCORE: CPU ID register
31 12 11 8 7 4 3 0
---------------------------------------------------------------------------
| NR | CLUSTER ID | NR | CPU ID |
--------------------------------------------------------------------------
ARM v7: MPIDR
31 24 23 16 15 8 7 0
---------------------------------------------------------------------------
| NR | AFFINITY 2 | AFFINITY 1 | AFFINITY 0 |
---------------------------------------------------------------------------
The split of CPU identifiers in multiple affinity levels implies that the CPU ID, and later the MPIDR, cannot be used as simple indexes, since the bit representation can contain holes:
eg 4 CPUs, in two separate clusters with two CPUs each:
CPU0: MPIDR = 0x0
CPU1: MPIDR = 0x1
CPU2: MPIDR = 0x100
CPU3: MPIDR = 0x101
In order to carry out operations that rely on the HW CPUID/MPIDR (CCI disabling, context save/restore) the association of the CPU ID, or MPIDR to an index is needed so that the CPU can be associated with a set of resources. Resources look-up through the HW CPU ID is carried out in code paths usually executed in power down procedures, that have to be fast and look-up should be performed with few instructions that may be executing in physical address space, with the MMU off.
In order to provide a fast conversion from [CPU ID, MPIDR] values to indexes this set provides methods to build a simple collision-free hash function based on shifting and OR'ing of CPU ID values, with shifts precomputed at boot by scanning the cpu_logical_map entries (that contain the CPUID/MPIDR) of possible CPUs.
By scanning the cpu_logical_map, the boot code detects how many bits are really required to represent HW identifiers in the system and map them to a set of buckets that actually represent the given index a HW id correspond to. The hashing algorithm inherently takes advantage of a-priori knowledge of the CPUIDs/MPIDRs allowed bits layout and it can be executed with few instructions even in code paths where caching and the MMU are turned off (e.g resuming from idle, S2R, hibernation).
One drawback of the current hashing algorithm is that it may result in a big number of buckets if the recommendations on the CPUID/MPIDR layout are not respected in the CPUID/MPIDR configuration; code warns on hash table sizes bigger than 4 times the number of possible CPUs, which is a symptom of a weird CPUID/MPIDR HW configuration and should be the exception not the rule.
The first patch in the series provides a function that precomputes all required hashing parameters by scanning the cpu_logical_map (that contains HW identifiers), computes and stashes the hash parameters in a structure exported to all kernel components for further usage.
The second patch fixes the current cpu_{suspend}/{resume} functionality, so that all levels of CPUID/MPIDR are supported and cpu_{suspend}/{resume} can be used on systems where affinity levels 1 and 2 are actually populated. The fix carries out dynamic allocation of the array used to save the context pointers, with size equal to the number of precomputed CPUID/MPIDR hash buckets. To access the array, the CPUID/MPIDR values are hashed through the algorithm built in patch 1 so that a hash value is retrieved and the array can be indexed properly through it.
Context pointer array is allocated through kmalloc, so that it is made up of a contiguous chunk of memory whose virtual address can be safely converted to physical address (used in the MMU off path) through a static mapping translation valid for all pages (if more than one) making up the context pointer array. Context pointer array base address is stashed in a structure easily retrieved in assembly through a pc relative load that provides both virtual and physical address so that address translation is not needed in the cpu_resume path, saving a few instructions.
Code will be improved later through dynamic patching so that the mask and shifts in the hashing algorithm will be embedded in the assembly instructions as immediates, removing the need for multiple loads to memory to retrieve them at every given cpu_{suspend}/{resume} cycle.
Tested on TC2 (dual cluster 2x3 A15/A7 system) through CPU idle deep C-states allowing A15 and A7 shutdown modes on both SMP and UP configurations.
Lorenzo Pieralisi (2):
ARM: kernel: build MPIDR hash function data structure
ARM: kernel: implement stack pointer save array through MPIDR hashing
 arch/arm/include/asm/smp_plat.h | 18 ++++++++
 arch/arm/include/asm/suspend.h  |  5 +++
 arch/arm/kernel/asm-offsets.c   |  6 +++
 arch/arm/kernel/setup.c         | 67 ++++++++++++++++++++++++++++
 arch/arm/kernel/sleep.S         | 97 +++++++++++++++++++++++++++++++++--------
 arch/arm/kernel/suspend.c       | 20 +++++++++
 6 files changed, 195 insertions(+), 18 deletions(-)
Signature · 1 line
1.8.2.2

Stephen Warren

2013-06-11 15:56 UTC #4 lore raw

v2 cover ARM: MPIDR linearization

Quoted 6 lines · Lorenzo Pieralisi

Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.

FWIW, I booted a Tegra system with these patches applied and didn't see any issue in very brief testing. I'm not sure what targeted testing would be useful?

Nicolas Pitre

2013-06-11 16:12 UTC #5 lore raw

v2 cover ARM: MPIDR linearization

Quoted 11 lines · Stephen Warren

Quoted 6 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
FWIW, I booted a Tegra system with these patches applied and didn't see any issue in very brief testing. I'm not sure what targeted testing would be useful?

Deep idle mode where the CPU is turned off and has to re-enter the kernel via cpu_resume.

Nicolas

Lorenzo Pieralisi

author

2013-06-11 16:22 UTC #6 lore raw

v2 cover ARM: MPIDR linearization

In reply to Stephen Warren

Hi Stephen,

Quoted 11 lines · Stephen Warren

Quoted 6 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
FWIW, I booted a Tegra system with these patches applied and didn't see any issue in very brief testing. I'm not sure what targeted testing would be useful?

That's great thanks. CPUidle deep C-states (when CPUs resume from reset through cpu_resume) are the main triggers of this code, so you should be running with them enabled to test it.

Thank you very much !!
Lorenzo

Stephen Warren

2013-06-11 16:48 UTC #7 lore raw

v2 cover ARM: MPIDR linearization

Quoted 11 lines · Lorenzo Pieralisi

Hi Stephen,
Quoted 8 lines · Stephen Warren
Quoted 6 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.

Quoted 7 lines

Quoted 3 lines
FWIW, I booted a Tegra system with these patches applied and didn't see any issue in very brief testing. I'm not sure what targeted testing would be useful?
That's great thanks. CPUidle deep C-states (when CPUs resume from reset through cpu_resume) are the main triggers of this code, so you should be running with them enabled to test it.

OK, in that case I believe I tested that; I had our "LP2" CPU power-management mode enabled as always, and that powers off the CPUs and resumes them, and didn't see any issue.

Lorenzo Pieralisi

author

2013-06-12 09:07 UTC #8 lore raw

v2 cover ARM: MPIDR linearization

Quoted 16 lines · Stephen Warren

Quoted 15 lines · Lorenzo Pieralisi
Hi Stephen,
Quoted 11 lines · Stephen Warren
Quoted 6 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
FWIW, I booted a Tegra system with these patches applied and didn't see any issue in very brief testing. I'm not sure what targeted testing would be useful?

Quoted 7 lines

Quoted 3 lines
That's great thanks. CPUidle deep C-states (when CPUs resume from reset through cpu_resume) are the main triggers of this code, so you should be running with them enabled to test it.
OK, in that case I believe I tested that; I had our "LP2" CPU power-management mode enabled as always, and that powers off the CPUs and resumes them, and didn't see any issue.

Great, thanks, I guess this also means you did not notice any suspicious warnings at boot (ie "Large number of MPIDR hash buckets detected").

Can I add your tested-by please ?

Thanks a lot,
Lorenzo

Stephen Warren

2013-06-12 15:55 UTC #9 lore raw

v2 cover ARM: MPIDR linearization

Quoted 21 lines · Lorenzo Pieralisi

Quoted 20 lines · Stephen Warren
Quoted 18 lines · Lorenzo Pieralisi
Hi Stephen,
Quoted 11 lines · Stephen Warren
Quoted 6 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
FWIW, I booted a Tegra system with these patches applied and didn't see any issue in very brief testing. I'm not sure what targeted testing would be useful?
That's great thanks. CPUidle deep C-states (when CPUs resume from reset through cpu_resume) are the main triggers of this code, so you should be running with them enabled to test it.

Quoted 6 lines

Quoted 3 lines
OK, in that case I believe I tested that; I had our "LP2" CPU power-management mode enabled as always, and that powers off the CPUs and resumes them, and didn't see any issue.
Great, thanks, I guess this also means you did not notice any suspicious warnings at boot (ie "Large number of MPIDR hash buckets detected").

I didn't, although I didn't look that hard for them!

Quoted 1 line

Can I add your tested-by please ?

Sure.

Nicolas Pitre

2013-06-11 15:58 UTC #10 lore raw

v2 cover ARM: MPIDR linearization

In reply to Lorenzo Pieralisi

Quoted 7 lines · Lorenzo Pieralisi

Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.

Quoted 6 lines

I pushed out a branch:
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization
if anyone has time to test the set that would be really great, thank you very much.

Since a lot of big.LITTLE related code, including proper TC2 support, is being withheld by this, I would suggest we wait say a week for people to test and report any issue they might have, after which it should simply be merged. Some people will test such code only after it is merged anyway.

@Lorenzo: Why not ask for this branch to be included in linux-next right away? This way you'll get implicit testing.

Nicolas

Lorenzo Pieralisi

author

2013-06-19 15:59 UTC #11 lore raw

v2 cover ARM: MPIDR linearization

Hi Russell, all,

Quoted 16 lines · Nicolas Pitre

Quoted 7 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
Quoted 6 lines
I pushed out a branch:
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization
if anyone has time to test the set that would be really great, thank you very much.

Quoted 8 lines

Since a lot of big.LITTLE related code, including proper TC2 support, is being withheld by this, I would suggest we wait say a week for people to test and report any issue they might have, after which it should simply be merged. Some people will test such code only after it is merged anyway.
@Lorenzo: Why not ask for this branch to be included in linux-next right away? This way you'll get implicit testing.

The series was added to -next last Monday, so far just a merge conflict reported, no issues raised. Can I request a pull or should we wait one week more, leave it in -next to enable further testing and then proceed ?

Thanks a lot,
Lorenzo

Nicolas Pitre

2013-06-19 16:05 UTC #12 lore raw

v2 cover ARM: MPIDR linearization

Quoted 25 lines · Lorenzo Pieralisi

Hi Russell, all,
Quoted 22 lines · Nicolas Pitre
Quoted 7 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
Quoted 6 lines
I pushed out a branch:
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization
if anyone has time to test the set that would be really great, thank you very much.
Since a lot of big.LITTLE related code, including proper TC2 support, is being withheld by this, I would suggest we wait say a week for people to test and report any issue they might have, after which it should simply be merged. Some people will test such code only after it is merged anyway.

Quoted 6 lines

Quoted 2 lines
@Lorenzo: Why not ask for this branch to be included in linux-next right away? This way you'll get implicit testing.
The series was added to -next last Monday, so far just a merge conflict reported, no issues raised. Can I request a pull or should we wait one week more, leave it in -next to enable further testing and then proceed ?

With the positive test results that were posted so far I would be confident enough to send a pull request now.

Nicolas

Shawn Guo

2013-06-12 08:36 UTC #13 lore raw

v2 cover ARM: MPIDR linearization

In reply to Lorenzo Pieralisi

Quoted 7 lines · Lorenzo Pieralisi

Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.

Quoted 6 lines

I pushed out a branch:
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization
if anyone has time to test the set that would be really great, thank you very much.

I tested the branch on imx6q, and system suspend/resume works fine with it.

Shawn

Lorenzo Pieralisi

author

2013-06-12 09:13 UTC #14 lore raw

v2 cover ARM: MPIDR linearization

Hi Shawn,

Quoted 10 lines · Shawn Guo

Quoted 9 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
I pushed out a branch:

Quoted 7 lines

Quoted 4 lines
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization
if anyone has time to test the set that would be really great, thank you very much.
I tested the branch on imx6q, and system suspend/resume works fine with it.

Thanks a lot. If you can enable idle deep C-states that would be grand, S2R exercises that code path just on one CPU whilst idle clobbers it on all CPUs at once and ensures the hash is working properly on your platform.

Anyway, thank you very much !
Lorenzo

Shawn Guo

2013-06-12 11:33 UTC #15 lore raw

v2 cover ARM: MPIDR linearization

Quoted 1 line · Lorenzo Pieralisi

Thanks a lot. If you can enable idle deep C-states that would be grand,

We haven't added the power gating support in cpuidle, but only clock gating so far.

Shawn

Quoted 2 lines

S2R exercises that code path just on one CPU whilst idle clobbers it on all CPUs at once and ensures the hash is working properly on your platform.

Lorenzo Pieralisi

author

2013-06-19 16:43 UTC #16 lore raw

v2 cover ARM: MPIDR linearization

In reply to Shawn Guo

Quoted 10 lines · Shawn Guo

Quoted 9 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
I pushed out a branch:

Quoted 7 lines

Quoted 4 lines
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization
if anyone has time to test the set that would be really great, thank you very much.
I tested the branch on imx6q, and system suspend/resume works fine with it.

Can I add your tested-by please ?

Thank you very much,
Lorenzo

Shawn Guo

2013-06-20 00:43 UTC #17 lore raw

v2 cover ARM: MPIDR linearization

Quoted 13 lines · Lorenzo Pieralisi

Quoted 12 lines · Shawn Guo
Quoted 11 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
I pushed out a branch:
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization

Quoted 7 lines

Quoted 5 lines
Quoted 2 lines
if anyone has time to test the set that would be really great, thank you very much.
I tested the branch on imx6q, and system suspend/resume works fine with it.
Can I add your tested-by please ?

Sure.

Tested-by Shawn Guo <[email protected]>

Lorenzo Pieralisi

author

2013-06-20 14:57 UTC #18 lore raw

v2 cover ARM: MPIDR linearization

Quoted 17 lines · Shawn Guo

Quoted 16 lines · Lorenzo Pieralisi
Quoted 15 lines · Shawn Guo
Quoted 13 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
I pushed out a branch:
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization
if anyone has time to test the set that would be really great, thank you very much.

Quoted 8 lines

Quoted 4 lines
Quoted 2 lines
I tested the branch on imx6q, and system suspend/resume works fine with it.
Can I add your tested-by please ?
Sure.
Tested-by Shawn Guo <[email protected]>

Thanks a lot,
Lorenzo

Kevin Hilman

2013-06-19 20:41 UTC #19 lore raw

v2 cover ARM: MPIDR linearization

In reply to Lorenzo Pieralisi

Hi Lorenzo,

Quoted 7 lines · Lorenzo Pieralisi

Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.

Quoted 6 lines

I pushed out a branch:
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization
if anyone has time to test the set that would be really great, thank you very much.

I'm a little late to the party, but I tested this on OMAP4 with the CPUs hitting off in the lower C-states.

Tested-by Kevin Hilman <[email protected]>

Kevin

Lorenzo Pieralisi

author

2013-06-20 10:19 UTC #20 lore raw

v2 cover ARM: MPIDR linearization

Hi Kevin,

Quoted 15 lines · Kevin Hilman

Hi Lorenzo,
Quoted 11 lines · Lorenzo Pieralisi
Hi Russell, all,
even though I think this set is ready to get merged, it would be great if we can test it on as many platforms as possible since it touches core suspend/resume operations on ARM platforms relying on CONFIG_ARM_CPU_SUSPEND, and there are many.
I pushed out a branch:
git://linux-arm.org/linux-2.6-lp.git mpidr-linearization

Quoted 7 lines

Quoted 2 lines
if anyone has time to test the set that would be really great, thank you very much.
I'm a little late to the party, but I tested this on OMAP4 with the CPUs hitting off in the lower C-states.
Tested-by Kevin Hilman <[email protected]>

That's great, thank you very much !

Lorenzo