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ARM: dts: Add camera and barometer sensor support for TRATS2 board

PATCH Superseded Sylwester Nawrocki 2 participants 11 messages Jun 21, 2013 – Jun 24, 2013

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cover ARM: dts: Add camera and barometer sensor support for TRATS2 board

This patch series includes some fixes and extensions to the Exynos dts files to add the camera and barometer sensor support for TRATS2 board. It depends on a patch from Tomasz adding initial TRATS2 board dts file [1].

[1] http://www.spinics.net/lists/arm-kernel/msg253184.html

Jacek Anaszewski (1):
ARM: dts: Add AK8975 device node for Exynos4412 TRATS2 board

Sylwester Nawrocki (7):
ARM: dts: Correct camera pinctrl nodes for Exynos4x12 SoCs
ARM: dts: Add pinctrl entries for Exynos4x12 FIMC-IS peripherals
ARM: dts: Add ISP power domain node for Exynos4x12
ARM: dts: Use generic DMA bindings for Exynos4 SPI devices
ARM: dts: Add camera nodes for Exynos4 SoCs
ARM: dts: Add camera subsystem nodes to exynos4x12.dtsi
ARM: dts: Add camera device nodes for Exynos4412 TRATS2 board

 arch/arm/boot/dts/exynos4.dtsi            |   80 +++++++++++++++++--
 arch/arm/boot/dts/exynos4412-trats2.dts   |  106 +++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4x12-pinctrl.dtsi |   61 ++++++++++++--
 arch/arm/boot/dts/exynos4x12.dtsi         |  123 +++++++++++++++++++++++++++++
 4 files changed, 357 insertions(+), 13 deletions(-)

--
1.7.9.5

#1 lore raw

PATCH 1/8 ARM: dts: Correct camera pinctrl nodes for Exynos4x12 SoCs

Add separate nodes for the CAMCLK pin and turn off pull-up on camera ports A, B. The video bus pins and the clock output (CAMCLK) pin need separate nodes since full camera port is not used in some configurations, e.g. for MIPI CSI-2 bus only CAMCLK is required and data/clock signal use separate dedicated pins.

---
 arch/arm/boot/dts/exynos4x12-pinctrl.dtsi |   40 ++++++++++++++++++++++++-----
 1 file changed, 33 insertions(+), 7 deletions(-)
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +33 -7
index 704290f..50eaa95 100644
@@ -401,13 +401,26 @@
 			samsung,pin-drv = <0>;
 		};
 
-		cam_port_a: cam-port-a {
+		cam_port_a_io: cam-port-a-io {
 			samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
 					"gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
-					"gpj1-0", "gpj1-1", "gpj1-2", "gpj1-3",
-					"gpj1-4";
+					"gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
 			samsung,pin-function = <2>;
-			samsung,pin-pud = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_port_a_clk_active: cam-port-a-clk-active {
+			samsung,pins = "gpj1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		cam_port_a_clk_idle: cam-port-a-clk-idle {
+			samsung,pins = "gpj1-3";
+			samsung,pin-function = <0>;
+			samsung,pin-pud = <0>;
 			samsung,pin-drv = <0>;
 		};
 	};
@@ -778,16 +791,29 @@
 			samsung,pin-drv = <3>;
 		};
 
-		cam_port_b: cam-port-b {
+		cam_port_b_io: cam-port-b-io {
 			samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
 					"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
-					"gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1",
-					"gpm2-2";
+					"gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
 			samsung,pin-function = <3>;
 			samsung,pin-pud = <3>;
 			samsung,pin-drv = <0>;
 		};
 
+		cam_port_b_clk_active: cam-port-b-clk-active {
+			samsung,pins = "gpm2-2";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		cam_port_b_clk_idle: cam-port-b-clk-idle {
+			samsung,pins = "gpm2-2";
+			samsung,pin-function = <0>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
 		eint0: ext-int0 {
 			samsung,pins = "gpx0-0";
 			samsung,pin-function = <0xf>;
Signature · 1 line
1.7.9.5
#2 lore raw

PATCH 1/8 ARM: dts: Correct camera pinctrl nodes for Exynos4x12 SoCs

Hi Sylwester,

Quoted 19 lines · On Friday 21 of June 2013 14:50:17 Sylwester Nawrocki wrote:

Add separate nodes for the CAMCLK pin and turn off pull-up on camera ports A, B. The video bus pins and the clock output (CAMCLK) pin need separate nodes since full camera port is not used in some configurations, e.g. for MIPI CSI-2 bus only CAMCLK is required and data/clock signal use separate dedicated pins.

---
 arch/arm/boot/dts/exynos4x12-pinctrl.dtsi |   40

++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 7 deletions(-)

(quoted diff) +0 -0

b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 704290f..50eaa95 100644

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 405

Quoted 6 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +1 -1
@@ -401,13 +401,26 @@
 			samsung,pin-drv = <0>;
 		};
 
-		cam_port_a: cam-port-a {
+		cam_port_a_io: cam-port-a-io {
 			samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", 

"gpj0-3",

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 406

Quoted 1 line
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +0 -0
 					"gpj0-4", "gpj0-5", "gpj0-6", 

"gpj0-7",

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 407

Quoted 1 line
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +0 -1
-					"gpj1-0", "gpj1-1", "gpj1-2", 

"gpj1-3",

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 407

Quoted 2 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +1 -1
-					"gpj1-4";
+					"gpj1-0", "gpj1-1", "gpj1-2", 

"gpj1-4";

Quoted 8 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +6 -1
 			samsung,pin-function = <2>;
-			samsung,pin-pud = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_port_a_clk_active: cam-port-a-clk-active {
+			samsung,pins = "gpj1-3";

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 424

Quoted 10 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +9 -0
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		cam_port_a_clk_idle: cam-port-a-clk-idle {
+			samsung,pins = "gpj1-3";
+			samsung,pin-function = <0>;
+			samsung,pin-pud = <0>;
 			samsung,pin-drv = <0>;

Who is driving the clock line in this configuration? Idle would suggest that neither the camera nor the camif, so I think some pull should be enabled to avoid floating pin. (Or is there an external pulling resistor for this line in most common setups?)

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 795

Quoted 9 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +1 -1
 		};
 	};
@@ -778,16 +791,29 @@
 			samsung,pin-drv = <3>;
 		};
 
-		cam_port_b: cam-port-b {
+		cam_port_b_io: cam-port-b-io {
 			samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", 

"gpm0-3",

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 796

Quoted 1 line
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +0 -0
 					"gpm0-4", "gpm0-5", "gpm0-6", 

"gpm0-7",

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 784

Quoted 1 line
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +0 -1
-					"gpm1-0", "gpm1-1", "gpm2-0", 

"gpm2-1",

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 797

Quoted 2 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +1 -1
-					"gpm2-2";
+					"gpm1-0", "gpm1-1", "gpm2-0", 

"gpm2-1";

Quoted 8 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +3 -0
 			samsung,pin-function = <3>;
 			samsung,pin-pud = <3>;
 			samsung,pin-drv = <0>;
 		};
 
+		cam_port_b_clk_active: cam-port-b-clk-active {
+			samsung,pins = "gpm2-2";
+			samsung,pin-function = <3>;

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 815

Quoted 10 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +10 -0
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		cam_port_b_clk_idle: cam-port-b-clk-idle {
+			samsung,pins = "gpm2-2";
+			samsung,pin-function = <0>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};

Same here.

Otherwise looks fine to me.

Best regards,
Tomasz

Quoted 4 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +1 -0
+
 		eint0: ext-int0 {
 			samsung,pins = "gpx0-0";
 			samsung,pin-function = <0xf>;
#3 lore raw

PATCH 1/8 ARM: dts: Correct camera pinctrl nodes for Exynos4x12 SoCs

Hi Tomasz,

Thanks for the review.

Quoted 49 lines · Tomasz Figa
Quoted 19 lines · On Friday 21 of June 2013 14:50:17 Sylwester Nawrocki wrote:

Add separate nodes for the CAMCLK pin and turn off pull-up on camera ports A, B. The video bus pins and the clock output (CAMCLK) pin need separate nodes since full camera port is not used in some configurations, e.g. for MIPI CSI-2 bus only CAMCLK is required and data/clock signal use separate dedicated pins.

---
 arch/arm/boot/dts/exynos4x12-pinctrl.dtsi |   40

++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 7 deletions(-)

(quoted diff) +0 -0

b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 704290f..50eaa95 100644

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 405

Quoted 6 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +1 -1
@@ -401,13 +401,26 @@
 			samsung,pin-drv = <0>;
 		};
 
-		cam_port_a: cam-port-a {
+		cam_port_a_io: cam-port-a-io {
 			samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", 

"gpj0-3",

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 406

Quoted 1 line
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +0 -0
 					"gpj0-4", "gpj0-5", "gpj0-6", 

"gpj0-7",

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 407

Quoted 1 line
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +0 -1
-					"gpj1-0", "gpj1-1", "gpj1-2", 

"gpj1-3",

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 407

Quoted 2 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +1 -1
-					"gpj1-4";
+					"gpj1-0", "gpj1-1", "gpj1-2", 

"gpj1-4";

Quoted 15 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +13 -1
 			samsung,pin-function = <2>;
-			samsung,pin-pud = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_port_a_clk_active: cam-port-a-clk-active {
+			samsung,pins = "gpj1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		cam_port_a_clk_idle: cam-port-a-clk-idle {
+			samsung,pins = "gpj1-3";
Quoted 8 lines

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi line 424

Quoted 3 lines
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +2 -0
+			samsung,pin-function = <0>;
+			samsung,pin-pud = <0>;
 			samsung,pin-drv = <0>;

Who is driving the clock line in this configuration? Idle would suggest that neither the camera nor the camif, so I think some pull should be enabled to avoid floating pin. (Or is there an external pulling resistor for this line in most common setups?)

In normal operation it is the AP SoC that feeds the clock to an external image sensor. And the 'idle' pinctrl state is meant for a state where the sensor is powered down completely or is in a suspend state that does not require the sensor's master clock to be provided.

I took this configuration directly from the SoC vendor kernels, but it indeed seems more appropriate to enable pull down on these pins in idle state to avoid floating pins. If anything else is needed relevant pinctrl nodes could be overridden in a board dts file.

I will update this and resend with pull down enabled.

Thanks,
Sylwester

#4 lore raw

PATCH 2/8 ARM: dts: Add pinctrl entries for Exynos4x12 FIMC-IS peripherals

In reply to Sylwester Nawrocki

Add pinctrl nodes for the ISP I2C0, ISP I2C1 and ISP UART devices.

---
 arch/arm/boot/dts/exynos4x12-pinctrl.dtsi |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +21 -0
index 50eaa95..162a1b2 100644
@@ -848,6 +848,27 @@
 			samsung,pin-pud = <0>;
 			samsung,pin-drv = <0>;
 		};
+
+		fimc_is_i2c0: fimc-is-i2c0 {
+			samsung,pins = "gpm4-0", "gpm4-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		fimc_is_i2c1: fimc-is-i2c1 {
+			samsung,pins = "gpm4-2", "gpm4-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		fimc_is_uart: fimc-is-uart {
+			samsung,pins = "gpm3-5", "gpm3-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
 	};
 
 	pinctrl at 03860000 {
Signature · 1 line
1.7.9.5
#5 lore raw

PATCH 3/8 ARM: dts: Add ISP power domain node for Exynos4x12

In reply to Sylwester Nawrocki

The ISP power domain is a common power domain for FIMC-LITE and FIMC-IS (camera ISP) devices.

---
 arch/arm/boot/dts/exynos4x12.dtsi |    5 +++++
 1 file changed, 5 insertions(+)
arch/arm/boot/dts/exynos4x12.dtsi +5 -0
index 01da194..0e24d85 100644
@@ -28,6 +28,11 @@
 		pinctrl3 = &pinctrl_3;
 	};
 
+	pd_isp: isp-power-domain at 10023CA0 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10023CA0 0x20>;
+	};
+
 	clock: clock-controller at 0x10030000 {
 		compatible = "samsung,exynos4412-clock";
 		reg = <0x10030000 0x20000>;
Signature · 1 line
1.7.9.5
#6 lore raw

PATCH 4/8 ARM: dts: Use generic DMA bindings for Exynos4 SPI devices

In reply to Sylwester Nawrocki

The Exynos4 SPI controller uses the PL330 DMA controller which has migrated to the generic DMA bindings since commit b5be04d35dbb2e00 "spi: s3c64xx: Modify SPI driver to use generic DMA DT support". Use the generic bindings to specify the corresponding DMA to make the SPI usable again on Exynos4x12 SOCs.

---
 arch/arm/boot/dts/exynos4.dtsi |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
arch/arm/boot/dts/exynos4.dtsi +6 -6
index 3f94fe8..bce2254 100644
@@ -297,8 +297,8 @@
 		compatible = "samsung,exynos4210-spi";
 		reg = <0x13920000 0x100>;
 		interrupts = <0 66 0>;
-		tx-dma-channel = <&pdma0 7>; /* preliminary */
-		rx-dma-channel = <&pdma0 6>; /* preliminary */
+		dmas = <&pdma0 7>, <&pdma0 6>;
+		dma-names = "tx", "rx";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&clock 327>, <&clock 159>;
@@ -312,8 +312,8 @@
 		compatible = "samsung,exynos4210-spi";
 		reg = <0x13930000 0x100>;
 		interrupts = <0 67 0>;
-		tx-dma-channel = <&pdma1 7>; /* preliminary */
-		rx-dma-channel = <&pdma1 6>; /* preliminary */
+		dmas = <&pdma1 7>, <&pdma1 6>;
+		dma-names = "tx", "rx";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&clock 328>, <&clock 160>;
@@ -327,8 +327,8 @@
 		compatible = "samsung,exynos4210-spi";
 		reg = <0x13940000 0x100>;
 		interrupts = <0 68 0>;
-		tx-dma-channel = <&pdma0 9>; /* preliminary */
-		rx-dma-channel = <&pdma0 8>; /* preliminary */
+		dmas = <&pdma0 9>, <&pdma0 8>;
+		dma-names = "tx", "rx";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&clock 329>, <&clock 161>;
Signature · 1 line
1.7.9.5
#7 lore raw

PATCH 5/8 ARM: dts: Add camera nodes for Exynos4 SoCs

In reply to Sylwester Nawrocki

This patch adds common FIMC and MIPI CSIS device nodes for Exynos4 SoCs.

Signed-off-by Kyungmin Park <kyungmin.park at samsung.com
---
 arch/arm/boot/dts/exynos4.dtsi |   68 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)
arch/arm/boot/dts/exynos4.dtsi +68 -0
index bce2254..4d61120 100644
@@ -36,6 +36,12 @@
 		i2c5 = &i2c_5;
 		i2c6 = &i2c_6;
 		i2c7 = &i2c_7;
+		csis0 = &csis_0;
+		csis1 = &csis_1;
+		fimc0 = &fimc_0;
+		fimc1 = &fimc_1;
+		fimc2 = &fimc_2;
+		fimc3 = &fimc_3;
 	};
 
 	chipid@10000000 {
@@ -92,6 +98,68 @@
 		reg = <0x10010000 0x400>;
 	};
 
+	camera {
+		compatible = "samsung,fimc", "simple-bus";
+		status = "disabled";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		fimc_0: fimc at 11800000 {
+			compatible = "samsung,exynos4210-fimc";
+			reg = <0x11800000 0x1000>;
+			interrupts = <0 84 0>;
+			samsung,power-domain = <&pd_cam>;
+			samsung,sysreg = <&sys_reg>;
+			status = "disabled";
+		};
+
+		fimc_1: fimc at 11810000 {
+			compatible = "samsung,exynos4210-fimc";
+			reg = <0x11810000 0x1000>;
+			interrupts = <0 85 0>;
+			samsung,power-domain = <&pd_cam>;
+			samsung,sysreg = <&sys_reg>;
+			status = "disabled";
+		};
+
+		fimc_2: fimc at 11820000 {
+			compatible = "samsung,exynos4210-fimc";
+			reg = <0x11820000 0x1000>;
+			interrupts = <0 86 0>;
+			samsung,power-domain = <&pd_cam>;
+			samsung,sysreg = <&sys_reg>;
+			status = "disabled";
+		};
+
+		fimc_3: fimc at 11830000 {
+			compatible = "samsung,exynos4210-fimc";
+			reg = <0x11830000 0x1000>;
+			interrupts = <0 87 0>;
+			samsung,power-domain = <&pd_cam>;
+			samsung,sysreg = <&sys_reg>;
+			status = "disabled";
+		};
+
+		csis_0: csis at 11880000 {
+			compatible = "samsung,exynos4210-csis";
+			reg = <0x11880000 0x4000>;
+			interrupts = <0 78 0>;
+			bus-width = <4>;
+			samsung,power-domain = <&pd_cam>;
+			status = "disabled";
+		};
+
+		csis_1: csis at 11890000 {
+			compatible = "samsung,exynos4210-csis";
+			reg = <0x11890000 0x4000>;
+			interrupts = <0 80 0>;
+			bus-width = <2>;
+			samsung,power-domain = <&pd_cam>;
+			status = "disabled";
+		};
+	};
+
 	watchdog at 10060000 {
 		compatible = "samsung,s3c2410-wdt";
 		reg = <0x10060000 0x100>;
Signature · 1 line
1.7.9.5
#8 lore raw

PATCH 6/8 ARM: dts: Add camera subsystem nodes to exynos4x12.dtsi

In reply to Sylwester Nawrocki

Add common camera node and Exynos4212/4412 specific nodes for FIMC, MIPI-CSIS, FIMC-LITE and FIMC-IS devices.

---
 arch/arm/boot/dts/exynos4x12.dtsi |  118 +++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)
arch/arm/boot/dts/exynos4x12.dtsi +118 -0
index 0e24d85..f8cc1d0 100644
@@ -26,6 +26,8 @@
 		pinctrl1 = &pinctrl_1;
 		pinctrl2 = &pinctrl_2;
 		pinctrl3 = &pinctrl_3;
+		fimc-lite0 = &fimc_lite_0;
+		fimc-lite1 = &fimc_lite_1;
 	};
 
 	pd_isp: isp-power-domain at 10023CA0 {
@@ -78,4 +80,120 @@
 		clock-names = "sclk_fimg2d", "fimg2d";
 		status = "disabled";
 	};
+
+	camera {
+		clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>,
+		         <&clock 388>, <&clock 389>, <&clock 17>;
+		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0",
+			    "pxl_async1", "mux_cam0", "mux_cam1", "parent";
+
+		fimc_0: fimc at 11800000 {
+			compatible = "samsung,exynos4212-fimc";
+			clocks = <&clock 256>, <&clock 128>, <&clock 384>, <&clock 17>;
+			clock-names = "fimc", "sclk_fimc", "mux", "parent";
+			samsung,pix-limits = <4224 8192 1920 4224>;
+			samsung,mainscaler-ext;
+			samsung,isp-wb;
+			samsung,cam-if;
+		};
+
+		fimc_1: fimc at 11810000 {
+			compatible = "samsung,exynos4212-fimc";
+			clocks = <&clock 257>, <&clock 129>, <&clock 385>, <&clock 17>;
+			clock-names = "fimc", "sclk_fimc", "mux", "parent";
+			samsung,pix-limits = <4224 8192 1920 4224>;
+			samsung,mainscaler-ext;
+			samsung,isp-wb;
+			samsung,cam-if;
+		};
+
+		fimc_2: fimc at 11820000 {
+			compatible = "samsung,exynos4212-fimc";
+			clocks = <&clock 258>, <&clock 130>, <&clock 386>, <&clock 17>;
+			clock-names = "fimc", "sclk_fimc", "mux", "parent";
+			samsung,pix-limits = <4224 8192 1920 4224>;
+			samsung,mainscaler-ext;
+			samsung,isp-wb;
+			samsung,lcd-wb;
+			samsung,cam-if;
+		};
+
+		fimc_3: fimc at 11830000 {
+			compatible = "samsung,exynos4212-fimc";
+			clocks = <&clock 259>, <&clock 131>, <&clock 387>, <&clock 17>;
+			clock-names = "fimc", "sclk_fimc", "mux", "parent";
+			samsung,pix-limits = <1920 8192 1366 1920>;
+			samsung,rotators = <0>;
+			samsung,mainscaler-ext;
+			samsung,isp-wb;
+			samsung,lcd-wb;
+		};
+
+		csis_0: csis at 11880000 {
+			clocks = <&clock 260>, <&clock 134>, <&clock 390>, <&clock 17>;
+			clock-names = "csis", "sclk_csis", "mux", "parent";
+		};
+
+		csis_1: csis at 11890000 {
+			clocks = <&clock 261>, <&clock 135>, <&clock 391>, <&clock 17>;
+			clock-names = "csis", "sclk_csis", "mux", "parent";
+		};
+
+		fimc_lite_0: fimc-lite at 12390000 {
+			compatible = "samsung,exynos4212-fimc-lite";
+			reg = <0x12390000 0x1000>;
+			interrupts = <0 105 0>;
+			samsung,power-domain = <&pd_isp>;
+			clocks = <&clock 353>;
+			clock-names = "flite";
+			status = "disabled";
+		};
+
+		fimc_lite_1: fimc-lite at 123A0000 {
+			compatible = "samsung,exynos4212-fimc-lite";
+			reg = <0x123A0000 0x1000>;
+			interrupts = <0 106 0>;
+			samsung,power-domain = <&pd_isp>;
+			clocks = <&clock 354>;
+			clock-names = "flite";
+			status = "disabled";
+		};
+
+		fimc_is: fimc-is at 12000000 {
+			compatible = "samsung,exynos4212-fimc-is", "simple-bus";
+			reg = <0x12000000 0x260000>;
+			interrupts = <0 90 0>, <0 95 0>;
+			samsung,power-domain = <&pd_isp>;
+			clocks = <&clock 353>, <&clock 354>, <&clock 355>,
+				<&clock 356>, <&clock 17>, <&clock 357>,
+				<&clock 358>, <&clock 359>, <&clock 360>,
+				<&clock 450>,<&clock 451>, <&clock 452>,
+				<&clock 453>, <&clock 176>, <&clock 13>,
+				<&clock 454>, <&clock 395>, <&clock 455>;
+			clock-names = "lite0", "lite1", "ppmuispx",
+				      "ppmuispmx", "mpll", "isp",
+				      "drc", "fd", "mcuisp",
+				      "ispdiv0", "ispdiv1", "mcuispdiv0",
+				      "mcuispdiv1", "uart", "aclk200",
+				      "div_aclk200", "aclk400mcuisp",
+				      "div_aclk400mcuisp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			status = "disabled";
+
+			pmu {
+				reg = <0x10020000 0x3000>;
+			};
+
+			i2c1_isp: i2c-isp at 12140000 {
+				compatible = "samsung,exynos4212-i2c-isp";
+				reg = <0x12130000 0x100>;
+				clocks = <&clock 370>;
+				clock-names = "i2c_isp";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+	};
 };
Signature · 1 line
1.7.9.5
#9 lore raw

PATCH 7/8 ARM: dts: Add AK8975 device node for Exynos4412 TRATS2 board

In reply to Sylwester Nawrocki

From: Jacek Anaszewski <[email protected]>

This patch adds AK8975 magnetometer node and corresponding i2c-gpio bus node for TRATS2 board.

---
 arch/arm/boot/dts/exynos4412-trats2.dts |   15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/arm/boot/dts/exynos4412-trats2.dts +15 -0
index 056b835..826e42e 100644
@@ -453,4 +453,19 @@
 	serial at 13830000 {
 		status = "okay";
 	};
+
+	i2c-gpio-0 {
+		compatible = "i2c-gpio";
+		gpios = <&gpy2 4 0>, <&gpy2 5 0>;
+		i2c-gpio,delay-us = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		ak8975 at 0c {
+			compatible = "asahi-kasei,ak8975";
+			reg = <0x0c>;
+			gpios = <&gpj0 7 0>;
+		};
+	};
 };
Signature · 1 line
1.7.9.5
#10 lore raw

PATCH 8/8 ARM: dts: Add camera device nodes for Exynos4412 TRATS2 board

In reply to Sylwester Nawrocki

This patch enables the front camera using the internal camera ISP (FIMC-IS).

---
 arch/arm/boot/dts/exynos4412-trats2.dts |   91 +++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)
arch/arm/boot/dts/exynos4412-trats2.dts +91 -0
index 826e42e..47c40df 100644
@@ -58,6 +58,15 @@
 			enable-active-high;
 		};
 
+		cam_io_reg: voltage-regulator at 3 {
+			compatible = "regulator-fixed";
+			regulator-name = "CAM_SENSOR_A";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpm0 2 0>;
+			enable-active-high;
+		};
+
 		/* More to come */
 	};
 
@@ -468,4 +477,86 @@
 			gpios = <&gpj0 7 0>;
 		};
 	};
+
+	camera {
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam_port_b_clk_active>;
+		status = "okay";
+
+		fimc_0: fimc at 11800000 {
+			clock-frequency = <160000000>;
+			status = "okay";
+		};
+
+		fimc_1: fimc at 11810000 {
+			clock-frequency = <160000000>;
+			status = "okay";
+		};
+
+		fimc_2: fimc at 11820000 {
+			clock-frequency = <160000000>;
+			status = "okay";
+		};
+
+		fimc_3: fimc at 11830000 {
+			clock-frequency = <160000000>;
+			status = "okay";
+		};
+
+		csis_1: csis at 11890000 {
+			vddcore-supply = <&ldo8_reg>;
+			vddio-supply = <&ldo10_reg>;
+			clock-frequency = <160000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			/* Camera D (4) MIPI CSI-2 (CSIS1) */
+			port at 4 {
+				reg = <4>;
+				csis1_ep: endpoint {
+					remote-endpoint = <&is_s5k6a3_ep>;
+					data-lanes = <1>;
+					samsung,csis-hs-settle = <18>;
+					samsung,csis-wclk;
+				};
+			};
+		};
+
+		fimc_lite_0: fimc-lite at 12390000 {
+			status = "okay";
+		};
+
+		fimc_lite_1: fimc-lite at 123A0000 {
+			status = "okay";
+		};
+
+		fimc-is at 12000000 {
+			pinctrl-0 = <&fimc_is_uart>;
+			pinctrl-names = "default";
+			status = "okay";
+
+			i2c1_isp: i2c-isp at 12140000 {
+				pinctrl-0 = <&fimc_is_i2c1>;
+				pinctrl-names = "default";
+
+				s5k6a3 at 10 {
+					compatible = "samsung,s5k6a3";
+					reg = <0x10>;
+					svdda-supply = <&cam_io_reg>;
+					svddio-supply = <&ldo19_reg>;
+					clock-frequency = <24000000>;
+					samsung,camclk-out = <1>;
+					gpios = <&gpm1 6 0>;
+
+					port {
+						is_s5k6a3_ep: endpoint {
+							remote-endpoint = <&csis1_ep>;
+							data-lanes = <1>;
+						};
+					};
+				};
+			};
+		};
+	};
 };
Signature · 1 line
1.7.9.5