AArch64 support for Versatile Express using KVM
cover AArch64 support for Versatile Express using KVM
This patch series implements KVM support in QEMU for the ARMv8 Cortex A57 CPU. It depends on the previously submitted AArch64 Preparation Patchset V4, and uses as a base, the existing Versatile Express machine model and the already available KVM in-kernel GIC support.
As a reference, KVM Tool and the AArch64 bootwrapper were used, as well as public documentation from ARM. The following work has been tested with SMP capabilities, under ARMv8 Fast Models and the Foundation model (Open Embedded userspace with an emulated MMC).
The work has been sponsored by Huawei, and developed in collaboration with Huawei Technologies Duesseldorf GmbH, European Research Center Munich (ERC). A working tree of this implementation is available on the "kvm-aarch64" branch of the following github repository.
https://github.com/virtualopensystems/qemu.git
Summary of Patches:
[PATCH 1/6] Added aarch64 configure support and default [PATCH 2/6] Added KVM Headers from KVM Tool
[PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers [PATCH 4/6] Added the Versatile Express Machine Model for A57 [PATCH 5/6] Added Boot Support for Aarch64 Processor. [PATCH 6/6] Added SMP for Aarch64 Processors.
Quoted 6 lines · Mian M. Hamayun
This patch series implements KVM support in QEMU for the ARMv8 Cortex A57 CPU.
It depends on the previously submitted AArch64 Preparation Patchset V4, and uses
as a base, the existing Versatile Express machine model and the already available KVM in-kernel GIC support.
This rather overlaps with a bunch of work John Rigby has already done (though not yet published to the mailing lists):
so now we need to reconcile the two trees. If you'd let us know you were doing this a bit earlier we could probably have coordinated something...
thanks
-- PMM
Am 28.06.2013 14:44, schrieb Peter Maydell:
Quoted 8 lines · Mian M. Hamayun
Quoted 6 lines
This patch series implements KVM support in QEMU for the ARMv8 Cortex A57 CPU.
It depends on the previously submitted AArch64 Preparation Patchset V4, and uses
as a base, the existing Versatile Express machine model and the already available KVM in-kernel GIC support.
Quoted 8 lines
This rather overlaps with a bunch of work John Rigby has already done (though not yet published to the mailing lists):
so now we need to reconcile the two trees. If you'd let us know you were doing this a bit earlier we could probably have coordinated something...
I had been looking into that tree myself, and apart from John's Linux'ish "ARM: " prefixes rather than our usual "target-arm: " (part of which you forgot to fix before sending a PULL), I am really opposed to copying A15MPCore_priv for A57. I plan to post a cleanup for the A9 version the weekend, now that we have a more elaborate hw/ directory structure for headers.
Also I would really prefer to have the is_aarch64() helper operate on ARMCPU rather than CPUARMState. QOM cast removal is underway to make that more efficient.
Is there a 32-bit aarch64 register in ARMv8 to be accessed by TCG? If not, the field should be in ARMCPU and a bool rather than uint32_t.
Regards,
Andreas
P.S. This cover letter got submitted separate from the actual patches so that they are not marked RFC - please use --subject-prefix="RFC" or the like and suggest to indicate there against which tree it is.
Signature · 2 lines
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Quoted 4 lines · Andreas Färber
I had been looking into that tree myself, and apart from John's Linux'ish "ARM: " prefixes rather than our usual "target-arm: " (part of which you forgot to fix before sending a PULL), I am really opposed to copying
A15MPCore_privfor A57.
I agree that just copying A15 is wrong (among other things, we should be modelling the hardware, not just "this seems to make KVM not barf"). That's one of the reasons I hadn't sent the patch set out yet.
Quoted 6 lines
Also I would really prefer to have the
is_aarch64()helper operate on ARMCPU rather than CPUARMState. QOM cast removal is underway to make that more efficient.Is there a 32-bit aarch64 register in ARMv8 to be accessed by TCG? If not, the field should be in ARMCPU and a bool rather than
uint32_t.
This also needs looking at, yes.
-- PMM
At the time we started working on AArch64, we were not certain that our implementation would be published in near future. Now that this is cleared up we are more than happy to coordinate together.
Quoted 10 lines · Andreas Färber
Quoted 4 lines
I had been looking into that tree myself, and apart from John's Linux'ish "ARM: " prefixes rather than our usual "target-arm: " (part of which you forgot to fix before sending a PULL), I am really opposed to copying
A15MPCore_privfor A57.I agree that just copying A15 is wrong (among other things, we should be modelling the hardware, not just "this seems to make KVM not barf"). That's one of the reasons I hadn't sent the patch set out yet.
Initially we thought about this aspect too, but in order to get started, we made the choice to continue using the already available A15 part as is. Obviously this is an RFC patch series and we would like to have your opinion on how we can proceed from here, based on the working solution that we have now, although we may have some differences from the real hardware.
Quoted 9 lines
Quoted 6 lines
Also I would really prefer to have the
is_aarch64()helper operate on ARMCPU rather than CPUARMState. QOM cast removal is underway to make that more efficient.Is there a 32-bit aarch64 register in ARMv8 to be accessed by TCG? If not, the field should be in ARMCPU and a bool rather than
uint32_t.This also needs looking at, yes.
-- PMM
--
Hamayun
Alex,
Am 28.06.2013 15:04, schrieb Andreas Färber:
Quoted 25 lines
Am 28.06.2013 14:44, schrieb Peter Maydell:
Quoted 8 lines · Mian M. Hamayun
Quoted 6 lines
This patch series implements KVM support in QEMU for the ARMv8 Cortex A57 CPU.
It depends on the previously submitted AArch64 Preparation Patchset V4, and uses
as a base, the existing Versatile Express machine model and the already available KVM in-kernel GIC support.Quoted 8 lines
This rather overlaps with a bunch of work John Rigby has already done (though not yet published to the mailing lists):
so now we need to reconcile the two trees. If you'd let us know you were doing this a bit earlier we could probably have coordinated something...
I had been looking into that tree myself, and apart from John's Linux'ish "ARM: " prefixes rather than our usual "target-arm: " (part of which you forgot to fix before sending a PULL), I am really opposed to copying
A15MPCore_privfor A57. I plan to post a cleanup for the A9 version the weekend, now that we have a more elaborate hw/ directory structure for headers.
Quoted 6 lines
Also I would really prefer to have the
is_aarch64()helper operate on ARMCPU rather than CPUARMState. QOM cast removal is underway to make that more efficient.Is there a 32-bit aarch64 register in ARMv8 to be accessed by TCG? If not, the field should be in ARMCPU and a bool rather than
uint32_t.
Care to comment on the latter?
Regards,
Andreas
Signature · 2 lines
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Quoted 5 lines · Andreas Färber
Am 28.06.2013 15:04, schrieb Andreas Färber:
Quoted 2 lines
Is there a 32-bit aarch64 register in ARMv8 to be accessed by TCG? If not, the field should be in ARMCPU and a bool rather than
uint32_t.Care to comment on the latter?
I don't suppose the usermode emulation touches it, but the architectural state corresponding to that 'aarch64' field is the PSTATE nRW bit. I don't think this bit is directly accessible via a register access though (other PSTATE bits may be).
thanks
-- PMM