EXYNOS: Convert Assembly code to c and make it common

This patch performs the following:

1) Convert the assembly code for memory and clock initialization to C code.
2) Move the memory and clock init codes from board/samsung to arch/arm
3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code
4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5.
5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main.
6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250.

TEST: Tested SD-MMC boot on SMDK5250 and Origen.
Tested USB and SPI boot on SMDK5250
Compile tested for SMDKV310.

Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes in V2:
- Rebased on latest u-boot-samsung tree.
- Incorporated review comments from Minkyu Kang.

 arch/arm/cpu/armv7/exynos/Makefile                 |   17 +-
 .../arm/cpu/armv7/exynos}/clock_init.h             |    0
 arch/arm/cpu/armv7/exynos/clock_init_exynos4.c     |   94 +++++
 .../arm/cpu/armv7/exynos/clock_init_exynos5.c      |   27 +-
 arch/arm/cpu/armv7/exynos/common_setup.h           |   43 ++
 .../arm/cpu/armv7/exynos}/dmc_common.c             |    7 +-
 .../arm/cpu/armv7/exynos}/dmc_init_ddr3.c          |   17 +-
 arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c       |  295 ++++++++++++++
 .../arm/cpu/armv7/exynos/exynos4_setup.h           |   97 +++++-
 .../arm/cpu/armv7/exynos/exynos5_setup.h           |   28 +-
 arch/arm/cpu/armv7/exynos/lowlevel_init.c          |   72 ++++
 .../arm/cpu/armv7/exynos}/spl_boot.c               |   77 +++-
 board/samsung/origen/Makefile                      |   11 +-
 board/samsung/origen/lowlevel_init.S               |  357 -----------------
 board/samsung/origen/mem_setup.S                   |  421 --------------------
 board/samsung/origen/mmc_boot.c                    |   58 ---
 board/samsung/smdk5250/Makefile                    |   14 +-
 board/samsung/smdkv310/Makefile                    |   10 +-
 board/samsung/smdkv310/lowlevel_init.S             |  414 -------------------
 board/samsung/smdkv310/mem_setup.S                 |  365 -----------------
 board/samsung/smdkv310/mmc_boot.c                  |   60 ---
 include/configs/exynos5250-dt.h                    |    8 +-
 include/configs/origen.h                           |    9 +-
 include/configs/smdkv310.h                         |    8 +-
 24 files changed, 743 insertions(+), 1766 deletions(-)
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/clock_init.h (100%)
 create mode 100644 arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
 rename board/samsung/smdk5250/clock_init.c => arch/arm/cpu/armv7/exynos/clock_init_exynos5.c (97%)
 create mode 100644 arch/arm/cpu/armv7/exynos/common_setup.h
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_common.c (97%)
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_init_ddr3.c (96%)
 create mode 100644 arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c
 rename board/samsung/origen/origen_setup.h => arch/arm/cpu/armv7/exynos/exynos4_setup.h (86%)
 rename board/samsung/smdk5250/setup.h => arch/arm/cpu/armv7/exynos/exynos5_setup.h (96%)
 create mode 100644 arch/arm/cpu/armv7/exynos/lowlevel_init.c
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/spl_boot.c (73%)
 delete mode 100644 board/samsung/origen/lowlevel_init.S
 delete mode 100644 board/samsung/origen/mem_setup.S
 delete mode 100644 board/samsung/origen/mmc_boot.c
 delete mode 100644 board/samsung/smdkv310/lowlevel_init.S
 delete mode 100644 board/samsung/smdkv310/mem_setup.S
 delete mode 100644 board/samsung/smdkv310/mmc_boot.c

arch/arm/cpu/armv7/exynos/Makefile +13 -4

index b2f9152..4661155 100644
@@ -22,10 +22,19 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+COBJS-y	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
+COBJS-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
+COBJS-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+COBJS-y	+= spl_boot.o
+COBJS-y	+= lowlevel_init.o
+endif
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	 $(obj).depend $(LIB)
 

arch/arm/cpu/armv7/exynos/clock_init.h renamed from board/samsung/smdk5250/clock_init.h +0 -0

similarity index 100%
rename from board/samsung/smdk5250/clock_init.h
rename to arch/arm/cpu/armv7/exynos/clock_init.h

arch/arm/cpu/armv7/exynos/clock_init_exynos4.c new file +94 -0

new file mode 100644
index 0000000..bee0b5c
@@ -0,0 +1,94 @@
+/*
+ * Clock Initialization for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+void system_clock_init(void)
+{
+	struct exynos4_clock *clk = (struct exynos4_clock *)EXYNOS4_CLOCK_BASE;
+
+	writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+
+	sdelay(0x10000);
+
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
+	writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
+	writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
+	writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+	writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
+	writel(CLK_SRC_CAM_VAL, &clk->src_cam);
+	writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
+	writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
+	writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
+
+	sdelay(0x10000);
+
+	writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+	writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
+	writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
+	writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
+	writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
+	writel(CLK_DIV_TOP_VAL, &clk->div_top);
+	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+	writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+	writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
+	writel(CLK_DIV_CAM_VAL, &clk->div_cam);
+	writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
+	writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
+	writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
+
+	/* Set PLL locktime */
+	writel(PLL_LOCKTIME, &clk->apll_lock);
+	writel(PLL_LOCKTIME, &clk->mpll_lock);
+	writel(PLL_LOCKTIME, &clk->epll_lock);
+	writel(PLL_LOCKTIME, &clk->vpll_lock);
+
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	writel(APLL_CON0_VAL, &clk->apll_con0);
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	writel(MPLL_CON0_VAL, &clk->mpll_con0);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	writel(EPLL_CON0_VAL, &clk->epll_con0);
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	writel(VPLL_CON0_VAL, &clk->vpll_con0);
+
+	sdelay(0x30000);
+}

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +10 -9

similarity index 97%
rename from board/samsung/smdk5250/clock_init.c
rename to arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index b288e66..3bdbab9 100644
@@ -31,7 +31,8 @@
 #include <asm/arch/dwmmc.h>
 
 #include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 
 #define FSYS1_MMC0_DIV_MASK	0xff0f
 #define FSYS1_MMC0_DIV_VAL	0x0701

@@ -214,10 +215,10 @@ struct mem_timings mem_timings[] = {
 			DMC_MEMCONTROL_BL_8 |
 			DMC_MEMCONTROL_PZQ_DISABLE |
 			DMC_MEMCONTROL_MRR_BYTE_7_0,
-		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-			DMC_MEMCONFIGx_CHIP_COL_10 |
-			DMC_MEMCONFIGx_CHIP_ROW_15 |
-			DMC_MEMCONFIGx_CHIP_BANK_8,
+		.memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGX_CHIP_COL_10 |
+			DMC_MEMCONFIGX_CHIP_ROW_15 |
+			DMC_MEMCONFIGX_CHIP_BANK_8,
 		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
 		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
 		.prechconfig_tp_cnt = 0xff,

@@ -317,10 +318,10 @@ struct mem_timings mem_timings[] = {
 			DMC_MEMCONTROL_BL_8 |
 			DMC_MEMCONTROL_PZQ_DISABLE |
 			DMC_MEMCONTROL_MRR_BYTE_7_0,
-		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-			DMC_MEMCONFIGx_CHIP_COL_10 |
-			DMC_MEMCONFIGx_CHIP_ROW_15 |
-			DMC_MEMCONFIGx_CHIP_BANK_8,
+		.memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGX_CHIP_COL_10 |
+			DMC_MEMCONFIGX_CHIP_ROW_15 |
+			DMC_MEMCONFIGX_CHIP_BANK_8,
 		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
 		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
 		.prechconfig_tp_cnt = 0xff,

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +3 -3

 	for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
 		i++, arm_ratio++) {

@@ -401,12 +402,12 @@ struct mem_timings *clock_get_mem_timings(void)
 	int i;
 
 	if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
-						&arm_freq, &mem_manuf)) {
+				     &arm_freq, &mem_manuf)) {
 		for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
 				i++, mem++) {
 			if (mem->mem_type == mem_type &&
-					mem->frequency_mhz == frequency_mhz &&
-					mem->mem_manuf == mem_manuf)
+			    mem->frequency_mhz == frequency_mhz &&
+			    mem->mem_manuf == mem_manuf)
 				return mem;
 		}
 	}

arch/arm/cpu/armv7/exynos/common_setup.h new file +43 -0

new file mode 100644
index 0000000..59ee192
@@ -0,0 +1,43 @@
+/*
+ * Common APIs for EXYNOS based board
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Memory initialization
+ *
+ * @param reset     Reset PHY during initialization.
+ */
+void mem_ctrl_init(int reset);
+
+ /* System Clock initialization */
+void system_clock_init(void);
+
+/*
+ * Init subsystems according to the reset status
+ *
+ * @return 0 for a normal boot, non-zero for a resume
+ */
+int do_lowlevel_init(void);
+
+void sdelay(unsigned long);

arch/arm/cpu/armv7/exynos/dmc_common.c renamed from board/samsung/smdk5250/dmc_common.c +4 -3

similarity index 97%
rename from board/samsung/smdk5250/dmc_common.c
rename to arch/arm/cpu/armv7/exynos/dmc_common.c
index 109602a..645f57e 100644
@@ -26,7 +26,8 @@
 #include <asm/arch/spl.h>
 
 #include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 
 #define ZQ_INIT_TIMEOUT	10000
 

@@ -175,7 +176,7 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
 	writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
 }
 
-void mem_ctrl_init()
+void mem_ctrl_init(int reset)
 {
 	struct spl_machine_param *param = spl_get_machine_params();
 	struct mem_timings *mem;

@@ -185,7 +186,7 @@ void mem_ctrl_init()
 
 	/* If there are any other memory variant, add their init call below */
 	if (param->mem_type == DDR_MODE_DDR3) {
-		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
+		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
 		if (ret) {
 			/* will hang if failed to init memory control */
 			while (1)

arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c renamed from board/samsung/smdk5250/dmc_init_ddr3.c +10 -7

similarity index 96%
rename from board/samsung/smdk5250/dmc_init_ddr3.c
rename to arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index e050790..4f31977 100644
@@ -27,7 +27,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dmc.h>
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 #include "clock_init.h"
 
 #define RDLVL_COMPLETE_TIMEOUT	10000

@@ -40,7 +41,8 @@ static void reset_phy_ctrl(void)
 	writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+		       int reset)
 {
 	unsigned int val;
 	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;

@@ -51,7 +53,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 	phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
 	dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
 
-	reset_phy_ctrl();
+	if (reset)
+		reset_phy_ctrl();
 
 	/* Set Impedance Output Driver */
 	val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |

@@ -100,14 +103,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
 	/* Start DLL locking */
 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&phy0_ctrl->phy_con12);
+	       &phy0_ctrl->phy_con12);
 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&phy1_ctrl->phy_con12);
+	       &phy1_ctrl->phy_con12);
 
 	update_reset_dll(dmc, DDR_MODE_DDR3);
 
 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-		&dmc->concontrol);
+	       &dmc->concontrol);
 
 	/* Memory Channel Inteleaving Size */
 	writel(mem->iv_size, &dmc->ivcontrol);

@@ -119,7 +122,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
 	/* Precharge Configuration */
 	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-		&dmc->prechconfig);
+	       &dmc->prechconfig);
 
 	/* Power Down mode Configuration */
 	writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +21 -0

new file mode 100644
index 0000000..868a986
@@ -0,0 +1,295 @@
+/*
+ * Memory setup for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +6 -0

+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +52 -0

+			0x00020000, 0x00030000, 0x00010002, 0x00000328
+		},
+#ifdef CONFIG_ORIGEN
+		.timingref = 0x000000BB,
+		.timingrow = 0x4046654f,
+		.timingdata = 0x46400506,
+		.timingpower = 0x52000A3C,
+#else
+		.timingref = 0x000000BC,
+#ifdef DRAM_CLK_330
+		.timingrow = 0x3545548d,
+		.timingdata = 0x45430506,
+		.timingpower = 0x4439033c,
+#endif
+#ifdef DRAM_CLK_400
+		.timingrow = 0x45430506,
+		.timingdata = 0x56500506,
+		.timingpower = 0x5444033d,
+#endif
+#endif
+		.zqcontrol = 0xE3855703,
+		.control0 = 0x71101008,
+		.control1 = 0xe0000086,
+		.control2 = 0x00000000,
+		.concontrol = 0x0fff301a,
+		.prechconfig = 0xff000000,
+		.memcontrol = 0x00312640,
+#ifdef CONFIG_MIU_LINEAR
+		/*
+		 * Memory Configuration Chip 0
+		 * Address Mapping: linear
+		 * Number of Column address Bits: 10 bits
+		 * Number of Rows Address Bits: 14
+		 * Number of Banks: 8
+		 */
+		.memconfig0 = 0x40e01323,
+		/*
+		 * Memory Configuration Chip 1
+		 * Address Mapping: Linear
+		 * Number of Column address Bits: 10 bits
+		 * Number of Rows Address Bits: 14
+		 * Number of Banks: 8
+		 */
+		.memconfig1 = 0x60e01323,
+#else
+		/*
+		* Memory Configuration Chip 0
+		* Address Mapping: Interleaved
+		* Number of Column address Bits: 10 bits
+		 * Number of Rows Address Bits: 14
+		* Number of Banks: 8
+		*/

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +24 -0

+		.dll_resync = 3,
+		.dll_on = 1,
+};
+
+static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
+{
+	if (ctrl_no) {
+		writel((mem.control1 | (1 << mem.dll_resync)),
+		       &dmc->phycontrol1);
+		writel((mem.control1 | (0 << mem.dll_resync)),
+		       &dmc->phycontrol1);
+	} else {
+		writel((mem.control0 | (0 << mem.dll_on)),
+		       &dmc->phycontrol0);
+		writel((mem.control0 | (1 << mem.dll_on)),
+		       &dmc->phycontrol0);
+	}
+}
+
+static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
+{
+	int i;
+	unsigned long mask = 0;
+

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +30 -0

+	/*
+	 * Async bridge configuration at CPU_core:
+	 * 1: half_sync
+	 * 0: full_sync
+	 */
+	writel(1, ASYNC_CONFIG);
+#ifdef SET_MIU
+#ifdef CONFIG_ORIGEN
+	/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+	writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+		APB_SFR_INTERLEAVE_CONF_OFFSET);
+	/* Update MIU Configuration */
+	writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +
+		APB_SFR_ARBRITATION_CONF_OFFSET);
+#else
+	writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+		APB_SFR_INTERLEAVE_CONF_OFFSET);
+	writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+	       ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET);
+	writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+	       ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET);
+	writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
+#ifdef CONFIG_MIU_LINEAR
+	writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+	       ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET);
+	writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+	       ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET);
+	writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+	       ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET);

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +99 -0

+	/*
+	 * DLL Parameter Setting:
+	 * Termination: Enable R/W
+	 * Phase Delay for DQS Cleaning: 180' Shift
+	 */
+	writel(mem.control1, &dmc0->phycontrol1);
+	writel(mem.control1, &dmc1->phycontrol1);
+
+	/*
+	 * ZQ Calibration
+	 * Termination: Disable
+	 * Auto Calibration Start: Enable
+	 */
+	writel(mem.zqcontrol, &dmc0->phyzqcontrol);
+	writel(mem.zqcontrol, &dmc1->phyzqcontrol);
+	sdelay(0x100000);
+
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	phy_control_reset(1, dmc0);
+	phy_control_reset(0, dmc0);
+	phy_control_reset(1, dmc1);
+	phy_control_reset(0, dmc1);
+
+	/* Set DLL Parameters */
+	writel(mem.control1, &dmc0->phycontrol1);
+	writel(mem.control1, &dmc1->phycontrol1);
+
+	/* DLL Start */
+	writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc0->phycontrol0);
+	writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc1->phycontrol0);
+
+	writel(mem.control2, &dmc0->phycontrol2);
+	writel(mem.control2, &dmc1->phycontrol2);
+
+	/* Set Clock Ratio of Bus clock to Memory Clock */
+	writel(mem.concontrol, &dmc0->concontrol);
+	writel(mem.concontrol, &dmc1->concontrol);
+
+	/*
+	 * Memor Burst length: 8
+	 * Number of chips: 2
+	 * Memory Bus width: 32 bit
+	 * Memory Type: DDR3
+	 * Additional Latancy for PLL: 1 Cycle
+	 */
+	writel(mem.memcontrol, &dmc0->memcontrol);
+	writel(mem.memcontrol, &dmc1->memcontrol);
+
+	writel(mem.memconfig0, &dmc0->memconfig0);
+	writel(mem.memconfig1, &dmc0->memconfig1);
+	writel(mem.memconfig0, &dmc1->memconfig0);
+	writel(mem.memconfig1, &dmc1->memconfig1);
+
+	/* Config Precharge Policy */
+	writel(mem.prechconfig, &dmc0->prechconfig);
+	writel(mem.prechconfig, &dmc1->prechconfig);
+	/*
+	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
+	 * Values as per Memory AC Parameters
+	 */
+	writel(mem.timingref, &dmc0->timingref);
+	writel(mem.timingrow, &dmc0->timingrow);
+	writel(mem.timingdata, &dmc0->timingdata);
+	writel(mem.timingpower, &dmc0->timingpower);
+
+	writel(mem.timingref, &dmc1->timingref);
+	writel(mem.timingrow, &dmc1->timingrow);
+	writel(mem.timingdata, &dmc1->timingdata);
+	writel(mem.timingpower, &dmc1->timingpower);
+
+	/* Chip0: NOP Command: Assert and Hold CKE to high level */
+	writel(DIRECT_CMD_NOP, &dmc0->directcmd);
+	writel(DIRECT_CMD_NOP, &dmc1->directcmd);
+	sdelay(0x100000);
+
+	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	dmc_config_mrs(dmc0, 0);
+	dmc_config_mrs(dmc1, 0);
+	sdelay(0x100000);
+
+	/* Chip0: ZQINIT */
+	writel(DIRECT_CMD_ZQ, &dmc0->directcmd);
+	writel(DIRECT_CMD_ZQ, &dmc1->directcmd);
+	sdelay(0x100000);
+
+	writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc0->directcmd);
+	writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc1->directcmd);
+	sdelay(0x100000);
+
+	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	dmc_config_mrs(dmc0, 1);
+	dmc_config_mrs(dmc1, 1);
+	sdelay(0x100000);
+
+	/* Chip1: ZQINIT */
+	writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc0->directcmd);

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +1 -0

+}

arch/arm/cpu/armv7/exynos/exynos4_setup.h renamed from board/samsung/origen/origen_setup.h +1 -5

similarity index 86%
rename from board/samsung/origen/origen_setup.h
rename to arch/arm/cpu/armv7/exynos/exynos4_setup.h
index 926a4cc..bfb31b8 100644
@@ -1,5 +1,5 @@
 /*
- * Machine Specific Values for ORIGEN board based on S5PV310
+ * Machine Specific Values for EXYNOS4012 based board
  *
  * Copyright (C) 2011 Samsung Electronics
  *

@@ -102,10 +102,6 @@
 /* Bus Configuration Register Address */
 #define ASYNC_CONFIG		0x10010350
 
-/* MIU Config Register Offsets*/
-#define APB_SFR_INTERLEAVE_CONF_OFFSET	0x400
-#define APB_SFR_ARBRITATION_CONF_OFFSET		0xC00
-
 /* Offset for inform registers */
 #define INFORM0_OFFSET			0x800
 #define INFORM1_OFFSET			0x804

arch/arm/cpu/armv7/exynos/exynos4_setup.h renamed from board/samsung/origen/origen_setup.h +21 -0

+
+#define TZPC_DECPROT0SET_OFFSET	0x804
+#define TZPC_DECPROT1SET_OFFSET	0x810
+#define TZPC_DECPROT2SET_OFFSET	0x81C
+#define TZPC_DECPROT3SET_OFFSET	0x828
+
 /* CLK_SRC_CPU */
 #define MUX_HPM_SEL_MOUTAPLL		0x0
 #define MUX_HPM_SEL_SCLKMPLL		0x1

@@ -604,4 +613,82 @@
  * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
  */
 #define UFRACVAL_VAL		0x4
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE			0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET		0xFF
+
+/* DMC */
+#define DIRECT_CMD_NOP	0x07000000

arch/arm/cpu/armv7/exynos/exynos4_setup.h renamed from board/samsung/origen/origen_setup.h +53 -0

+		unsigned timingref;
+		unsigned timingrow;
+		unsigned timingdata;
+		unsigned timingpower;
+		unsigned zqcontrol;
+		unsigned control0;
+		unsigned control1;
+		unsigned control2;
+		unsigned concontrol;
+		unsigned prechconfig;
+		unsigned memcontrol;
+		unsigned memconfig0;
+		unsigned memconfig1;
+		unsigned dll_resync;
+		unsigned dll_on;
+};
+
+/* MIU */
+/* MIU Config Register Offsets*/
+#define APB_SFR_INTERLEAVE_CONF_OFFSET	0x400
+#define APB_SFR_ARBRITATION_CONF_OFFSET	0xC00
+#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET	0x800
+#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET	0x808
+#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET	0x810
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET	0x818
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET	0x820
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET	0x828
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET	0x830
+
+#ifdef CONFIG_ORIGEN
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+#define APB_SFR_INTERLEAVE_CONF_VAL	0x20001507
+#define APB_SFR_ARBRITATION_CONF_VAL	0x00000001
+#endif
+
+#define INTERLEAVE_ADDR_MAP_START_ADDR	0x40000000
+#define INTERLEAVE_ADDR_MAP_END_ADDR	0xbfffffff
+#define INTERLEAVE_ADDR_MAP_EN		0x00000001
+
+#ifdef CONFIG_MIU_1BIT_INTERLEAVED
+/* Interleave_bit0: 0xC*/
+#define APB_SFR_INTERLEAVE_CONF_VAL	0x0000000c
+#endif
+#ifdef CONFIG_MIU_2BIT_INTERLEAVED
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
+#define APB_SFR_INTERLEAVE_CONF_VAL	0x2000150c
+#endif
+#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR	0x40000000
+#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR		0x7fffffff
+#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR	0x80000000
+#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR		0xbfffffff
+/* Enable SME0 and SME1*/
+#define APB_SFR_SLV_ADDR_MAP_CONF_VAL		0x00000006
 #endif

arch/arm/cpu/armv7/exynos/exynos5_setup.h renamed from board/samsung/smdk5250/setup.h +13 -15

similarity index 96%
rename from board/samsung/smdk5250/setup.h
rename to arch/arm/cpu/armv7/exynos/exynos5_setup.h
index eb91d13..8f36c16 100644
@@ -93,17 +93,17 @@
 #define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)
 
 /* MEMCONFIG0 register bit fields */
-#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED     (1 << 12)
-#define DMC_MEMCONFIGx_CHIP_COL_10              (3 << 8)
-#define DMC_MEMCONFIGx_CHIP_ROW_14              (2 << 4)
-#define DMC_MEMCONFIGx_CHIP_ROW_15              (3 << 4)
-#define DMC_MEMCONFIGx_CHIP_BANK_8              (3 << 0)
-
-#define DMC_MEMBASECONFIGx_CHIP_BASE(x)         (x << 16)
-#define DMC_MEMBASECONFIGx_CHIP_MASK(x)         (x << 0)
+#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED     (1 << 12)
+#define DMC_MEMCONFIGX_CHIP_COL_10              (3 << 8)
+#define DMC_MEMCONFIGX_CHIP_ROW_14              (2 << 4)
+#define DMC_MEMCONFIGX_CHIP_ROW_15              (3 << 4)
+#define DMC_MEMCONFIGX_CHIP_BANK_8              (3 << 0)
+
+#define DMC_MEMBASECONFIGX_CHIP_BASE(x)         (x << 16)
+#define DMC_MEMBASECONFIGX_CHIP_MASK(x)         (x << 0)
 #define DMC_MEMBASECONFIG_VAL(x)        (       \
-	DMC_MEMBASECONFIGx_CHIP_BASE(x) |       \
-	DMC_MEMBASECONFIGx_CHIP_MASK(0x780)     \
+	DMC_MEMBASECONFIGX_CHIP_BASE(x) |       \
+	DMC_MEMBASECONFIGX_CHIP_MASK(0x780)     \
 )
 
 #define DMC_MEMBASECONFIG0_VAL  DMC_MEMBASECONFIG_VAL(0x40)

@@ -513,9 +513,11 @@ enum {
  *			which the DMC uses to decide how to split a memory
  *			chunk into smaller chunks to support concurrent
  *			accesses; may vary across boards.
+ * @param reset         Reset DDR PHY during initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+			int reset);
 
 /*
  * Configure ZQ I/O interface

@@ -562,8 +564,4 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
  * @param ddr_mode	Type of DDR memory
  */
 void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
-
-void sdelay(unsigned long);
-void mem_ctrl_init(void);
-void system_clock_init(void);
 #endif

arch/arm/cpu/armv7/exynos/lowlevel_init.c new file +0 -0

new file mode 100644
index 0000000..44d6522

arch/arm/cpu/armv7/exynos/lowlevel_init.c new file +68 -0

+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
+#include <asm/arch/tzpc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include "common_setup.h"
+
+/* These are the things we can do during low-level init */
+enum {
+	DO_WAKEUP	= 1 << 0,
+	DO_CLOCKS	= 1 << 1,
+	DO_MEM_RESET	= 1 << 2,
+	DO_UART		= 1 << 3,
+};
+
+int do_lowlevel_init(void)
+{
+	uint32_t reset_status;
+	int actions = 0;
+
+	arch_cpu_init();
+
+	reset_status = get_reset_status();
+
+	switch (reset_status) {
+	case S5P_CHECK_SLEEP:
+		actions = DO_CLOCKS | DO_WAKEUP;
+		break;
+	case S5P_CHECK_DIDLE:
+	case S5P_CHECK_LPA:
+		actions = DO_WAKEUP;
+		break;
+	default:
+		/* This is a normal boot (not a wake from sleep) */
+		actions = DO_CLOCKS | DO_MEM_RESET;
+	}
+
+	if (actions & DO_CLOCKS) {
+		system_clock_init();
+		mem_ctrl_init(actions & DO_MEM_RESET);
+		tzpc_init();
+	}
+
+	return actions & DO_WAKEUP;
+}

arch/arm/cpu/armv7/exynos/spl_boot.c renamed from board/samsung/smdk5250/spl_boot.c +33 -11

similarity index 73%
rename from board/samsung/smdk5250/spl_boot.c
rename to arch/arm/cpu/armv7/exynos/spl_boot.c
index 83275f1..32cb6b7 100644
@@ -23,13 +23,18 @@
 #include<common.h>
 #include<config.h>
 
-#include <asm/arch-exynos/dmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
 #include <asm/arch/spl.h>
 
+#include "common_setup.h"
 #include "clock_init.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+#define OM_STAT         (0x1f << 1)
+
 /* Index into irom ptr table */
 enum index {
 	MMC_INDEX,

@@ -54,6 +59,7 @@ void *get_irom_func(int index)
 	return (void *)*(u32 *)irom_ptr_table[index];
 }
 
+#ifdef CONFIG_USB_BOOTING
 /*
  * Set/clear program flow prediction and return the previous state.
  */

@@ -67,6 +73,7 @@ static int config_branch_prediction(int set_cr_z)
 
 	return cr & CR_Z;
 }
+#endif
 
 /*
 * Copy U-boot from mmc to RAM:

@@ -75,35 +82,42 @@ static int config_branch_prediction(int set_cr_z)
 */
 void copy_uboot_to_ram(void)
 {
-	int is_cr_z_set;
-	unsigned int sec_boot_check;
 	enum boot_mode bootmode = BOOT_MODE_OM;
 
-	u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst);
-	u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst);
+	u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
+	u32 offset = 0, size = 0;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
 	u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
 	void (*end_bootop_from_emmc)(void);
+#endif
+#ifdef CONFIG_USB_BOOTING
 	u32 (*usb_copy)(void);
+	int is_cr_z_set;
+	unsigned int sec_boot_check;
 
 	/* Read iRAM location to check for secondary USB boot mode */
 	sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
 	if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
 		bootmode = BOOT_MODE_USB;
+#endif
 
 	if (bootmode == BOOT_MODE_OM)
-		bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
+		bootmode = readl(samsung_get_base_power()) & OM_STAT;
 
 	switch (bootmode) {
+#ifdef CONFIG_SPI_BOOTING
 	case BOOT_MODE_SERIAL:
-		spi_copy = get_irom_func(SPI_INDEX);
-		spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
-			 CONFIG_SYS_TEXT_BASE);
+		offset = SPI_FLASH_UBOOT_POS;
+		size = CONFIG_BL2_SIZE;
+		copy_bl2 = get_irom_func(SPI_INDEX);
 		break;
+#endif
 	case BOOT_MODE_MMC:
+		offset = BL2_START_OFFSET;
+		size = BL2_SIZE_BLOC_COUNT;
 		copy_bl2 = get_irom_func(MMC_INDEX);
-		copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
-			 CONFIG_SYS_TEXT_BASE);
 		break;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
 	case BOOT_MODE_EMMC:
 		/* Set the FSYS1 clock divisor value for EMMC boot */
 		emmc_boot_clk_div_set();

@@ -114,6 +128,8 @@ void copy_uboot_to_ram(void)
 		copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
 		end_bootop_from_emmc();
 		break;
+#endif
+#ifdef CONFIG_USB_BOOTING
 	case BOOT_MODE_USB:
 		/*
 		 * iROM needs program flow prediction to be disabled

@@ -124,14 +140,50 @@ void copy_uboot_to_ram(void)
 		usb_copy();
 		config_branch_prediction(is_cr_z_set);
 		break;
+#endif
 	default:
 		break;
 	}
+
+	if (copy_bl2)
+		copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
+}
+

arch/arm/cpu/armv7/exynos/spl_boot.c renamed from board/samsung/smdk5250/spl_boot.c +20 -0

+ * Set up the U-Boot global_data pointer
+ *
+ * This sets the address of the global data, and sets up basic values.
+ *
+ * @param gdp   Value to give to gd
+ */
+static void setup_global_data(gd_t *gdp)
+{
+	gd = gdp;
+	memzero((void *)gd, sizeof(gd_t));
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	gd->have_console = 1;
 }
 
 void board_init_f(unsigned long bootflag)
 {
+	__aligned(8) gd_t local_gd;
 	__attribute__((noreturn)) void (*uboot)(void);
+
+	setup_global_data(&local_gd);
+
+	if (do_lowlevel_init())
+		power_exit_wakeup();
+
 	copy_uboot_to_ram();
 
 	/* Jump to U-Boot image */

board/samsung/origen/Makefile +0 -4

index 3a885a5..63c8b46 100644
@@ -24,19 +24,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-SOBJS	:= mem_setup.o
-SOBJS	+= lowlevel_init.o
-
 ifndef CONFIG_SPL_BUILD
 COBJS	+= origen.o
 endif
 
-ifdef CONFIG_SPL_BUILD

Dear Rajeshwari,

Quoted 243 lines · Rajeshwari Shinde

This patch performs the following:

1) Convert the assembly code for memory and clock initialization to C code.
2) Move the memory and clock init codes from board/samsung to arch/arm
3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code
4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5.
5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main.
6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250.

TEST: Tested SD-MMC boot on SMDK5250 and Origen.
Tested USB and SPI boot on SMDK5250
Compile tested for SMDKV310.

Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes in V2:
- Rebased on latest u-boot-samsung tree.
- Incorporated review comments from Minkyu Kang.

 arch/arm/cpu/armv7/exynos/Makefile                 |   17 +-
 .../arm/cpu/armv7/exynos}/clock_init.h             |    0
 arch/arm/cpu/armv7/exynos/clock_init_exynos4.c     |   94 +++++
 .../arm/cpu/armv7/exynos/clock_init_exynos5.c      |   27 +-
 arch/arm/cpu/armv7/exynos/common_setup.h           |   43 ++
 .../arm/cpu/armv7/exynos}/dmc_common.c             |    7 +-
 .../arm/cpu/armv7/exynos}/dmc_init_ddr3.c          |   17 +-
 arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c       |  295 ++++++++++++++
 .../arm/cpu/armv7/exynos/exynos4_setup.h           |   97 +++++-
 .../arm/cpu/armv7/exynos/exynos5_setup.h           |   28 +-
 arch/arm/cpu/armv7/exynos/lowlevel_init.c          |   72 ++++
 .../arm/cpu/armv7/exynos}/spl_boot.c               |   77 +++-
 board/samsung/origen/Makefile                      |   11 +-
 board/samsung/origen/lowlevel_init.S               |  357 -----------------
 board/samsung/origen/mem_setup.S                   |  421 --------------------
 board/samsung/origen/mmc_boot.c                    |   58 ---
 board/samsung/smdk5250/Makefile                    |   14 +-
 board/samsung/smdkv310/Makefile                    |   10 +-
 board/samsung/smdkv310/lowlevel_init.S             |  414 -------------------
 board/samsung/smdkv310/mem_setup.S                 |  365 -----------------
 board/samsung/smdkv310/mmc_boot.c                  |   60 ---
 include/configs/exynos5250-dt.h                    |    8 +-
 include/configs/origen.h                           |    9 +-
 include/configs/smdkv310.h                         |    8 +-
 24 files changed, 743 insertions(+), 1766 deletions(-)
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/clock_init.h (100%)
 create mode 100644 arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
 rename board/samsung/smdk5250/clock_init.c => arch/arm/cpu/armv7/exynos/clock_init_exynos5.c (97%)
 create mode 100644 arch/arm/cpu/armv7/exynos/common_setup.h
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_common.c (97%)
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_init_ddr3.c (96%)
 create mode 100644 arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c
 rename board/samsung/origen/origen_setup.h => arch/arm/cpu/armv7/exynos/exynos4_setup.h (86%)
 rename board/samsung/smdk5250/setup.h => arch/arm/cpu/armv7/exynos/exynos5_setup.h (96%)
 create mode 100644 arch/arm/cpu/armv7/exynos/lowlevel_init.c
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/spl_boot.c (73%)
 delete mode 100644 board/samsung/origen/lowlevel_init.S
 delete mode 100644 board/samsung/origen/mem_setup.S
 delete mode 100644 board/samsung/origen/mmc_boot.c
 delete mode 100644 board/samsung/smdkv310/lowlevel_init.S
 delete mode 100644 board/samsung/smdkv310/mem_setup.S
 delete mode 100644 board/samsung/smdkv310/mmc_boot.c

arch/arm/cpu/armv7/exynos/Makefile +13 -4

index b2f9152..4661155 100644
@@ -22,10 +22,19 @@ include $(TOPDIR)/config.mk
 
 LIB  = $(obj)lib$(SOC).o
 
-COBJS        += clock.o power.o soc.o system.o pinmux.o tzpc.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+COBJS-y      += clock.o power.o soc.o system.o pinmux.o tzpc.o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_EXYNOS5)      += clock_init_exynos5.o
+COBJS-$(CONFIG_EXYNOS5)      += dmc_common.o dmc_init_ddr3.o
+COBJS-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+COBJS-y      += spl_boot.o
+COBJS-y      += lowlevel_init.o
+endif
+
+COBJS   := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
 
 all:  $(obj).depend $(LIB)
 

arch/arm/cpu/armv7/exynos/clock_init.h renamed from board/samsung/smdk5250/clock_init.h +0 -0

similarity index 100%
rename from board/samsung/smdk5250/clock_init.h
rename to arch/arm/cpu/armv7/exynos/clock_init.h

arch/arm/cpu/armv7/exynos/clock_init_exynos4.c new file +94 -0

new file mode 100644
index 0000000..bee0b5c
@@ -0,0 +1,94 @@
+/*
+ * Clock Initialization for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+void system_clock_init(void)
+{
+     struct exynos4_clock *clk = (struct exynos4_clock *)EXYNOS4_CLOCK_BASE;
+
+     writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+
+     sdelay(0x10000);
+
+     writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+     writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+     writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
+     writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
+     writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
+     writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+     writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
+     writel(CLK_SRC_CAM_VAL, &clk->src_cam);
+     writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
+     writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
+     writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
+
+     sdelay(0x10000);
+
+     writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+     writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+     writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
+     writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
+     writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
+     writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
+     writel(CLK_DIV_TOP_VAL, &clk->div_top);
+     writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+     writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+     writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+     writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
+     writel(CLK_DIV_CAM_VAL, &clk->div_cam);
+     writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
+     writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
+     writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
+
+     /* Set PLL locktime */
+     writel(PLL_LOCKTIME, &clk->apll_lock);
+     writel(PLL_LOCKTIME, &clk->mpll_lock);
+     writel(PLL_LOCKTIME, &clk->epll_lock);
+     writel(PLL_LOCKTIME, &clk->vpll_lock);
+
+     writel(APLL_CON1_VAL, &clk->apll_con1);
+     writel(APLL_CON0_VAL, &clk->apll_con0);
+     writel(MPLL_CON1_VAL, &clk->mpll_con1);
+     writel(MPLL_CON0_VAL, &clk->mpll_con0);
+     writel(EPLL_CON1_VAL, &clk->epll_con1);
+     writel(EPLL_CON0_VAL, &clk->epll_con0);
+     writel(VPLL_CON1_VAL, &clk->vpll_con1);
+     writel(VPLL_CON0_VAL, &clk->vpll_con0);
+
+     sdelay(0x30000);
+}

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +10 -9

similarity index 97%
rename from board/samsung/smdk5250/clock_init.c
rename to arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index b288e66..3bdbab9 100644
@@ -31,7 +31,8 @@
 #include <asm/arch/dwmmc.h>
 
 #include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 
 #define FSYS1_MMC0_DIV_MASK  0xff0f
 #define FSYS1_MMC0_DIV_VAL   0x0701

@@ -214,10 +215,10 @@ struct mem_timings mem_timings[] = {
                      DMC_MEMCONTROL_BL_8 |
                      DMC_MEMCONTROL_PZQ_DISABLE |
                      DMC_MEMCONTROL_MRR_BYTE_7_0,
-             .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-                     DMC_MEMCONFIGx_CHIP_COL_10 |
-                     DMC_MEMCONFIGx_CHIP_ROW_15 |
-                     DMC_MEMCONFIGx_CHIP_BANK_8,
+             .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+                     DMC_MEMCONFIGX_CHIP_COL_10 |
+                     DMC_MEMCONFIGX_CHIP_ROW_15 |
+                     DMC_MEMCONFIGX_CHIP_BANK_8,
              .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
              .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
              .prechconfig_tp_cnt = 0xff,

@@ -317,10 +318,10 @@ struct mem_timings mem_timings[] = {
                      DMC_MEMCONTROL_BL_8 |
                      DMC_MEMCONTROL_PZQ_DISABLE |
                      DMC_MEMCONTROL_MRR_BYTE_7_0,
-             .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-                     DMC_MEMCONFIGx_CHIP_COL_10 |
-                     DMC_MEMCONFIGx_CHIP_ROW_15 |
-                     DMC_MEMCONFIGx_CHIP_BANK_8,
+             .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+                     DMC_MEMCONFIGX_CHIP_COL_10 |
+                     DMC_MEMCONFIGX_CHIP_ROW_15 |
+                     DMC_MEMCONFIGX_CHIP_BANK_8,
              .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
              .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
              .prechconfig_tp_cnt = 0xff,

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c struct arm_clk_ratios *get_arm_ratios(void) · line 381

Quoted 5 lines

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +1 -1

@@ -377,7 +378,7 @@ struct arm_clk_ratios *get_arm_ratios(void)
      int i;
 
      if (clock_get_mem_selection(&mem_type, &frequency_mhz,
-                                     &arm_freq, &mem_manuf))
+                                 &arm_freq, &mem_manuf))

I can't understand, why should match open parenthesis? I think this is unnecessary and unrelated changes.

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c struct arm_clk_ratios *get_arm_ratios(void) · line 382

Quoted 1 line

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +0 -0

              ;

And this if statement have no effect.

Quoted 193 lines

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +3 -3

      for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
              i++, arm_ratio++) {

@@ -401,12 +402,12 @@ struct mem_timings *clock_get_mem_timings(void)
      int i;
 
      if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
-                                             &arm_freq, &mem_manuf)) {
+                                  &arm_freq, &mem_manuf)) {
              for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
                              i++, mem++) {
                      if (mem->mem_type == mem_type &&
-                                     mem->frequency_mhz == frequency_mhz &&
-                                     mem->mem_manuf == mem_manuf)
+                         mem->frequency_mhz == frequency_mhz &&
+                         mem->mem_manuf == mem_manuf)
                              return mem;
              }
      }

arch/arm/cpu/armv7/exynos/common_setup.h new file +43 -0

new file mode 100644
index 0000000..59ee192
@@ -0,0 +1,43 @@
+/*
+ * Common APIs for EXYNOS based board
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Memory initialization
+ *
+ * @param reset     Reset PHY during initialization.
+ */
+void mem_ctrl_init(int reset);
+
+ /* System Clock initialization */
+void system_clock_init(void);
+
+/*
+ * Init subsystems according to the reset status
+ *
+ * @return 0 for a normal boot, non-zero for a resume
+ */
+int do_lowlevel_init(void);
+
+void sdelay(unsigned long);

arch/arm/cpu/armv7/exynos/dmc_common.c renamed from board/samsung/smdk5250/dmc_common.c +4 -3

similarity index 97%
rename from board/samsung/smdk5250/dmc_common.c
rename to arch/arm/cpu/armv7/exynos/dmc_common.c
index 109602a..645f57e 100644
@@ -26,7 +26,8 @@
 #include <asm/arch/spl.h>
 
 #include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 
 #define ZQ_INIT_TIMEOUT      10000
 

@@ -175,7 +176,7 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
      writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
 }
 
-void mem_ctrl_init()
+void mem_ctrl_init(int reset)
 {
      struct spl_machine_param *param = spl_get_machine_params();
      struct mem_timings *mem;

@@ -185,7 +186,7 @@ void mem_ctrl_init()
 
      /* If there are any other memory variant, add their init call below */
      if (param->mem_type == DDR_MODE_DDR3) {
-             ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
+             ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
              if (ret) {
                      /* will hang if failed to init memory control */
                      while (1)

arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c renamed from board/samsung/smdk5250/dmc_init_ddr3.c +10 -7

similarity index 96%
rename from board/samsung/smdk5250/dmc_init_ddr3.c
rename to arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index e050790..4f31977 100644
@@ -27,7 +27,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dmc.h>
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 #include "clock_init.h"
 
 #define RDLVL_COMPLETE_TIMEOUT       10000

@@ -40,7 +41,8 @@ static void reset_phy_ctrl(void)
      writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+                    int reset)
 {
      unsigned int val;
      struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;

@@ -51,7 +53,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
      phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
      dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
 
-     reset_phy_ctrl();
+     if (reset)
+             reset_phy_ctrl();
 
      /* Set Impedance Output Driver */
      val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |

@@ -100,14 +103,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
      /* Start DLL locking */
      writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-             &phy0_ctrl->phy_con12);
+            &phy0_ctrl->phy_con12);
      writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-             &phy1_ctrl->phy_con12);
+            &phy1_ctrl->phy_con12);
 
      update_reset_dll(dmc, DDR_MODE_DDR3);
 
      writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-             &dmc->concontrol);
+            &dmc->concontrol);
 
      /* Memory Channel Inteleaving Size */
      writel(mem->iv_size, &dmc->ivcontrol);

@@ -119,7 +122,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
      /* Precharge Configuration */
      writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-             &dmc->prechconfig);
+            &dmc->prechconfig);
 
      /* Power Down mode Configuration */
      writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +21 -0

new file mode 100644
index 0000000..868a986
@@ -0,0 +1,295 @@
+/*
+ * Memory setup for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 31

Quoted 10 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +10 -0

+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dmc.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+#define SET_MIU

Then, we always set MIU. right?
If so, is it needed?

Quoted 6 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +6 -0

+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 47

Quoted 10 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +10 -0

+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
+
+struct mem_timings mem = {
+             .direct_cmd_msr = {

Is it right indentaion?
Looks two depth of tabs.

Quoted 56 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +56 -0

+                     0x00020000, 0x00030000, 0x00010002, 0x00000328
+             },
+#ifdef CONFIG_ORIGEN
+             .timingref = 0x000000BB,
+             .timingrow = 0x4046654f,
+             .timingdata = 0x46400506,
+             .timingpower = 0x52000A3C,
+#else
+             .timingref = 0x000000BC,
+#ifdef DRAM_CLK_330
+             .timingrow = 0x3545548d,
+             .timingdata = 0x45430506,
+             .timingpower = 0x4439033c,
+#endif
+#ifdef DRAM_CLK_400
+             .timingrow = 0x45430506,
+             .timingdata = 0x56500506,
+             .timingpower = 0x5444033d,
+#endif
+#endif
+             .zqcontrol = 0xE3855703,
+             .control0 = 0x71101008,
+             .control1 = 0xe0000086,
+             .control2 = 0x00000000,
+             .concontrol = 0x0fff301a,
+             .prechconfig = 0xff000000,
+             .memcontrol = 0x00312640,
+#ifdef CONFIG_MIU_LINEAR
+             /*
+              * Memory Configuration Chip 0
+              * Address Mapping: linear
+              * Number of Column address Bits: 10 bits
+              * Number of Rows Address Bits: 14
+              * Number of Banks: 8
+              */
+             .memconfig0 = 0x40e01323,
+             /*
+              * Memory Configuration Chip 1
+              * Address Mapping: Linear
+              * Number of Column address Bits: 10 bits
+              * Number of Rows Address Bits: 14
+              * Number of Banks: 8
+              */
+             .memconfig1 = 0x60e01323,
+#else
+             /*
+             * Memory Configuration Chip 0
+             * Address Mapping: Interleaved
+             * Number of Column address Bits: 10 bits
+              * Number of Rows Address Bits: 14
+             * Number of Banks: 8
+             */
+             .memconfig0 = 0x20e01323,
+             /*
+             * Memory Configuration Chip 1
+             * Address Mapping: Interleaved

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 109

Quoted 6 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +6 -0

+             * Number of Column address Bits: 10 bits
+             * Number of Rows Address Bits: 14
+             * Number of Banks: 8
+             */
+             .memconfig1 = 0x40e01323,
+#endif

I reqeusted to fix magic codes.

Quoted 25 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +24 -0

+             .dll_resync = 3,
+             .dll_on = 1,
+};
+
+static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
+{
+     if (ctrl_no) {
+             writel((mem.control1 | (1 << mem.dll_resync)),
+                    &dmc->phycontrol1);
+             writel((mem.control1 | (0 << mem.dll_resync)),
+                    &dmc->phycontrol1);
+     } else {
+             writel((mem.control0 | (0 << mem.dll_on)),
+                    &dmc->phycontrol0);
+             writel((mem.control0 | (1 << mem.dll_on)),
+                    &dmc->phycontrol0);
+     }
+}
+
+static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
+{
+     int i;
+     unsigned long mask = 0;
+

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 143

Quoted 10 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +10 -0

+     if (chip)
+             mask = DIRECT_CMD_CHIP1_SHIFT;
+
+     for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
+             writel(mem.direct_cmd_msr[i] | mask,
+                    &dmc->directcmd);
+     }
+}
+
+void mem_ctrl_init(int reset)

Why function prefixes are different?
phy, mem, dmc.. looks confused.
please fix it.

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 145

Quoted 2 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +2 -0

+{
+     struct exynos4_dmc *dmc0, *dmc1;

need blank line here.

Quoted 30 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +30 -0

+     /*
+      * Async bridge configuration at CPU_core:
+      * 1: half_sync
+      * 0: full_sync
+      */
+     writel(1, ASYNC_CONFIG);
+#ifdef SET_MIU
+#ifdef CONFIG_ORIGEN
+     /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+     writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+             APB_SFR_INTERLEAVE_CONF_OFFSET);
+     /* Update MIU Configuration */
+     writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +
+             APB_SFR_ARBRITATION_CONF_OFFSET);
+#else
+     writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+             APB_SFR_INTERLEAVE_CONF_OFFSET);
+     writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+            ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET);
+     writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+            ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET);
+     writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE +
+             ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
+#ifdef CONFIG_MIU_LINEAR
+     writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+            ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET);
+     writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+            ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET);
+     writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+            ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET);

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 185

Quoted 10 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +10 -0

+     writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+            ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET);
+     writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE +
+            ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
+#endif
+#endif
+#endif
+     /* DREX0 */
+     dmc0 = (struct exynos4_dmc *)EXYNOS4_DMC0_BASE;
+     dmc1 = (struct exynos4_dmc *)EXYNOS4_DMC1_BASE;

NAK.
please use samsung_get_base_dmc0/1()

Quoted 99 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +99 -0

+     /*
+      * DLL Parameter Setting:
+      * Termination: Enable R/W
+      * Phase Delay for DQS Cleaning: 180' Shift
+      */
+     writel(mem.control1, &dmc0->phycontrol1);
+     writel(mem.control1, &dmc1->phycontrol1);
+
+     /*
+      * ZQ Calibration
+      * Termination: Disable
+      * Auto Calibration Start: Enable
+      */
+     writel(mem.zqcontrol, &dmc0->phyzqcontrol);
+     writel(mem.zqcontrol, &dmc1->phyzqcontrol);
+     sdelay(0x100000);
+
+     /*
+      * Update DLL Information:
+      * Force DLL Resyncronization
+      */
+     phy_control_reset(1, dmc0);
+     phy_control_reset(0, dmc0);
+     phy_control_reset(1, dmc1);
+     phy_control_reset(0, dmc1);
+
+     /* Set DLL Parameters */
+     writel(mem.control1, &dmc0->phycontrol1);
+     writel(mem.control1, &dmc1->phycontrol1);
+
+     /* DLL Start */
+     writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc0->phycontrol0);
+     writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc1->phycontrol0);
+
+     writel(mem.control2, &dmc0->phycontrol2);
+     writel(mem.control2, &dmc1->phycontrol2);
+
+     /* Set Clock Ratio of Bus clock to Memory Clock */
+     writel(mem.concontrol, &dmc0->concontrol);
+     writel(mem.concontrol, &dmc1->concontrol);
+
+     /*
+      * Memor Burst length: 8
+      * Number of chips: 2
+      * Memory Bus width: 32 bit
+      * Memory Type: DDR3
+      * Additional Latancy for PLL: 1 Cycle
+      */
+     writel(mem.memcontrol, &dmc0->memcontrol);
+     writel(mem.memcontrol, &dmc1->memcontrol);
+
+     writel(mem.memconfig0, &dmc0->memconfig0);
+     writel(mem.memconfig1, &dmc0->memconfig1);
+     writel(mem.memconfig0, &dmc1->memconfig0);
+     writel(mem.memconfig1, &dmc1->memconfig1);
+
+     /* Config Precharge Policy */
+     writel(mem.prechconfig, &dmc0->prechconfig);
+     writel(mem.prechconfig, &dmc1->prechconfig);
+     /*
+      * TimingAref, TimingRow, TimingData, TimingPower Setting:
+      * Values as per Memory AC Parameters
+      */
+     writel(mem.timingref, &dmc0->timingref);
+     writel(mem.timingrow, &dmc0->timingrow);
+     writel(mem.timingdata, &dmc0->timingdata);
+     writel(mem.timingpower, &dmc0->timingpower);
+
+     writel(mem.timingref, &dmc1->timingref);
+     writel(mem.timingrow, &dmc1->timingrow);
+     writel(mem.timingdata, &dmc1->timingdata);
+     writel(mem.timingpower, &dmc1->timingpower);
+
+     /* Chip0: NOP Command: Assert and Hold CKE to high level */
+     writel(DIRECT_CMD_NOP, &dmc0->directcmd);
+     writel(DIRECT_CMD_NOP, &dmc1->directcmd);
+     sdelay(0x100000);
+
+     /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+     dmc_config_mrs(dmc0, 0);
+     dmc_config_mrs(dmc1, 0);
+     sdelay(0x100000);
+
+     /* Chip0: ZQINIT */
+     writel(DIRECT_CMD_ZQ, &dmc0->directcmd);
+     writel(DIRECT_CMD_ZQ, &dmc1->directcmd);
+     sdelay(0x100000);
+
+     writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc0->directcmd);
+     writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc1->directcmd);
+     sdelay(0x100000);
+
+     /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+     dmc_config_mrs(dmc0, 1);
+     dmc_config_mrs(dmc1, 1);
+     sdelay(0x100000);
+
+     /* Chip1: ZQINIT */
+     writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc0->directcmd);

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 294

Quoted 10 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +10 -0

+     writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc1->directcmd);
+     sdelay(0x100000);
+
+     phy_control_reset(1, dmc0);
+     phy_control_reset(1, dmc1);
+     sdelay(0x100000);
+
+     /* turn on DREX0, DREX1 */
+     writel((mem.concontrol | AREF_EN) , &dmc0->concontrol);
+     writel((mem.concontrol | AREF_EN), &dmc1->concontrol);

It looks redundant.
dmc0 and dmc1 is almost same.
why don't you make it function?

e.g)
dmc_init(dmc0);
dmc_init(dmc1);

Quoted 27 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +1 -0

+}

arch/arm/cpu/armv7/exynos/exynos4_setup.h renamed from board/samsung/origen/origen_setup.h +1 -5

similarity index 86%
rename from board/samsung/origen/origen_setup.h
rename to arch/arm/cpu/armv7/exynos/exynos4_setup.h
index 926a4cc..bfb31b8 100644
@@ -1,5 +1,5 @@
 /*
- * Machine Specific Values for ORIGEN board based on S5PV310
+ * Machine Specific Values for EXYNOS4012 based board
  *
  * Copyright (C) 2011 Samsung Electronics
  *

@@ -102,10 +102,6 @@
 /* Bus Configuration Register Address */
 #define ASYNC_CONFIG         0x10010350
 
-/* MIU Config Register Offsets*/
-#define APB_SFR_INTERLEAVE_CONF_OFFSET       0x400
-#define APB_SFR_ARBRITATION_CONF_OFFSET              0xC00
-
 /* Offset for inform registers */
 #define INFORM0_OFFSET                       0x800
 #define INFORM1_OFFSET                       0x804

arch/arm/cpu/armv7/exynos/exynos4_setup.h line 118

Quoted 2 lines

arch/arm/cpu/armv7/exynos/exynos4_setup.h renamed from board/samsung/origen/origen_setup.h +0 -0

@@ -121,6 +117,19 @@
 #define UBRDIV_OFFSET                0x28
 #define UFRACVAL_OFFSET              0x2C

Is it used?

arch/arm/cpu/armv7/exynos/exynos4_setup.h line 126

Quoted 8 lines

arch/arm/cpu/armv7/exynos/exynos4_setup.h renamed from board/samsung/origen/origen_setup.h +7 -0

+/* TZPC : Register Offsets */
+#define TZPC0_BASE           0x10110000
+#define TZPC1_BASE           0x10120000
+#define TZPC2_BASE           0x10130000
+#define TZPC3_BASE           0x10140000
+#define TZPC4_BASE           0x10150000
+#define TZPC5_BASE           0x10160000

ditto.

There are so many unused defines in this file.
please check and remove them.

Quoted 28 lines

arch/arm/cpu/armv7/exynos/exynos4_setup.h renamed from board/samsung/origen/origen_setup.h +21 -0

+
+#define TZPC_DECPROT0SET_OFFSET      0x804
+#define TZPC_DECPROT1SET_OFFSET      0x810
+#define TZPC_DECPROT2SET_OFFSET      0x81C
+#define TZPC_DECPROT3SET_OFFSET      0x828
+
 /* CLK_SRC_CPU */
 #define MUX_HPM_SEL_MOUTAPLL         0x0
 #define MUX_HPM_SEL_SCLKMPLL         0x1

@@ -604,4 +613,82 @@
  * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
  */
 #define UFRACVAL_VAL         0x4
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE                       0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET          0xFF
+
+/* DMC */
+#define DIRECT_CMD_NOP       0x07000000

arch/arm/cpu/armv7/exynos/exynos4_setup.h line 640

Quoted 10 lines

arch/arm/cpu/armv7/exynos/exynos4_setup.h renamed from board/samsung/origen/origen_setup.h +10 -0

+#define DIRECT_CMD_ZQ        0x0a000000
+#define DIRECT_CMD_CHIP1_SHIFT       (1 << 20)
+#define MEM_TIMINGS_MSR_COUNT        4
+#define CTRL_START   (1 << 0)
+#define CTRL_DLL_ON  (1 << 1)
+#define AREF_EN              (1 << 5)
+#define DRV_TYPE     (1 << 6)
+
+struct mem_timings {
+             unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];

fix indentation.

Quoted 117 lines

arch/arm/cpu/armv7/exynos/exynos4_setup.h renamed from board/samsung/origen/origen_setup.h +53 -0

+             unsigned timingref;
+             unsigned timingrow;
+             unsigned timingdata;
+             unsigned timingpower;
+             unsigned zqcontrol;
+             unsigned control0;
+             unsigned control1;
+             unsigned control2;
+             unsigned concontrol;
+             unsigned prechconfig;
+             unsigned memcontrol;
+             unsigned memconfig0;
+             unsigned memconfig1;
+             unsigned dll_resync;
+             unsigned dll_on;
+};
+
+/* MIU */
+/* MIU Config Register Offsets*/
+#define APB_SFR_INTERLEAVE_CONF_OFFSET       0x400
+#define APB_SFR_ARBRITATION_CONF_OFFSET      0xC00
+#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET      0x800
+#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET      0x808
+#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET        0x810
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET     0x818
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET       0x820
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET     0x828
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET       0x830
+
+#ifdef CONFIG_ORIGEN
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+#define APB_SFR_INTERLEAVE_CONF_VAL  0x20001507
+#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
+#endif
+
+#define INTERLEAVE_ADDR_MAP_START_ADDR       0x40000000
+#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
+#define INTERLEAVE_ADDR_MAP_EN               0x00000001
+
+#ifdef CONFIG_MIU_1BIT_INTERLEAVED
+/* Interleave_bit0: 0xC*/
+#define APB_SFR_INTERLEAVE_CONF_VAL  0x0000000c
+#endif
+#ifdef CONFIG_MIU_2BIT_INTERLEAVED
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
+#define APB_SFR_INTERLEAVE_CONF_VAL  0x2000150c
+#endif
+#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR    0x40000000
+#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR              0x7fffffff
+#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR    0x80000000
+#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR              0xbfffffff
+/* Enable SME0 and SME1*/
+#define APB_SFR_SLV_ADDR_MAP_CONF_VAL                0x00000006
 #endif

arch/arm/cpu/armv7/exynos/exynos5_setup.h renamed from board/samsung/smdk5250/setup.h +13 -15

similarity index 96%
rename from board/samsung/smdk5250/setup.h
rename to arch/arm/cpu/armv7/exynos/exynos5_setup.h
index eb91d13..8f36c16 100644
@@ -93,17 +93,17 @@
 #define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)
 
 /* MEMCONFIG0 register bit fields */
-#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED     (1 << 12)
-#define DMC_MEMCONFIGx_CHIP_COL_10              (3 << 8)
-#define DMC_MEMCONFIGx_CHIP_ROW_14              (2 << 4)
-#define DMC_MEMCONFIGx_CHIP_ROW_15              (3 << 4)
-#define DMC_MEMCONFIGx_CHIP_BANK_8              (3 << 0)
-
-#define DMC_MEMBASECONFIGx_CHIP_BASE(x)         (x << 16)
-#define DMC_MEMBASECONFIGx_CHIP_MASK(x)         (x << 0)
+#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED     (1 << 12)
+#define DMC_MEMCONFIGX_CHIP_COL_10              (3 << 8)
+#define DMC_MEMCONFIGX_CHIP_ROW_14              (2 << 4)
+#define DMC_MEMCONFIGX_CHIP_ROW_15              (3 << 4)
+#define DMC_MEMCONFIGX_CHIP_BANK_8              (3 << 0)
+
+#define DMC_MEMBASECONFIGX_CHIP_BASE(x)         (x << 16)
+#define DMC_MEMBASECONFIGX_CHIP_MASK(x)         (x << 0)
 #define DMC_MEMBASECONFIG_VAL(x)        (       \
-     DMC_MEMBASECONFIGx_CHIP_BASE(x) |       \
-     DMC_MEMBASECONFIGx_CHIP_MASK(0x780)     \
+     DMC_MEMBASECONFIGX_CHIP_BASE(x) |       \
+     DMC_MEMBASECONFIGX_CHIP_MASK(0x780)     \
 )
 
 #define DMC_MEMBASECONFIG0_VAL  DMC_MEMBASECONFIG_VAL(0x40)

@@ -513,9 +513,11 @@ enum {
  *                   which the DMC uses to decide how to split a memory
  *                   chunk into smaller chunks to support concurrent
  *                   accesses; may vary across boards.
+ * @param reset         Reset DDR PHY during initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+                     int reset);
 
 /*
  * Configure ZQ I/O interface

@@ -562,8 +564,4 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
  * @param ddr_mode   Type of DDR memory
  */
 void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
-
-void sdelay(unsigned long);
-void mem_ctrl_init(void);
-void system_clock_init(void);
 #endif

arch/arm/cpu/armv7/exynos/lowlevel_init.c new file +0 -0

new file mode 100644
index 0000000..44d6522

arch/arm/cpu/armv7/exynos/lowlevel_init.c line 4

Quoted 4 lines

arch/arm/cpu/armv7/exynos/lowlevel_init.c new file +4 -0

@@ -0,0 +1,72 @@
+/*
+ * Lowlevel setup for EXYNOS5 based board
+ *
+ * Copyright (C) 2013 Samsung Electronics

missing authors.

Quoted 186 lines

arch/arm/cpu/armv7/exynos/lowlevel_init.c new file +68 -0

+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
+#include <asm/arch/tzpc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include "common_setup.h"
+
+/* These are the things we can do during low-level init */
+enum {
+     DO_WAKEUP       = 1 << 0,
+     DO_CLOCKS       = 1 << 1,
+     DO_MEM_RESET    = 1 << 2,
+     DO_UART         = 1 << 3,
+};
+
+int do_lowlevel_init(void)
+{
+     uint32_t reset_status;
+     int actions = 0;
+
+     arch_cpu_init();
+
+     reset_status = get_reset_status();
+
+     switch (reset_status) {
+     case S5P_CHECK_SLEEP:
+             actions = DO_CLOCKS | DO_WAKEUP;
+             break;
+     case S5P_CHECK_DIDLE:
+     case S5P_CHECK_LPA:
+             actions = DO_WAKEUP;
+             break;
+     default:
+             /* This is a normal boot (not a wake from sleep) */
+             actions = DO_CLOCKS | DO_MEM_RESET;
+     }
+
+     if (actions & DO_CLOCKS) {
+             system_clock_init();
+             mem_ctrl_init(actions & DO_MEM_RESET);
+             tzpc_init();
+     }
+
+     return actions & DO_WAKEUP;
+}

arch/arm/cpu/armv7/exynos/spl_boot.c renamed from board/samsung/smdk5250/spl_boot.c +33 -11

similarity index 73%
rename from board/samsung/smdk5250/spl_boot.c
rename to arch/arm/cpu/armv7/exynos/spl_boot.c
index 83275f1..32cb6b7 100644
@@ -23,13 +23,18 @@
 #include<common.h>
 #include<config.h>
 
-#include <asm/arch-exynos/dmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
 #include <asm/arch/spl.h>
 
+#include "common_setup.h"
 #include "clock_init.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+#define OM_STAT         (0x1f << 1)
+
 /* Index into irom ptr table */
 enum index {
      MMC_INDEX,

@@ -54,6 +59,7 @@ void *get_irom_func(int index)
      return (void *)*(u32 *)irom_ptr_table[index];
 }
 
+#ifdef CONFIG_USB_BOOTING
 /*
  * Set/clear program flow prediction and return the previous state.
  */

@@ -67,6 +73,7 @@ static int config_branch_prediction(int set_cr_z)
 
      return cr & CR_Z;
 }
+#endif
 
 /*
 * Copy U-boot from mmc to RAM:

@@ -75,35 +82,42 @@ static int config_branch_prediction(int set_cr_z)
 */
 void copy_uboot_to_ram(void)
 {
-     int is_cr_z_set;
-     unsigned int sec_boot_check;
      enum boot_mode bootmode = BOOT_MODE_OM;
 
-     u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst);
-     u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst);
+     u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
+     u32 offset = 0, size = 0;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
      u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
      void (*end_bootop_from_emmc)(void);
+#endif
+#ifdef CONFIG_USB_BOOTING
      u32 (*usb_copy)(void);
+     int is_cr_z_set;
+     unsigned int sec_boot_check;
 
      /* Read iRAM location to check for secondary USB boot mode */
      sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
      if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
              bootmode = BOOT_MODE_USB;
+#endif
 
      if (bootmode == BOOT_MODE_OM)
-             bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
+             bootmode = readl(samsung_get_base_power()) & OM_STAT;
 
      switch (bootmode) {
+#ifdef CONFIG_SPI_BOOTING
      case BOOT_MODE_SERIAL:
-             spi_copy = get_irom_func(SPI_INDEX);
-             spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
-                      CONFIG_SYS_TEXT_BASE);
+             offset = SPI_FLASH_UBOOT_POS;
+             size = CONFIG_BL2_SIZE;
+             copy_bl2 = get_irom_func(SPI_INDEX);
              break;
+#endif
      case BOOT_MODE_MMC:
+             offset = BL2_START_OFFSET;
+             size = BL2_SIZE_BLOC_COUNT;
              copy_bl2 = get_irom_func(MMC_INDEX);
-             copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
-                      CONFIG_SYS_TEXT_BASE);
              break;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
      case BOOT_MODE_EMMC:
              /* Set the FSYS1 clock divisor value for EMMC boot */
              emmc_boot_clk_div_set();

@@ -114,6 +128,8 @@ void copy_uboot_to_ram(void)
              copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
              end_bootop_from_emmc();
              break;
+#endif
+#ifdef CONFIG_USB_BOOTING
      case BOOT_MODE_USB:
              /*
               * iROM needs program flow prediction to be disabled

@@ -124,14 +140,50 @@ void copy_uboot_to_ram(void)
              usb_copy();
              config_branch_prediction(is_cr_z_set);
              break;
+#endif
      default:
              break;
      }
+
+     if (copy_bl2)
+             copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
+}
+

arch/arm/cpu/armv7/exynos/spl_boot.c void copy_uboot_to_ram(void) · line 161

Quoted 10 lines

arch/arm/cpu/armv7/exynos/spl_boot.c renamed from board/samsung/smdk5250/spl_boot.c +10 -0

+void memzero(void *s, size_t n)
+{
+     char *ptr = s;
+     size_t i;
+
+     for (i = 0; i < n; i++)
+             *ptr++ = '\0';
+}
+
+/**

/*

Quoted 29 lines

arch/arm/cpu/armv7/exynos/spl_boot.c renamed from board/samsung/smdk5250/spl_boot.c +20 -0

+ * Set up the U-Boot global_data pointer
+ *
+ * This sets the address of the global data, and sets up basic values.
+ *
+ * @param gdp   Value to give to gd
+ */
+static void setup_global_data(gd_t *gdp)
+{
+     gd = gdp;
+     memzero((void *)gd, sizeof(gd_t));
+     gd->flags |= GD_FLG_RELOC;
+     gd->baudrate = CONFIG_BAUDRATE;
+     gd->have_console = 1;
 }
 
 void board_init_f(unsigned long bootflag)
 {
+     __aligned(8) gd_t local_gd;
      __attribute__((noreturn)) void (*uboot)(void);
+
+     setup_global_data(&local_gd);
+
+     if (do_lowlevel_init())
+             power_exit_wakeup();
+
      copy_uboot_to_ram();
 
      /* Jump to U-Boot image */

arch/arm/cpu/armv7/exynos/spl_boot.c void board_init_r(gd_t *id, ulong dest_addr) · line 204

Quoted 6 lines

arch/arm/cpu/armv7/exynos/spl_boot.c renamed from board/samsung/smdk5250/spl_boot.c +2 -1

@@ -148,4 +200,5 @@ void board_init_r(gd_t *id, ulong dest_addr)
      while (1)
              ;
 }
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+{}

unrelated change.

Quoted 16 lines

board/samsung/origen/Makefile +0 -4

index 3a885a5..63c8b46 100644
@@ -24,19 +24,12 @@ include $(TOPDIR)/config.mk
 
 LIB  = $(obj)lib$(BOARD).o
 
-SOBJS        := mem_setup.o
-SOBJS        += lowlevel_init.o
-
 ifndef CONFIG_SPL_BUILD
 COBJS        += origen.o
 endif
 
-ifdef CONFIG_SPL_BUILD

board/samsung/origen/Makefile include $(TOPDIR)/config.mk · line 35

Quoted 10 lines

board/samsung/origen/Makefile +2 -5

-COBJS        += mmc_boot.o
-endif
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
 
 ALL  +=$(obj).depend $(LIB)
 

Thanks,
Minkyu Kang.

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Dear Rajeshwari,

Quoted 243 lines · Rajeshwari Shinde

This patch performs the following:

1) Convert the assembly code for memory and clock initialization to C code.
2) Move the memory and clock init codes from board/samsung to arch/arm
3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code
4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5.
5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main.
6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250.

TEST: Tested SD-MMC boot on SMDK5250 and Origen.
Tested USB and SPI boot on SMDK5250
Compile tested for SMDKV310.

Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes in V2:
- Rebased on latest u-boot-samsung tree.
- Incorporated review comments from Minkyu Kang.

 arch/arm/cpu/armv7/exynos/Makefile                 |   17 +-
 .../arm/cpu/armv7/exynos}/clock_init.h             |    0
 arch/arm/cpu/armv7/exynos/clock_init_exynos4.c     |   94 +++++
 .../arm/cpu/armv7/exynos/clock_init_exynos5.c      |   27 +-
 arch/arm/cpu/armv7/exynos/common_setup.h           |   43 ++
 .../arm/cpu/armv7/exynos}/dmc_common.c             |    7 +-
 .../arm/cpu/armv7/exynos}/dmc_init_ddr3.c          |   17 +-
 arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c       |  295 ++++++++++++++
 .../arm/cpu/armv7/exynos/exynos4_setup.h           |   97 +++++-
 .../arm/cpu/armv7/exynos/exynos5_setup.h           |   28 +-
 arch/arm/cpu/armv7/exynos/lowlevel_init.c          |   72 ++++
 .../arm/cpu/armv7/exynos}/spl_boot.c               |   77 +++-
 board/samsung/origen/Makefile                      |   11 +-
 board/samsung/origen/lowlevel_init.S               |  357 -----------------
 board/samsung/origen/mem_setup.S                   |  421 --------------------
 board/samsung/origen/mmc_boot.c                    |   58 ---
 board/samsung/smdk5250/Makefile                    |   14 +-
 board/samsung/smdkv310/Makefile                    |   10 +-
 board/samsung/smdkv310/lowlevel_init.S             |  414 -------------------
 board/samsung/smdkv310/mem_setup.S                 |  365 -----------------
 board/samsung/smdkv310/mmc_boot.c                  |   60 ---
 include/configs/exynos5250-dt.h                    |    8 +-
 include/configs/origen.h                           |    9 +-
 include/configs/smdkv310.h                         |    8 +-
 24 files changed, 743 insertions(+), 1766 deletions(-)
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/clock_init.h (100%)
 create mode 100644 arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
 rename board/samsung/smdk5250/clock_init.c => arch/arm/cpu/armv7/exynos/clock_init_exynos5.c (97%)
 create mode 100644 arch/arm/cpu/armv7/exynos/common_setup.h
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_common.c (97%)
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_init_ddr3.c (96%)
 create mode 100644 arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c
 rename board/samsung/origen/origen_setup.h => arch/arm/cpu/armv7/exynos/exynos4_setup.h (86%)
 rename board/samsung/smdk5250/setup.h => arch/arm/cpu/armv7/exynos/exynos5_setup.h (96%)
 create mode 100644 arch/arm/cpu/armv7/exynos/lowlevel_init.c
 rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/spl_boot.c (73%)
 delete mode 100644 board/samsung/origen/lowlevel_init.S
 delete mode 100644 board/samsung/origen/mem_setup.S
 delete mode 100644 board/samsung/origen/mmc_boot.c
 delete mode 100644 board/samsung/smdkv310/lowlevel_init.S
 delete mode 100644 board/samsung/smdkv310/mem_setup.S
 delete mode 100644 board/samsung/smdkv310/mmc_boot.c

arch/arm/cpu/armv7/exynos/Makefile +13 -4

index b2f9152..4661155 100644
@@ -22,10 +22,19 @@ include $(TOPDIR)/config.mk
 
 LIB  = $(obj)lib$(SOC).o
 
-COBJS        += clock.o power.o soc.o system.o pinmux.o tzpc.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+COBJS-y      += clock.o power.o soc.o system.o pinmux.o tzpc.o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_EXYNOS5)      += clock_init_exynos5.o
+COBJS-$(CONFIG_EXYNOS5)      += dmc_common.o dmc_init_ddr3.o
+COBJS-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+COBJS-y      += spl_boot.o
+COBJS-y      += lowlevel_init.o
+endif
+
+COBJS   := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
 
 all:  $(obj).depend $(LIB)
 

arch/arm/cpu/armv7/exynos/clock_init.h renamed from board/samsung/smdk5250/clock_init.h +0 -0

similarity index 100%
rename from board/samsung/smdk5250/clock_init.h
rename to arch/arm/cpu/armv7/exynos/clock_init.h

arch/arm/cpu/armv7/exynos/clock_init_exynos4.c new file +94 -0

new file mode 100644
index 0000000..bee0b5c
@@ -0,0 +1,94 @@
+/*
+ * Clock Initialization for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+void system_clock_init(void)
+{
+     struct exynos4_clock *clk = (struct exynos4_clock *)EXYNOS4_CLOCK_BASE;
+
+     writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+
+     sdelay(0x10000);
+
+     writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+     writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+     writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
+     writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
+     writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
+     writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+     writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
+     writel(CLK_SRC_CAM_VAL, &clk->src_cam);
+     writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
+     writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
+     writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
+
+     sdelay(0x10000);
+
+     writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+     writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+     writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
+     writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
+     writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
+     writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
+     writel(CLK_DIV_TOP_VAL, &clk->div_top);
+     writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+     writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+     writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+     writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
+     writel(CLK_DIV_CAM_VAL, &clk->div_cam);
+     writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
+     writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
+     writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
+
+     /* Set PLL locktime */
+     writel(PLL_LOCKTIME, &clk->apll_lock);
+     writel(PLL_LOCKTIME, &clk->mpll_lock);
+     writel(PLL_LOCKTIME, &clk->epll_lock);
+     writel(PLL_LOCKTIME, &clk->vpll_lock);
+
+     writel(APLL_CON1_VAL, &clk->apll_con1);
+     writel(APLL_CON0_VAL, &clk->apll_con0);
+     writel(MPLL_CON1_VAL, &clk->mpll_con1);
+     writel(MPLL_CON0_VAL, &clk->mpll_con0);
+     writel(EPLL_CON1_VAL, &clk->epll_con1);
+     writel(EPLL_CON0_VAL, &clk->epll_con0);
+     writel(VPLL_CON1_VAL, &clk->vpll_con1);
+     writel(VPLL_CON0_VAL, &clk->vpll_con0);
+
+     sdelay(0x30000);
+}

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +10 -9

similarity index 97%
rename from board/samsung/smdk5250/clock_init.c
rename to arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index b288e66..3bdbab9 100644
@@ -31,7 +31,8 @@
 #include <asm/arch/dwmmc.h>
 
 #include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 
 #define FSYS1_MMC0_DIV_MASK  0xff0f
 #define FSYS1_MMC0_DIV_VAL   0x0701

@@ -214,10 +215,10 @@ struct mem_timings mem_timings[] = {
                      DMC_MEMCONTROL_BL_8 |
                      DMC_MEMCONTROL_PZQ_DISABLE |
                      DMC_MEMCONTROL_MRR_BYTE_7_0,
-             .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-                     DMC_MEMCONFIGx_CHIP_COL_10 |
-                     DMC_MEMCONFIGx_CHIP_ROW_15 |
-                     DMC_MEMCONFIGx_CHIP_BANK_8,
+             .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+                     DMC_MEMCONFIGX_CHIP_COL_10 |
+                     DMC_MEMCONFIGX_CHIP_ROW_15 |
+                     DMC_MEMCONFIGX_CHIP_BANK_8,
              .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
              .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
              .prechconfig_tp_cnt = 0xff,

@@ -317,10 +318,10 @@ struct mem_timings mem_timings[] = {
                      DMC_MEMCONTROL_BL_8 |
                      DMC_MEMCONTROL_PZQ_DISABLE |
                      DMC_MEMCONTROL_MRR_BYTE_7_0,
-             .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-                     DMC_MEMCONFIGx_CHIP_COL_10 |
-                     DMC_MEMCONFIGx_CHIP_ROW_15 |
-                     DMC_MEMCONFIGx_CHIP_BANK_8,
+             .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+                     DMC_MEMCONFIGX_CHIP_COL_10 |
+                     DMC_MEMCONFIGX_CHIP_ROW_15 |
+                     DMC_MEMCONFIGX_CHIP_BANK_8,
              .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
              .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
              .prechconfig_tp_cnt = 0xff,

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c struct arm_clk_ratios *get_arm_ratios(void) · line 381

Quoted 5 lines

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +1 -1

@@ -377,7 +378,7 @@ struct arm_clk_ratios *get_arm_ratios(void)
      int i;
 
      if (clock_get_mem_selection(&mem_type, &frequency_mhz,
-                                     &arm_freq, &mem_manuf))
+                                 &arm_freq, &mem_manuf))

I can't understand, why should match open parenthesis? I think this is unnecessary and unrelated changes.

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c struct arm_clk_ratios *get_arm_ratios(void) · line 382

Quoted 1 line

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +0 -0

              ;

And this if statement have no effect.

Quoted 193 lines

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c renamed from board/samsung/smdk5250/clock_init.c +3 -3

      for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
              i++, arm_ratio++) {

@@ -401,12 +402,12 @@ struct mem_timings *clock_get_mem_timings(void)
      int i;
 
      if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
-                                             &arm_freq, &mem_manuf)) {
+                                  &arm_freq, &mem_manuf)) {
              for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
                              i++, mem++) {
                      if (mem->mem_type == mem_type &&
-                                     mem->frequency_mhz == frequency_mhz &&
-                                     mem->mem_manuf == mem_manuf)
+                         mem->frequency_mhz == frequency_mhz &&
+                         mem->mem_manuf == mem_manuf)
                              return mem;
              }
      }

arch/arm/cpu/armv7/exynos/common_setup.h new file +43 -0

new file mode 100644
index 0000000..59ee192
@@ -0,0 +1,43 @@
+/*
+ * Common APIs for EXYNOS based board
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Memory initialization
+ *
+ * @param reset     Reset PHY during initialization.
+ */
+void mem_ctrl_init(int reset);
+
+ /* System Clock initialization */
+void system_clock_init(void);
+
+/*
+ * Init subsystems according to the reset status
+ *
+ * @return 0 for a normal boot, non-zero for a resume
+ */
+int do_lowlevel_init(void);
+
+void sdelay(unsigned long);

arch/arm/cpu/armv7/exynos/dmc_common.c renamed from board/samsung/smdk5250/dmc_common.c +4 -3

similarity index 97%
rename from board/samsung/smdk5250/dmc_common.c
rename to arch/arm/cpu/armv7/exynos/dmc_common.c
index 109602a..645f57e 100644
@@ -26,7 +26,8 @@
 #include <asm/arch/spl.h>
 
 #include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 
 #define ZQ_INIT_TIMEOUT      10000
 

@@ -175,7 +176,7 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
      writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
 }
 
-void mem_ctrl_init()
+void mem_ctrl_init(int reset)
 {
      struct spl_machine_param *param = spl_get_machine_params();
      struct mem_timings *mem;

@@ -185,7 +186,7 @@ void mem_ctrl_init()
 
      /* If there are any other memory variant, add their init call below */
      if (param->mem_type == DDR_MODE_DDR3) {
-             ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
+             ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
              if (ret) {
                      /* will hang if failed to init memory control */
                      while (1)

arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c renamed from board/samsung/smdk5250/dmc_init_ddr3.c +10 -7

similarity index 96%
rename from board/samsung/smdk5250/dmc_init_ddr3.c
rename to arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index e050790..4f31977 100644
@@ -27,7 +27,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dmc.h>
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 #include "clock_init.h"
 
 #define RDLVL_COMPLETE_TIMEOUT       10000

@@ -40,7 +41,8 @@ static void reset_phy_ctrl(void)
      writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+                    int reset)
 {
      unsigned int val;
      struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;

@@ -51,7 +53,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
      phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
      dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
 
-     reset_phy_ctrl();
+     if (reset)
+             reset_phy_ctrl();
 
      /* Set Impedance Output Driver */
      val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |

@@ -100,14 +103,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
      /* Start DLL locking */
      writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-             &phy0_ctrl->phy_con12);
+            &phy0_ctrl->phy_con12);
      writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-             &phy1_ctrl->phy_con12);
+            &phy1_ctrl->phy_con12);
 
      update_reset_dll(dmc, DDR_MODE_DDR3);
 
      writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-             &dmc->concontrol);
+            &dmc->concontrol);
 
      /* Memory Channel Inteleaving Size */
      writel(mem->iv_size, &dmc->ivcontrol);

@@ -119,7 +122,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
      /* Precharge Configuration */
      writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-             &dmc->prechconfig);
+            &dmc->prechconfig);
 
      /* Power Down mode Configuration */
      writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +21 -0

new file mode 100644
index 0000000..868a986
@@ -0,0 +1,295 @@
+/*
+ * Memory setup for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 31

Quoted 10 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +10 -0

+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dmc.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+#define SET_MIU

Then, we always set MIU. right?
If so, is it needed?

Quoted 6 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +6 -0

+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 47

Quoted 10 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +10 -0

+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
+
+struct mem_timings mem = {
+             .direct_cmd_msr = {

Is it right indentaion?
Looks two depth of tabs.

Quoted 52 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +52 -0

+                     0x00020000, 0x00030000, 0x00010002, 0x00000328
+             },
+#ifdef CONFIG_ORIGEN
+             .timingref = 0x000000BB,
+             .timingrow = 0x4046654f,
+             .timingdata = 0x46400506,
+             .timingpower = 0x52000A3C,
+#else
+             .timingref = 0x000000BC,
+#ifdef DRAM_CLK_330
+             .timingrow = 0x3545548d,
+             .timingdata = 0x45430506,
+             .timingpower = 0x4439033c,
+#endif
+#ifdef DRAM_CLK_400
+             .timingrow = 0x45430506,
+             .timingdata = 0x56500506,
+             .timingpower = 0x5444033d,
+#endif
+#endif
+             .zqcontrol = 0xE3855703,
+             .control0 = 0x71101008,
+             .control1 = 0xe0000086,
+             .control2 = 0x00000000,
+             .concontrol = 0x0fff301a,
+             .prechconfig = 0xff000000,
+             .memcontrol = 0x00312640,
+#ifdef CONFIG_MIU_LINEAR
+             /*
+              * Memory Configuration Chip 0
+              * Address Mapping: linear
+              * Number of Column address Bits: 10 bits
+              * Number of Rows Address Bits: 14
+              * Number of Banks: 8
+              */
+             .memconfig0 = 0x40e01323,
+             /*
+              * Memory Configuration Chip 1
+              * Address Mapping: Linear
+              * Number of Column address Bits: 10 bits
+              * Number of Rows Address Bits: 14
+              * Number of Banks: 8
+              */
+             .memconfig1 = 0x60e01323,
+#else
+             /*
+             * Memory Configuration Chip 0
+             * Address Mapping: Interleaved
+             * Number of Column address Bits: 10 bits
+              * Number of Rows Address Bits: 14
+             * Number of Banks: 8
+             */

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c line 109

Quoted 10 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +10 -0

+             .memconfig0 = 0x20e01323,
+             /*
+             * Memory Configuration Chip 1
+             * Address Mapping: Interleaved
+             * Number of Column address Bits: 10 bits
+             * Number of Rows Address Bits: 14
+             * Number of Banks: 8
+             */
+             .memconfig1 = 0x40e01323,
+#endif

I reqeusted to fix magic codes.

Quoted 30 lines

arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file +30 -0

+             .dll_resync = 3,
+             .dll_on = 1,
+};
+
+static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
+{
+     if (ctrl_no) {
+             writel((mem.control1 | (1 << mem.dll_resync)),
+                    &dmc->phycontrol1);
+             writel((mem.control1 | (0 << mem.dll_resync)),
+                    &dmc->phycontrol1);
+     } else {
+             writel((mem.control0 | (0 << mem.dll_on)),
+                    &dmc->phycontrol0);
+             writel((mem.control0 | (1 << mem.dll_on)),
+                    &dmc->phycontrol0);
+     }
+}
+
+static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
+{
+     int i;
+     unsigned long mask = 0;
+
+     if (chip)
+             mask = DIRECT_CMD_CHIP1_SHIFT;
+
+     for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
+             writel(mem.direct_cmd_msr[i] | mask,
+                    &dmc->directcmd);