EXYNOS: Convert Assembly code to c and make it common

index 6375a81..5d3bda2 100644
@@ -140,3 +140,53 @@ void set_hw_thermal_trip(void)
 		setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
 	}
 }
+
+static uint32_t exynos5_get_reset_status(void)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	return power->inform1;
+}
+
+static uint32_t exynos4_get_reset_status(void)
+{
+	struct exynos4_power *power =
+		(struct exynos4_power *)samsung_get_base_power();
+
+	return power->inform1;
+}
+
+uint32_t get_reset_status(void)
+{
+	if (cpu_is_exynos5())
+		return exynos5_get_reset_status();
+	else
+		return  exynos4_get_reset_status();
+}
+
+static void exynos5_power_exit_wakeup(void)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+	typedef void (*resume_func)(void);
+
+	((resume_func)power->inform0)();
+}
+
+static void exynos4_power_exit_wakeup(void)
+{
+	struct exynos4_power *power =
+		(struct exynos4_power *)samsung_get_base_power();
+	typedef void (*resume_func)(void);
+
+	((resume_func)power->inform0)();
+}
+
+void power_exit_wakeup(void)
+{
+	if (cpu_is_exynos5())
+		exynos5_power_exit_wakeup();
+	else
+		exynos4_power_exit_wakeup();
+}

index 3549667..44ad8d3 100644
@@ -888,4 +888,16 @@ void set_ps_hold_ctrl(void);
  * source as XXTI
  */
 void set_xclkout(void);
+
+/*
+ *  Read inform1 to get the reset status.
+ *  @return: the value can be either S5P_CHECK_SLEEP or
+ *  S5P_CHECK_DIDLE or S5P_CHECK_LPA as stored in inform1
+ *  if none of these then its normal booting.
+ */
+uint32_t get_reset_status(void);
+
+
+/* Read the resume function and call it */
+void power_exit_wakeup(void);
 #endif

index 1c9eca2..6c7a052 100644
@@ -153,7 +153,7 @@
 #define COPY_BL2_FNPTR_ADDR	0x02020030
 
 /* specific .lds file */
-#define CONFIG_SPL_LDSCRIPT	"board/samsung/smdk5250/smdk5250-uboot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
 #define CONFIG_SPL_TEXT_BASE	0x02023400
 #define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
 

index bd499b4..2042062 100644
@@ -408,9 +408,49 @@ static int exynos4_mmc_config(int peripheral, int flags)
 	return 0;
 }
 
+static void exynos4_uart_config(int peripheral)
+{
+	struct exynos4_gpio_part1 *gpio1 =
+		(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+	struct s5p_gpio_bank *bank;
+	int i, start, count;
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+		bank = &gpio1->a0;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART1:
+		bank = &gpio1->a0;
+		start = 4;
+		count = 4;
+		break;
+	case PERIPH_ID_UART2:
+		bank = &gpio1->a1;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART3:
+		bank = &gpio1->a1;
+		start = 4;
+		count = 2;
+		break;
+	}
+	for (i = start; i < start + count; i++) {
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+	}
+}
 static int exynos4_pinmux_config(int peripheral, int flags)
 {
 	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+		exynos4_uart_config(peripheral);
+		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
 	case PERIPH_ID_I2C2:

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index e179911..f71a463 100644
@@ -36,6 +36,7 @@
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
 
 /* Keep L2 Cache Disabled */
 #define CONFIG_L2_OFF			1

index 5e43066..db78127 100644
@@ -36,6 +36,7 @@
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
 
 /* Mach Type */
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMDKV310

similarity index 100%
rename from board/samsung/smdk5250/clock_init.h
rename to arch/arm/cpu/armv7/exynos/clock_init.h

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similarity index 97%
rename from board/samsung/smdk5250/dmc_common.c
rename to arch/arm/cpu/armv7/exynos/dmc_common.c
index 109602a..645f57e 100644
@@ -26,7 +26,8 @@
 #include <asm/arch/spl.h>
 
 #include "clock_init.h"
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 
 #define ZQ_INIT_TIMEOUT	10000
 

@@ -175,7 +176,7 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
 	writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
 }
 
-void mem_ctrl_init()
+void mem_ctrl_init(int reset)
 {
 	struct spl_machine_param *param = spl_get_machine_params();
 	struct mem_timings *mem;

@@ -185,7 +186,7 @@ void mem_ctrl_init()
 
 	/* If there are any other memory variant, add their init call below */
 	if (param->mem_type == DDR_MODE_DDR3) {
-		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
+		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
 		if (ret) {
 			/* will hang if failed to init memory control */
 			while (1)

similarity index 92%
rename from board/samsung/smdk5250/dmc_init_ddr3.c
rename to arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index e050790..e03d74b 100644
@@ -27,31 +27,36 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dmc.h>
-#include "setup.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
 #include "clock_init.h"
 
 #define RDLVL_COMPLETE_TIMEOUT	10000
 
 static void reset_phy_ctrl(void)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
 
 	writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
 	writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+		       int reset)
 {
 	unsigned int val;
 	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
 	struct exynos5_dmc *dmc;
 	int i;
 
-	phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
-	phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
-	dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
+	phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
+	phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
+							+ DMC_OFFSET);
+	dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
 
-	reset_phy_ctrl();
+	if (reset)
+		reset_phy_ctrl();
 
 	/* Set Impedance Output Driver */
 	val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |

@@ -100,14 +105,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
 	/* Start DLL locking */
 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&phy0_ctrl->phy_con12);
+	       &phy0_ctrl->phy_con12);
 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&phy1_ctrl->phy_con12);
+	       &phy1_ctrl->phy_con12);
 
 	update_reset_dll(dmc, DDR_MODE_DDR3);
 
 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-		&dmc->concontrol);
+	       &dmc->concontrol);
 
 	/* Memory Channel Inteleaving Size */
 	writel(mem->iv_size, &dmc->ivcontrol);

@@ -119,7 +124,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 
 	/* Precharge Configuration */
 	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-		&dmc->prechconfig);
+	       &dmc->prechconfig);
 
 	/* Power Down mode Configuration */
 	writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |

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similarity index 96%
rename from board/samsung/smdk5250/setup.h
rename to arch/arm/cpu/armv7/exynos/exynos5_setup.h
index eb91d13..8f36c16 100644
@@ -93,17 +93,17 @@
 #define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)
 
 /* MEMCONFIG0 register bit fields */
-#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED     (1 << 12)
-#define DMC_MEMCONFIGx_CHIP_COL_10              (3 << 8)
-#define DMC_MEMCONFIGx_CHIP_ROW_14              (2 << 4)
-#define DMC_MEMCONFIGx_CHIP_ROW_15              (3 << 4)
-#define DMC_MEMCONFIGx_CHIP_BANK_8              (3 << 0)
-
-#define DMC_MEMBASECONFIGx_CHIP_BASE(x)         (x << 16)
-#define DMC_MEMBASECONFIGx_CHIP_MASK(x)         (x << 0)
+#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED     (1 << 12)
+#define DMC_MEMCONFIGX_CHIP_COL_10              (3 << 8)
+#define DMC_MEMCONFIGX_CHIP_ROW_14              (2 << 4)
+#define DMC_MEMCONFIGX_CHIP_ROW_15              (3 << 4)
+#define DMC_MEMCONFIGX_CHIP_BANK_8              (3 << 0)
+
+#define DMC_MEMBASECONFIGX_CHIP_BASE(x)         (x << 16)
+#define DMC_MEMBASECONFIGX_CHIP_MASK(x)         (x << 0)
 #define DMC_MEMBASECONFIG_VAL(x)        (       \
-	DMC_MEMBASECONFIGx_CHIP_BASE(x) |       \
-	DMC_MEMBASECONFIGx_CHIP_MASK(0x780)     \
+	DMC_MEMBASECONFIGX_CHIP_BASE(x) |       \
+	DMC_MEMBASECONFIGX_CHIP_MASK(0x780)     \
 )
 
 #define DMC_MEMBASECONFIG0_VAL  DMC_MEMBASECONFIG_VAL(0x40)

@@ -513,9 +513,11 @@ enum {
  *			which the DMC uses to decide how to split a memory
  *			chunk into smaller chunks to support concurrent
  *			accesses; may vary across boards.
+ * @param reset         Reset DDR PHY during initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+			int reset);
 
 /*
  * Configure ZQ I/O interface

@@ -562,8 +564,4 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
  * @param ddr_mode	Type of DDR memory
  */
 void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
-
-void sdelay(unsigned long);
-void mem_ctrl_init(void);
-void system_clock_init(void);
 #endif

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index 36b98c8..8685c42 100644
@@ -40,8 +40,7 @@
 #define EXYNOS4_WATCHDOG_BASE		0x10060000
 #define EXYNOS4_TZPC_BASE		0x10110000
 #define EXYNOS4_MIU_BASE		0x10600000
-#define EXYNOS4_DMC0_BASE		0x10400000
-#define EXYNOS4_DMC1_BASE		0x10410000
+#define EXYNOS4_DMC_CTRL_BASE		0x10400000
 #define EXYNOS4_GPIO_PART2_BASE		0x11000000
 #define EXYNOS4_GPIO_PART1_BASE		0x11400000
 #define EXYNOS4_FIMD_BASE		0x11C00000

@@ -64,6 +63,7 @@
 #define EXYNOS4_DP_BASE			DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
 
 /* EXYNOS4X12 */
 #define EXYNOS4X12_GPIO_PART3_BASE	0x03860000

@@ -76,8 +76,7 @@
 #define EXYNOS4X12_SYSTIMER_BASE	0x10050000
 #define EXYNOS4X12_WATCHDOG_BASE	0x10060000
 #define EXYNOS4X12_TZPC_BASE		0x10110000
-#define EXYNOS4X12_DMC0_BASE		0x10600000
-#define EXYNOS4X12_DMC1_BASE		0x10610000
+#define EXYNOS4X12_DMC_CTRL_BASE	0x10600000
 #define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
 #define EXYNOS4X12_GPIO_PART2_BASE	0x11000000
 #define EXYNOS4X12_GPIO_PART1_BASE	0x11400000

@@ -99,6 +98,7 @@
 #define EXYNOS4X12_SPI_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
 
 /* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING		0x10000

@@ -112,8 +112,7 @@
 #define EXYNOS5_TZPC_BASE		0x10100000
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_ACE_SFR_BASE            0x10830000
-#define EXYNOS5_DMC_PHY0_BASE		0x10C00000
-#define EXYNOS5_DMC_PHY1_BASE		0x10C10000
+#define EXYNOS5_DMC_PHY_BASE		0x10C00000
 #define EXYNOS5_GPIO_PART3_BASE		0x10D10000
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000

@@ -237,6 +236,8 @@ SAMSUNG_BASE(power, POWER_BASE)
 SAMSUNG_BASE(spi, SPI_BASE)
 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
 SAMSUNG_BASE(tzpc, TZPC_BASE)
+SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
+SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
 #endif
 
 #endif	/* _EXYNOS4_CPU_H */

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