Skip to contentSkip to conversation

arm: exynos: fix clock calculation

PATCH Superseded Minkyu Kang 6 participants 9 messages Jul 5, 2013 – Jul 16, 2013

Subsystems (2)
Arm (32-bit) Arm Samsung Exynos
lore
Share & tools
lore

Minkyu Kang

author
#0 lore raw

PATCH 1/1 arm: exynos: fix clock calculation

There are differnce with clock calcuation by cpu variations. This patch will fix it according to user manual.

Signed-off-by Minkyu Kang <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>
---
 arch/arm/cpu/armv7/exynos/clock.c |   37 +++++++++++++++++++++++++++++++++----
 1 file changed, 33 insertions(+), 4 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +33 -4
index e1c4246..da43373 100644
@@ -85,6 +85,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 {
 	unsigned long m, p, s = 0, mask, fout;
+	unsigned int div;
 	unsigned int freq;
 	/*
 	 * APLL_CON: MIDV [25:16]

@@ -113,11 +114,39 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 		fout = (m + k / 65536) * (freq / (p * (1 << s)));
 	} else if (pllreg == VPLL) {
 		k = k & 0xfff;
-		/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
-		fout = (m + k / 1024) * (freq / (p * (1 << s)));
+
+		/*
+		 * Exynos4210
+		 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos4412
+		 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos5250
+		 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+		 */
+		if (proid_is_exynos4210())
+			div = 1024;
+		else if (proid_is_exynos4412())
+			div = 65535;
+		else if (proid_is_exynos5250())
+			div = 65536;
+		else
+			return 0;
+
+		fout = (m + k / div) * (freq / (p * (1 << s)));
 	} else {
-		/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
-		fout = m * (freq / (p * (1 << s)));
+		/*
+		 * Exynos4210
+		 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos4412 / Exynos5250
+		 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+		 */
+		if (proid_is_exynos4210())
+			fout = m * (freq / (p * (1 << s)));
+		else
+			fout = m * (freq / (p * (1 << (s - 1))));
 	}
 
 	return fout;
Signature · 5 lines
1.7.9.5

-- 
Thanks,
Minkyu Kang.
#1 lore raw

PATCH 1/1 arm: exynos: fix clock calculation

Hi Minkyu Kang,

Quoted 30 lines · Minkyu Kang

There are differnce with clock calcuation by cpu variations. This patch will fix it according to user manual.

Signed-off-by Minkyu Kang <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>
---
 arch/arm/cpu/armv7/exynos/clock.c |   37 +++++++++++++++++++++++++++++++++----
 1 file changed, 33 insertions(+), 4 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +4 -2
index e1c4246..da43373 100644
@@ -85,6 +85,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 {
        unsigned long m, p, s = 0, mask, fout;
+       unsigned int div;
        unsigned int freq;
        /*
         * APLL_CON: MIDV [25:16]

@@ -113,11 +114,39 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
                fout = (m + k / 65536) * (freq / (p * (1 << s)));
        } else if (pllreg == VPLL) {
                k = k & 0xfff;
-               /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
-               fout = (m + k / 1024) * (freq / (p * (1 << s)));
+
+               /*
+                * Exynos4210

arch/arm/cpu/armv7/exynos/clock.c static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) · line 129

Quoted 10 lines
arch/arm/cpu/armv7/exynos/clock.c +10 -0
+                * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+                *
+                * Exynos4412
+                * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+                *
+                * Exynos5250
+                * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+                */
+               if (proid_is_exynos4210())
+                       div = 1024;

Cannot we remove these hard codings for div?

Quoted 35 lines
arch/arm/cpu/armv7/exynos/clock.c +19 -3
+               else if (proid_is_exynos4412())
+                       div = 65535;
+               else if (proid_is_exynos5250())
+                       div = 65536;
+               else
+                       return 0;
+
+               fout = (m + k / div) * (freq / (p * (1 << s)));
        } else {
-               /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
-               fout = m * (freq / (p * (1 << s)));
+               /*
+                * Exynos4210
+                * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+                *
+                * Exynos4412 / Exynos5250
+                * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+                */
+               if (proid_is_exynos4210())
+                       fout = m * (freq / (p * (1 << s)));
+               else
+                       fout = m * (freq / (p * (1 << (s - 1))));
        }
 
        return fout;
--

1.7.9.5

--
Thanks,
Minkyu Kang.
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Signature · 2 lines
Regards,
Rajeshwari Shinde
author
#2 lore raw

PATCH v2 1/1 arm: exynos: fix clock calculation

There are differnce with clock calcuation by cpu variations. This patch will fix it according to user manual.

Signed-off-by Minkyu Kang <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes for v2:
- remove hard-coded constants.

 arch/arm/cpu/armv7/exynos/clock.c |   43 ++++++++++++++++++++++++++++++++-----
 1 file changed, 38 insertions(+), 5 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +38 -5
index e1c4246..9f07181 100644
@@ -27,6 +27,10 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/periph.h>
 
+#define PLL_DIV_1024	1024
+#define PLL_DIV_65535	65535
+#define PLL_DIV_65536	65536
+
 /* *
  * This structure is to store the src bit, div bit and prediv bit
  * positions of the peripheral clocks of the src and div registers

@@ -85,6 +89,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 {
 	unsigned long m, p, s = 0, mask, fout;
+	unsigned int div;
 	unsigned int freq;
 	/*
 	 * APLL_CON: MIDV [25:16]

@@ -110,14 +115,42 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 	if (pllreg == EPLL) {
 		k = k & 0xffff;
 		/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
-		fout = (m + k / 65536) * (freq / (p * (1 << s)));
+		fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
 	} else if (pllreg == VPLL) {
 		k = k & 0xfff;
-		/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
-		fout = (m + k / 1024) * (freq / (p * (1 << s)));
+
+		/*
+		 * Exynos4210
+		 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos4412
+		 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos5250
+		 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+		 */
+		if (proid_is_exynos4210())
+			div = PLL_DIV_1024;
+		else if (proid_is_exynos4412())
+			div = PLL_DIV_65535;
+		else if (proid_is_exynos5250())
+			div = PLL_DIV_65536;
+		else
+			return 0;
+
+		fout = (m + k / div) * (freq / (p * (1 << s)));
 	} else {
-		/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
-		fout = m * (freq / (p * (1 << s)));
+		/*
+		 * Exynos4210
+		 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos4412 / Exynos5250
+		 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+		 */
+		if (proid_is_exynos4210())
+			fout = m * (freq / (p * (1 << s)));
+		else
+			fout = m * (freq / (p * (1 << (s - 1))));
 	}
 
 	return fout;
Signature · 1 line
1.7.9.5
#3 lore raw

PATCH v2 1/1 arm: exynos: fix clock calculation

Looks fine to me.

Acked-by Rajeshwari Shinde<[email protected]>
Quoted 85 lines · Minkyu Kang

There are differnce with clock calcuation by cpu variations. This patch will fix it according to user manual.

Signed-off-by Minkyu Kang <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes for v2:
- remove hard-coded constants.

 arch/arm/cpu/armv7/exynos/clock.c |   43 ++++++++++++++++++++++++++++++++-----
 1 file changed, 38 insertions(+), 5 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +38 -6
index e1c4246..9f07181 100644
@@ -27,6 +27,10 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/periph.h>
 
+#define PLL_DIV_1024   1024
+#define PLL_DIV_65535  65535
+#define PLL_DIV_65536  65536
+
 /* *
  * This structure is to store the src bit, div bit and prediv bit
  * positions of the peripheral clocks of the src and div registers

@@ -85,6 +89,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 {
        unsigned long m, p, s = 0, mask, fout;
+       unsigned int div;
        unsigned int freq;
        /*
         * APLL_CON: MIDV [25:16]

@@ -110,14 +115,42 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
        if (pllreg == EPLL) {
                k = k & 0xffff;
                /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
-               fout = (m + k / 65536) * (freq / (p * (1 << s)));
+               fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
        } else if (pllreg == VPLL) {
                k = k & 0xfff;
-               /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
-               fout = (m + k / 1024) * (freq / (p * (1 << s)));
+
+               /*
+                * Exynos4210
+                * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+                *
+                * Exynos4412
+                * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+                *
+                * Exynos5250
+                * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+                */
+               if (proid_is_exynos4210())
+                       div = PLL_DIV_1024;
+               else if (proid_is_exynos4412())
+                       div = PLL_DIV_65535;
+               else if (proid_is_exynos5250())
+                       div = PLL_DIV_65536;
+               else
+                       return 0;
+
+               fout = (m + k / div) * (freq / (p * (1 << s)));
        } else {
-               /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
-               fout = m * (freq / (p * (1 << s)));
+               /*
+                * Exynos4210
+                * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+                *
+                * Exynos4412 / Exynos5250
+                * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+                */
+               if (proid_is_exynos4210())
+                       fout = m * (freq / (p * (1 << s)));
+               else
+                       fout = m * (freq / (p * (1 << (s - 1))));
        }
 
        return fout;
--

1.7.9.5

Signature · 2 lines
Regards,
Rajeshwari Shinde
author
#4 lore raw

PATCH v2 1/1 arm: exynos: fix clock calculation

Quoted 17 lines · Rajeshwari Birje

Looks fine to me.

Acked-by Rajeshwari Shinde<[email protected]>
Quoted 12 lines · Minkyu Kang

There are differnce with clock calcuation by cpu variations. This patch will fix it according to user manual.

Signed-off-by Minkyu Kang <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Changes for v2:
- remove hard-coded constants.

 arch/arm/cpu/armv7/exynos/clock.c |   43 ++++++++++++++++++++++++++++++++-----
 1 file changed, 38 insertions(+), 5 deletions(-)

applied to u-boot-samsung.

#5 lore raw

PATCH 1/1 arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.

In reply to Minkyu Kang

Provide proper setting for the APLL fout frequency calculation for Exynos4 based targets (especially Exynos4210 - Trats board).

Signed-off-by Lukasz Majewski <[email protected]>
Cc Minkyu Kang <[email protected]>
---
 arch/arm/cpu/armv7/exynos/clock.c |    9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +4 -5
index 9f07181..5a5cfa1 100644
@@ -141,18 +141,17 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 		fout = (m + k / div) * (freq / (p * (1 << s)));
 	} else {
 		/*
-		 * Exynos4210
+		 * Exynos4412 / Exynos5250
 		 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
 		 *
-		 * Exynos4412 / Exynos5250
+		 * Exynos4210
 		 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
 		 */
 		if (proid_is_exynos4210())
-			fout = m * (freq / (p * (1 << s)));
-		else
 			fout = m * (freq / (p * (1 << (s - 1))));
+		else
+			fout = m * (freq / (p * (1 << s)));
 	}
-
 	return fout;
 }
Signature · 1 line
1.7.10.4
#6 lore raw

PATCH 1/1 arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.

Dear Tom,

Please apply this patch to u-boot directly. I wish that this fix will be merged before release.

Quoted 11 lines · Lukasz Majewski

Provide proper setting for the APLL fout frequency calculation for Exynos4 based targets (especially Exynos4210 - Trats board).

Signed-off-by Lukasz Majewski <[email protected]>
Cc Minkyu Kang <[email protected]>
---
 arch/arm/cpu/armv7/exynos/clock.c |    9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)
Acked-by Minkyu Kang <[email protected]>

Thanks for patch.

Minkyu Kang.

Signature · 2 lines
from. prom.
www.promsoft.net
#7 lore raw

PATCH 1/1 arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.

In reply to Lukasz Majewski
Quoted 7 lines · Lukasz Majewski

Provide proper setting for the APLL fout frequency calculation for Exynos4 based targets (especially Exynos4210 - Trats board).

Signed-off-by Lukasz Majewski <[email protected]>
Cc Minkyu Kang <[email protected]>

This also fixes booting on snow.

Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>
Quoted 41 lines
---
 arch/arm/cpu/armv7/exynos/clock.c |    9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +4 -6
index 9f07181..5a5cfa1 100644
@@ -141,18 +141,17 @@ static int exynos_get_pll_clk(int pllreg, unsigned
 int r, unsigned int k)
                fout = (m + k / div) * (freq / (p * (1 << s)));
        } else {
                /*
-                * Exynos4210
+                * Exynos4412 / Exynos5250
                 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
                 *
-                * Exynos4412 / Exynos5250
+                * Exynos4210
                 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
                 */
                if (proid_is_exynos4210())
-                       fout = m * (freq / (p * (1 << s)));
-               else
                        fout = m * (freq / (p * (1 << (s - 1))));
+               else
+                       fout = m * (freq / (p * (1 << s)));
        }
-
        return fout;
 }
 
--

1.7.10.4

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

#8 lore raw

[U-Boot] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.

In reply to Lukasz Majewski
Quoted 9 lines · ??ukasz Majewski

Provide proper setting for the APLL fout frequency calculation for Exynos4 based targets (especially Exynos4210 - Trats board).

Signed-off-by Lukasz Majewski <[email protected]>
Cc Minkyu Kang <[email protected]>
Acked-by Minkyu Kang <[email protected]>
Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20130716/66563353/attachment.pgp>