ARM: DT cpu bindings updates

The introduction of the cpu-map topology node in the cpus node implies that cpus node might have children that are not cpu nodes. The DT parsing code needs updating otherwise it would check for cpu nodes properties in nodes that are not required to contain them, resulting in warnings that have no bearing on bindings defined in the dts source file.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm/kernel/devtree.c | 3 +++
 1 file changed, 3 insertions(+)

arch/arm/kernel/devtree.c +3 -0

index 5af04f6..904cad5 100644
@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
 	for_each_child_of_node(cpus, cpu) {
 		u32 hwid;
 
+		if (of_node_cmp(cpu->type, "cpu"))
+			continue;
+
 		pr_debug(" * %s...\n", cpu->full_name);
 		/*
 		 * A device tree containing CPU nodes with missing "reg"

Signature · 1 line

1.8.2.2

The introduction of the cpu-map topology node in the cpus node implies that cpus node might have children that are not cpu nodes. The DT parsing code needs updating otherwise it would check for cpu nodes properties in nodes that are not required to contain them, resulting in warnings that have no bearing on bindings defined in the dts source file.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm/kernel/devtree.c | 3 +++
 1 file changed, 3 insertions(+)

arch/arm/kernel/devtree.c +3 -1

index 5af04f6..904cad5 100644
@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
        for_each_child_of_node(cpus, cpu) {
                u32 hwid;
 
+               if (of_node_cmp(cpu->type, "cpu"))
+                       continue;
+
                pr_debug(" * %s...\n", cpu->full_name);
                /*
                 * A device tree containing CPU nodes with missing "reg"
--

1.8.2.2

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Quoted 5 lines · Lorenzo Pieralisi

The introduction of the cpu-map topology node in the cpus node implies that cpus node might have children that are not cpu nodes. The DT parsing code needs updating otherwise it would check for cpu nodes properties in nodes that are not required to contain them, resulting in warnings that have no bearing on bindings defined in the dts source file.

Great, so a new DT with cpu-map entries may not work with old kernels. Please check the behavior. This should go to stable kernels.

Rob

Quoted 28 lines

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm/kernel/devtree.c | 3 +++
 1 file changed, 3 insertions(+)

arch/arm/kernel/devtree.c +3 -1

index 5af04f6..904cad5 100644
@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
        for_each_child_of_node(cpus, cpu) {
                u32 hwid;
 
+               if (of_node_cmp(cpu->type, "cpu"))
+                       continue;
+
                pr_debug(" * %s...\n", cpu->full_name);
                /*
                 * A device tree containing CPU nodes with missing "reg"
--

1.8.2.2

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The __cpu_logical_map array is statically initialized to 0, which is a valid MPIDR value. To prevent issues with the current implementation, this patch defines an MPIDR_INVALID value, and statically initializes the __cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps() tmp_map array used to stash DT reg properties while parsing DT are initialized with the MPIDR_INVALID value as well for consistency.

Signed-off-by Lorenzo Pieralisi <[email protected]>

CC Will Deacon <[email protected]>

---
 arch/arm/include/asm/cputype.h  | 2 ++
 arch/arm/include/asm/smp_plat.h | 2 +-
 arch/arm/kernel/devtree.c       | 2 +-
 arch/arm/kernel/setup.c         | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

arch/arm/include/asm/cputype.h +2 -0

index 7652712..dba62cb 100644
@@ -32,6 +32,8 @@
 
 #define MPIDR_HWID_BITMASK 0xFFFFFF
 
+#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
+
 #define MPIDR_LEVEL_BITS 8
 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
 

arch/arm/include/asm/smp_plat.h +1 -1

index aaa61b6..e789832 100644
@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
 /*
  * Logical CPU mapping.
  */
-extern int __cpu_logical_map[];
+extern u32 __cpu_logical_map[];
 #define cpu_logical_map(cpu)	__cpu_logical_map[cpu]
 /*
  * Retrieve logical cpu index corresponding to a given MPIDR[23:0]

arch/arm/kernel/devtree.c +1 -1

index 904cad5..0905502 100644
@@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
 	u32 i, j, cpuidx = 1;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
+	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
 	bool bootcpu_valid = false;
 	cpus = of_find_node_by_path("/cpus");
 

arch/arm/kernel/setup.c +1 -1

index 6ae71b7..eeac924 100644
@@ -457,7 +457,7 @@ void notrace cpu_init(void)
 	    : "r14");
 }
 
-int __cpu_logical_map[NR_CPUS];
+u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
 
 void __init smp_setup_processor_id(void)
 {

Signature · 7 lines

1.8.2.2


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In order to extend the current cpu nodes bindings to newer CPUs inclusive of AArch64 and to update support for older ARM CPUs this patch updates device tree documentation for the cpu nodes bindings.

Main changes:
- adds 64-bit bindings
- define usage of #address-cells
- define 32/64 dts compatibility settings
- defines behaviour on pre and post v7 uniprocessor systems
- adds ARM 11MPcore specific reg property definition

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
 1 file changed, 412 insertions(+), 47 deletions(-)

Documentation/devicetree/bindings/arm/cpus.txt +412 -47

index f32494d..3fc0c11 100644
@@ -1,77 +1,442 @@
-* ARM CPUs binding description
+=================
+ARM CPUs bindings
+=================
 
 The device tree allows to describe the layout of CPUs in a system through
 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
 defining properties for every cpu.
 
-Bindings for CPU nodes follow the ePAPR standard, available from:
-
-http://devicetree.org
-
-For the ARM architecture every CPU node must contain the following properties:
-
-- device_type:	must be "cpu"
-- reg:		property matching the CPU MPIDR[23:0] register bits
-		reg[31:24] bits must be set to 0
-- compatible:	should be one of:
-		"arm,arm1020"
-		"arm,arm1020e"
-		"arm,arm1022"
-		"arm,arm1026"
-		"arm,arm720"
-		"arm,arm740"
-		"arm,arm7tdmi"
-		"arm,arm920"
-		"arm,arm922"
-		"arm,arm925"
-		"arm,arm926"
-		"arm,arm940"
-		"arm,arm946"
-		"arm,arm9tdmi"
-		"arm,cortex-a5"
-		"arm,cortex-a7"
-		"arm,cortex-a8"
-		"arm,cortex-a9"
-		"arm,cortex-a15"
-		"arm,arm1136"
-		"arm,arm1156"
-		"arm,arm1176"
-		"arm,arm11mpcore"
-		"faraday,fa526"
-		"intel,sa110"
-		"intel,sa1100"
-		"marvell,feroceon"
-		"marvell,mohawk"
-		"marvell,xsc3"
-		"marvell,xscale"
-
-Example:
+Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+
+https://www.power.org/documentation/epapr-version-1-1/
+
+with updates for 32-bit and 64-bit ARM systems provided in this document.
+
+================================
+Convention used in this document
+================================
+
+This document follows the conventions described in the ePAPR v1.1, with
+the addition:
+
+- square brackets define bitfields, eg reg[7:0] value of the bitfield in
+  the reg property contained in bits 7 down to 0
+
+=====================================
+cpus and cpu node bindings definition
+=====================================
+
+The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
+nodes to be present and contain the properties described below.
+
+- cpus node
+
+	Description: Container of cpu nodes
+
+	The node name must be "cpus".
+
+	A cpus node must define the following properties:
+
+	- #address-cells
+		Usage: required
+		Value type: <u32>
+
+		Definition depends on ARM architecture version and
+		configuration:
+
+			# On uniprocessor ARM architectures previous to v7
+			  value must be 0.
+			# On 32-bit ARM 11 MPcore, ARM v7 or later systems
+			  value must be 1.
+			# On ARM v8 64-bit systems value must be set to 1
+			  or 2. Refer to the cpu node's reg property
+			  description for allowed configurations.
+
+	- #size-cells
+		Usage: required
+		Value type: <u32>
+		Definition: must be set to 0
+
+- cpu node
+
+	Description: Describes a CPU in an ARM based system
+
+	PROPERTIES
+
+	- device_type
+		Usage: required
+		Value type: <string>
+		Definition: must be "cpu"
+	- reg
+		Usage and definition depend on ARM architecture version and
+		configuration:
+
+			# On uniprocessor ARM architectures previous to v7
+			  this property is optional since they do not define
+			  any register that provides a CPU identifier.
+			  Any value set in the reg property for these CPUs
+			  should be ignored.
+
+			# On ARM 11 MPcore based systems this property is
+			  required and matches the CPUID[11:0] register bits.
+
+			  Bits [11:0] in the reg cell must be set to
+			  bits [11:0] in CPU ID register.
+
+			  All other bits in the reg cell must be set to 0.
+
+			# On 32-bit ARM v7 or later systems this property is
+			  required and matches the CPU MPIDR[23:0] register
+			  bits.
+
+			  Bits [23:0] in the reg cell must be set to
+			  bits [23:0] in MPIDR.
+
+			  All other bits in the reg cell must be set to 0.
+
+			# On ARM v8 64-bit systems, where the reg property
+			  size can be 1 or 2 cells (as defined by cpus node's
+			  #address-cells property), this property is
+			  required and matches:
+
+			  - On systems running the OS in AArch32:
+
+			    * If the cpus node's #address-cells value is 2:
+
+			      The first reg cell must be set to 0.
+
+			      The second reg cell bits [23:0] must be set to
+			      bits [23:0] of MPIDR_EL1.
+
+			      All other bits in the reg cells must be set to 0.
+
+			    * If the cpus node's #address-cells value is 1:
+
+			      Bits [23:0] in the reg cell must be set to
+			      bits [23:0] in MPIDR_EL1.
+
+			      All other bits in the reg cell must be 0.
+
+			  - On systems running the OS in AArch64:
+
+			    * If the cpus node's #address-cells value is 2:
+
+			      The first reg cell bits [7:0] must be set to
+			      bits [39:32] of MPIDR_EL1.
+
+			      The second reg cell bits [23:0] must be set to
+			      bits [23:0] of MPIDR_EL1.
+
+			      All other bits in the reg cells must be set to 0.
+
+			    * If the cpus node's #address-cells value is 1:
+
+			      MPIDR_EL1[63:32] is 0 on all processors in the
+			      system.
+
+			      The reg cell bits [23:0] must be set to
+			      bits [23:0] of MPIDR_EL1.
+
+			      All other bits in the reg cell must be set to 0.
+
+	- compatible:
+		Usage: required
+		Value type: <string>
+		Definition: should be one of:
+			    "arm,arm710t"
+			    "arm,arm720t"
+			    "arm,arm740t"
+			    "arm,arm7ej-s"
+			    "arm,arm7tdmi"
+			    "arm,arm7tdmi-s"
+			    "arm,arm9es"
+			    "arm,arm9ej-s"
+			    "arm,arm920t"
+			    "arm,arm922t"
+			    "arm,arm925"
+			    "arm,arm926e-s"
+			    "arm,arm926ej-s"
+			    "arm,arm940t"
+			    "arm,arm946e-s"
+			    "arm,arm966e-s"
+			    "arm,arm968e-s"
+			    "arm,arm9tdmi"
+			    "arm,arm1020e"
+			    "arm,arm1020t"
+			    "arm,arm1022e"
+			    "arm,arm1026ej-s"
+			    "arm,arm1136j-s"
+			    "arm,arm1136jf-s"
+			    "arm,arm1156t2-s"
+			    "arm,arm1156t2f-s"
+			    "arm,arm1176jzf"
+			    "arm,arm1176jz-s"
+			    "arm,arm1176jzf-s"
+			    "arm,arm11mpcore"
+			    "arm,cortex-a5"
+			    "arm,cortex-a7"
+			    "arm,cortex-a8"
+			    "arm,cortex-a9"
+			    "arm,cortex-a15"
+			    "arm,cortex-a53"
+			    "arm,cortex-a57"
+			    "arm,cortex-m0"
+			    "arm,cortex-m0+"
+			    "arm,cortex-m1"
+			    "arm,cortex-m3"
+			    "arm,cortex-m4"
+			    "arm,cortex-r4"
+			    "arm,cortex-r5"
+			    "arm,cortex-r7"
+			    "faraday,fa526"
+			    "intel,sa110"
+			    "intel,sa1100"
+			    "marvell,feroceon"
+			    "marvell,mohawk"
+			    "marvell,pj4"
+			    "marvell,sheeva-v7"
+			    "marvell,xsc3"
+			    "marvell,xscale"
+			    "qcom,krait"
+			    "qcom,scorpion"
+	- enable-method
+		Value type: <stringlist>
+		Usage and definition depend on ARM architecture version and
+		configuration:
+			# On ARM v8 64-bit systems running the OS in AArch64,
+			  this property is required and must be one of:
+			     "spin-table"
+			     "psci"
+			# On ARM 32-bit systems or ARM v8 systems running
+			  the OS in AArch32 this property is prohibited.
+
+	- cpu-release-addr
+		Usage: required for systems that have an "enable-method"
+		       property value of "spin-table".
+		Value type: <prop-encoded-array>
+		Definition:
+			# On ARM v8 64-bit systems must be a two cell
+			  property identifying a 64-bit zero-initialised
+			  memory location.
+
+Example 1 (dual-cluster big.LITTLE system 32-bit):
 
 	cpus {
 		#size-cells = <0>;
 		#address-cells = <1>;
 
-		CPU0: cpu at 0 {
+		cpu at 0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
 		};
 
-		CPU1: cpu at 1 {
+		cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x1>;
 		};
 
-		CPU2: cpu at 100 {
+		cpu at 100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 		};
 
-		CPU3: cpu at 101 {
+		cpu at 101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 		};
 	};
+
+Example 2 (Cortex-A8 uniprocessor 32-bit system):
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a8";
+			reg = <0x0>;
+		};
+	};
+
+Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <0>;
+
+		cpu {
+			device_type = "cpu";
+			compatible = "arm,arm926ej-s";
+		};
+	};
+
+Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <2>;
+
+	cpu at 0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 10000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 10001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 10100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 10101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100000000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x0>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100000001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x1>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100000100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100000101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100010000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10000>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100010001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10001>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100010100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10100>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+
+	cpu at 100010101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x1 0x10101>;
+		enable-method = "spin-table";
+		cpu-release-addr = <0 0x20000000>;
+	};
+};
+
+Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <2>;
+
+	cpu at 0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+	};
+
+	cpu at 1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x1>;
+	};
+
+	cpu at 100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x100>;
+	};
+
+	cpu at 101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x101>;
+	};
+};

Signature · 1 line

1.8.2.2

In order to extend the current cpu nodes bindings to newer CPUs inclusive of AArch64 and to update support for older ARM CPUs this patch updates device tree documentation for the cpu nodes bindings.

Main changes:
- adds 64-bit bindings
- define usage of #address-cells
- define 32/64 dts compatibility settings
- defines behaviour on pre and post v7 uniprocessor systems
- adds ARM 11MPcore specific reg property definition

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
 1 file changed, 412 insertions(+), 47 deletions(-)

Documentation/devicetree/bindings/arm/cpus.txt +23 -0

+
+                           * If the cpus node's #address-cells value is 2:
+
+                             The first reg cell must be set to 0.
+
+                             The second reg cell bits [23:0] must be set to
+                             bits [23:0] of MPIDR_EL1.
+
+                             All other bits in the reg cells must be set to 0.
+
+                           * If the cpus node's #address-cells value is 1:
+
+                             Bits [23:0] in the reg cell must be set to
+                             bits [23:0] in MPIDR_EL1.
+
+                             All other bits in the reg cell must be 0.
+
+                         - On systems running the OS in AArch64:
+
+                           * If the cpus node's #address-cells value is 2:
+
+                             The first reg cell bits [7:0] must be set to
+                             bits [39:32] of MPIDR_EL1.

Documentation/devicetree/bindings/arm/cpus.txt +61 -0

+
+                             The reg cell bits [23:0] must be set to
+                             bits [23:0] of MPIDR_EL1.
+
+                             All other bits in the reg cell must be set to 0.
+
+       - compatible:
+               Usage: required
+               Value type: <string>
+               Definition: should be one of:
+                           "arm,arm710t"
+                           "arm,arm720t"
+                           "arm,arm740t"
+                           "arm,arm7ej-s"
+                           "arm,arm7tdmi"
+                           "arm,arm7tdmi-s"
+                           "arm,arm9es"
+                           "arm,arm9ej-s"
+                           "arm,arm920t"
+                           "arm,arm922t"
+                           "arm,arm925"
+                           "arm,arm926e-s"
+                           "arm,arm926ej-s"
+                           "arm,arm940t"
+                           "arm,arm946e-s"
+                           "arm,arm966e-s"
+                           "arm,arm968e-s"
+                           "arm,arm9tdmi"
+                           "arm,arm1020e"
+                           "arm,arm1020t"
+                           "arm,arm1022e"
+                           "arm,arm1026ej-s"
+                           "arm,arm1136j-s"
+                           "arm,arm1136jf-s"
+                           "arm,arm1156t2-s"
+                           "arm,arm1156t2f-s"
+                           "arm,arm1176jzf"
+                           "arm,arm1176jz-s"
+                           "arm,arm1176jzf-s"
+                           "arm,arm11mpcore"
+                           "arm,cortex-a5"
+                           "arm,cortex-a7"
+                           "arm,cortex-a8"
+                           "arm,cortex-a9"
+                           "arm,cortex-a15"
+                           "arm,cortex-a53"
+                           "arm,cortex-a57"
+                           "arm,cortex-m0"
+                           "arm,cortex-m0+"
+                           "arm,cortex-m1"
+                           "arm,cortex-m3"
+                           "arm,cortex-m4"
+                           "arm,cortex-r4"
+                           "arm,cortex-r5"
+                           "arm,cortex-r7"
+                           "faraday,fa526"
+                           "intel,sa110"
+                           "intel,sa1100"
+                           "marvell,feroceon"
+                           "marvell,mohawk"
+                           "marvell,pj4"

Quoted 3 lines · Lorenzo Pieralisi

In order to extend the current cpu nodes bindings to newer CPUs inclusive of AArch64 and to update support for older ARM CPUs this patch updates device tree documentation for the cpu nodes bindings.

Sorry for the long delay on this, but I'm still not happy with the binding here.

Quoted 11 lines

Main changes:
- adds 64-bit bindings
- define usage of #address-cells
- define 32/64 dts compatibility settings
- defines behaviour on pre and post v7 uniprocessor systems
- adds ARM 11MPcore specific reg property definition

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
 1 file changed, 412 insertions(+), 47 deletions(-)

[snip]

Documentation/devicetree/bindings/arm/cpus.txt line 102

Quoted 6 lines

Documentation/devicetree/bindings/arm/cpus.txt +6 -0

+                       # On ARM v8 64-bit systems, where the reg property
+                         size can be 1 or 2 cells (as defined by cpus node's
+                         #address-cells property), this property is
+                         required and matches:
+
+                         - On systems running the OS in AArch32:

The DTS cannot change based on 32-bit or 64-bit OS.

Quoted 32 lines

Documentation/devicetree/bindings/arm/cpus.txt +32 -0

+
+                           * If the cpus node's #address-cells value is 2:
+
+                             The first reg cell must be set to 0.
+
+                             The second reg cell bits [23:0] must be set to
+                             bits [23:0] of MPIDR_EL1.
+
+                             All other bits in the reg cells must be set to 0.
+
+                           * If the cpus node's #address-cells value is 1:
+
+                             Bits [23:0] in the reg cell must be set to
+                             bits [23:0] in MPIDR_EL1.
+
+                             All other bits in the reg cell must be 0.
+
+                         - On systems running the OS in AArch64:
+
+                           * If the cpus node's #address-cells value is 2:
+
+                             The first reg cell bits [7:0] must be set to
+                             bits [39:32] of MPIDR_EL1.
+
+                             The second reg cell bits [23:0] must be set to
+                             bits [23:0] of MPIDR_EL1.
+
+                             All other bits in the reg cells must be set to 0.
+
+                           * If the cpus node's #address-cells value is 1:
+
+                             MPIDR_EL1[63:32] is 0 on all processors in the

Quoted 1 line

+ system.

Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then #address-cells can be 1. You could say the upper bits are ignored and treated as 0. However, you should simplify all this and just mandate that #address-cells must be 2 for ARMv8 or more generally must match the size of the MPIDR. If we want to boot a 32-bit kernel, then the kernel will have to adapt to support this.

Quoted 65 lines

Documentation/devicetree/bindings/arm/cpus.txt +65 -0

+
+                             The reg cell bits [23:0] must be set to
+                             bits [23:0] of MPIDR_EL1.
+
+                             All other bits in the reg cell must be set to 0.
+
+       - compatible:
+               Usage: required
+               Value type: <string>
+               Definition: should be one of:
+                           "arm,arm710t"
+                           "arm,arm720t"
+                           "arm,arm740t"
+                           "arm,arm7ej-s"
+                           "arm,arm7tdmi"
+                           "arm,arm7tdmi-s"
+                           "arm,arm9es"
+                           "arm,arm9ej-s"
+                           "arm,arm920t"
+                           "arm,arm922t"
+                           "arm,arm925"
+                           "arm,arm926e-s"
+                           "arm,arm926ej-s"
+                           "arm,arm940t"
+                           "arm,arm946e-s"
+                           "arm,arm966e-s"
+                           "arm,arm968e-s"
+                           "arm,arm9tdmi"
+                           "arm,arm1020e"
+                           "arm,arm1020t"
+                           "arm,arm1022e"
+                           "arm,arm1026ej-s"
+                           "arm,arm1136j-s"
+                           "arm,arm1136jf-s"
+                           "arm,arm1156t2-s"
+                           "arm,arm1156t2f-s"
+                           "arm,arm1176jzf"
+                           "arm,arm1176jz-s"
+                           "arm,arm1176jzf-s"
+                           "arm,arm11mpcore"
+                           "arm,cortex-a5"
+                           "arm,cortex-a7"
+                           "arm,cortex-a8"
+                           "arm,cortex-a9"
+                           "arm,cortex-a15"
+                           "arm,cortex-a53"
+                           "arm,cortex-a57"
+                           "arm,cortex-m0"
+                           "arm,cortex-m0+"
+                           "arm,cortex-m1"
+                           "arm,cortex-m3"
+                           "arm,cortex-m4"
+                           "arm,cortex-r4"
+                           "arm,cortex-r5"
+                           "arm,cortex-r7"
+                           "faraday,fa526"
+                           "intel,sa110"
+                           "intel,sa1100"
+                           "marvell,feroceon"
+                           "marvell,mohawk"
+                           "marvell,pj4"
+                           "marvell,sheeva-v7"
+                           "marvell,xsc3"
+                           "marvell,xscale"
+                           "qcom,krait"

Documentation/devicetree/bindings/arm/cpus.txt line 206

Quoted 6 lines

Documentation/devicetree/bindings/arm/cpus.txt +6 -0

+                           "qcom,scorpion"
+       - enable-method
+               Value type: <stringlist>
+               Usage and definition depend on ARM architecture version and
+               configuration:
+                       # On ARM v8 64-bit systems running the OS in AArch64,

Again, the DTS can't depend on the OS type.

Documentation/devicetree/bindings/arm/cpus.txt line 211

Quoted 5 lines

Documentation/devicetree/bindings/arm/cpus.txt +5 -0

+                         this property is required and must be one of:
+                            "spin-table"
+                            "psci"
+                       # On ARM 32-bit systems or ARM v8 systems running
+                         the OS in AArch32 this property is prohibited.

I still don't get the distinction between 32 and 64 bit here. On 32-bit, you have 3 choices: psci, spin-table, or SoC specific. So make this property optional for 32-bit and mandatory for 64-bit.

Documentation/devicetree/bindings/arm/cpus.txt line 220

Quoted 9 lines

Documentation/devicetree/bindings/arm/cpus.txt +9 -0

+
+       - cpu-release-addr
+               Usage: required for systems that have an "enable-method"
+                      property value of "spin-table".
+               Value type: <prop-encoded-array>
+               Definition:
+                       # On ARM v8 64-bit systems must be a two cell
+                         property identifying a 64-bit zero-initialised
+                         memory location.

As I mentioned previously, isn't some wake-up method needed? Most systems will be in wfi or wfe rather than continuously spinning.

Quoted 6 lines · Rob Herring

Quoted 3 lines · Lorenzo Pieralisi

In order to extend the current cpu nodes bindings to newer CPUs inclusive of AArch64 and to update support for older ARM CPUs this patch updates device tree documentation for the cpu nodes bindings.

Quoted 1 line

Sorry for the long delay on this, but I'm still not happy with the binding here.

I had to ask Russell again to drop the bindings patches from the patch system, and this is not acceptable since two months have passed and the entire series was reviewed, acked and partially merged. I will review these bindings again but I would like to understand who should give the final go ahead to get these patches queued for upstreaming, I can't continue updating this stuff forever.

Quoted 21 lines

Quoted 11 lines

Main changes:
- adds 64-bit bindings
- define usage of #address-cells
- define 32/64 dts compatibility settings
- defines behaviour on pre and post v7 uniprocessor systems
- adds ARM 11MPcore specific reg property definition

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
 1 file changed, 412 insertions(+), 47 deletions(-)

[snip]

Quoted 6 lines

Documentation/devicetree/bindings/arm/cpus.txt +6 -0

+                       # On ARM v8 64-bit systems, where the reg property
+                         size can be 1 or 2 cells (as defined by cpus node's
+                         #address-cells property), this property is
+                         required and matches:
+
+                         - On systems running the OS in AArch32:

Quoted 1 line

The DTS cannot change based on 32-bit or 64-bit OS.

"On systems running the OS in AArch32" implies a dependency on the HW execution state. Since the DT is used to configure OSs I thought that could be a valid sentence. Unfortunately this stuff is not C, so I reiterate my point above, before changing it I would like to understand who should say the wording is ok otherwise we could argue forever.

Quoted 10 lines

Quoted 9 lines

Documentation/devicetree/bindings/arm/cpus.txt +9 -0

+
+       - cpu-release-addr
+               Usage: required for systems that have an "enable-method"
+                      property value of "spin-table".
+               Value type: <prop-encoded-array>
+               Definition:
+                       # On ARM v8 64-bit systems must be a two cell
+                         property identifying a 64-bit zero-initialised
+                         memory location.

Quoted 2 lines

As I mentioned previously, isn't some wake-up method needed? Most systems will be in wfi or wfe rather than continuously spinning.

Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some thought.

Quoted 7 lines · Lorenzo Pieralisi

Quoted 6 lines · Rob Herring

Quoted 3 lines · Lorenzo Pieralisi

In order to extend the current cpu nodes bindings to newer CPUs inclusive of AArch64 and to update support for older ARM CPUs this patch updates device tree documentation for the cpu nodes bindings.

Quoted 8 lines

Quoted 1 line

Sorry for the long delay on this, but I'm still not happy with the binding here.

I had to ask Russell again to drop the bindings patches from the patch system, and this is not acceptable since two months have passed and the entire series was reviewed, acked and partially merged. I will review these bindings again but I would like to understand who should give the final go ahead to get these patches queued for upstreaming, I can't continue updating this stuff forever.

Most of my comments are for 64-bit. So don't blame me that it had to be reverted. I said up front I was concerned about this change breaking things and it appears it did. New kernels must not require a new DT.

But yes, this should have been reviewed more quickly. We're working on a plan to help address DT binding reviews. We have not enforced that Grant and I must ack all bindings, but in this case you certainly need mine since I have reviewed it and if you want to me to pull it.

Quoted 21 lines

Quoted 21 lines

Quoted 11 lines

Main changes:
- adds 64-bit bindings
- define usage of #address-cells
- define 32/64 dts compatibility settings
- defines behaviour on pre and post v7 uniprocessor systems
- adds ARM 11MPcore specific reg property definition

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
 1 file changed, 412 insertions(+), 47 deletions(-)

[snip]

Quoted 6 lines

Documentation/devicetree/bindings/arm/cpus.txt +6 -0

+                       # On ARM v8 64-bit systems, where the reg property
+                         size can be 1 or 2 cells (as defined by cpus node's
+                         #address-cells property), this property is
+                         required and matches:
+
+                         - On systems running the OS in AArch32:

Quoted 7 lines

Quoted 1 line

The DTS cannot change based on 32-bit or 64-bit OS.

"On systems running the OS in AArch32" implies a dependency on the HW execution state. Since the DT is used to configure OSs I thought that could be a valid sentence. Unfortunately this stuff is not C, so I reiterate my point above, before changing it I would like to understand who should say the wording is ok otherwise we could argue forever.

It does configure the OS, but not for 32 vs. 64 bit. That is more of a problem for the bootloader to know which mode to boot in and covered under something like Documentation/arm/Booting. Booting ARM vs. Thumb mode would be similar situation.

Think about how your PC boots and add to that having a DTB as part of the firmware shipped with your PC. Then the end user can install a 32-bit or 64-bit OS on it. That is the usecase that needs to be supported and having different DTB for 32 and 64 bit is totally broken and doesn't even help solve that problem.

Quoted 10 lines

Quoted 10 lines

Quoted 9 lines

Documentation/devicetree/bindings/arm/cpus.txt +9 -0

+
+       - cpu-release-addr
+               Usage: required for systems that have an "enable-method"
+                      property value of "spin-table".
+               Value type: <prop-encoded-array>
+               Definition:
+                       # On ARM v8 64-bit systems must be a two cell
+                         property identifying a 64-bit zero-initialised
+                         memory location.

Quoted 5 lines

Quoted 2 lines

As I mentioned previously, isn't some wake-up method needed? Most systems will be in wfi or wfe rather than continuously spinning.

Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some thought.

Yes, it is today and standardizing this is a good thing. Which is what PSCI does. So why are you adding the spintable at all? Are you trying to set this as the standard for non-PSCI enabled platforms? Why not just say v8 boot interface is PSCI. Sure, we'll probably have to deal with other methods, but documenting something else here is not going to prevent that problem. I don't think a simple spintable would even work for any/most current platforms. I'd think we'd want to define something that would work for existing platforms (chances are new platforms will work like vendors' existing 32-bit platforms).

Quoted 17 lines · Rob Herring

Quoted 7 lines · Lorenzo Pieralisi

Quoted 6 lines · Rob Herring

Quoted 3 lines · Lorenzo Pieralisi

In order to extend the current cpu nodes bindings to newer CPUs inclusive of AArch64 and to update support for older ARM CPUs this patch updates device tree documentation for the cpu nodes bindings.

Quoted 8 lines

Quoted 1 line

Sorry for the long delay on this, but I'm still not happy with the binding here.

I had to ask Russell again to drop the bindings patches from the patch system, and this is not acceptable since two months have passed and the entire series was reviewed, acked and partially merged. I will review these bindings again but I would like to understand who should give the final go ahead to get these patches queued for upstreaming, I can't continue updating this stuff forever.

Quoted 3 lines

Most of my comments are for 64-bit. So don't blame me that it had to be reverted. I said up front I was concerned about this change breaking things and it appears it did. New kernels must not require a new DT.

The patches in Russell's tree do not break anything, I asked him to drop them since, if we change the bindings again, those patches change and have to be reworked. It was not meant to blame you at all, just saying that the process to get this stuff in the kernel should be defined properly and patches reviewed in a timely fashion.

And for legacy reasons the situation related to cpu/cpus node bindings is a complicated one, there are bindings in the ePAPR, bindings in the kernel, people are confused and with this set we wanted to draw a line. For arm64 this is an absolute must.

I disagree with you on the "new kernels must not require a new DT". That's true if bindings are well defined, not for a mix of legacy ePAPR and bindings-in-the-kernel.

What's the DT standard for ARM cpu/cpus node ? ePAPR ? In kernel docs ? A combination thereof ? Things are not clear cut and I do not like that, it is confusing.

Quoted 3 lines · Lorenzo Pieralisi

In order to extend the current cpu nodes bindings to newer CPUs inclusive of AArch64 and to update support for older ARM CPUs this patch updates device tree documentation for the cpu nodes bindings.

Sorry for the long delay on this, but I'm still not happy with the binding here.

Quoted 11 lines

Main changes:
- adds 64-bit bindings
- define usage of #address-cells
- define 32/64 dts compatibility settings
- defines behaviour on pre and post v7 uniprocessor systems
- adds ARM 11MPcore specific reg property definition

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
 1 file changed, 412 insertions(+), 47 deletions(-)

[snip]

Documentation/devicetree/bindings/arm/cpus.txt line 102

Quoted 6 lines

Documentation/devicetree/bindings/arm/cpus.txt +6 -0

+                       # On ARM v8 64-bit systems, where the reg property
+                         size can be 1 or 2 cells (as defined by cpus node's
+                         #address-cells property), this property is
+                         required and matches:
+
+                         - On systems running the OS in AArch32:

The DTS cannot change based on 32-bit or 64-bit OS.

Quoted 32 lines

Documentation/devicetree/bindings/arm/cpus.txt +32 -0

+
+                           * If the cpus node's #address-cells value is 2:
+
+                             The first reg cell must be set to 0.
+
+                             The second reg cell bits [23:0] must be set to
+                             bits [23:0] of MPIDR_EL1.
+
+                             All other bits in the reg cells must be set to 0.
+
+                           * If the cpus node's #address-cells value is 1:
+
+                             Bits [23:0] in the reg cell must be set to
+                             bits [23:0] in MPIDR_EL1.
+
+                             All other bits in the reg cell must be 0.
+
+                         - On systems running the OS in AArch64:
+
+                           * If the cpus node's #address-cells value is 2:
+
+                             The first reg cell bits [7:0] must be set to
+                             bits [39:32] of MPIDR_EL1.
+
+                             The second reg cell bits [23:0] must be set to
+                             bits [23:0] of MPIDR_EL1.
+
+                             All other bits in the reg cells must be set to 0.
+
+                           * If the cpus node's #address-cells value is 1:
+
+                             MPIDR_EL1[63:32] is 0 on all processors in the

Quoted 1 line

+ system.

Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then #address-cells can be 1. You could say the upper bits are ignored and treated as 0. However, you should simplify all this and just mandate that #address-cells must be 2 for ARMv8 or more generally must match the size of the MPIDR. If we want to boot a 32-bit kernel, then the kernel will have to adapt to support this.

This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

arch/arm/boot/dts/armada-370-xp.dtsi +0 -0

index 272bbc6..2407903 100644
@@ -23,8 +23,12 @@
 	compatible = "marvell,armada-370-xp";
 

DT cpu map parsing code must be made compliant with the latest cpus/cpu nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps() function with checks and additional parsing rules.

Uniprocessor systems predating v7 do not parse the cpus node at all since the reg property is meaningless on those systems.

Device trees for 64-bit systems can be taken as device tree input also for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries are zeroed as required in the respective fields and detects automatically the cpus node #address-cells value so that device tree written for 64-bit ARM platforms (that can have cpus node #address-cells == 2) can still be taken as input. The correct device tree entries are to be set up by the boot loader, kernel code just checks that device tree entries in the cpus node are as expected for a 32-bit CPU (reg[63:24] == 0).

cpu node entries with invalid reg property or containing duplicates are ignored and the device tree parsing is not stopped anymore when such entries are encountered, the device tree cpu node entry is just skipped.

A device tree with cpu nodes missing the boot CPU MPIDR is considered an error and the kernel flags this up as such to trigger firmware updates.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm/kernel/devtree.c | 146 ++++++++++++++++++++++++++++------------------
 1 file changed, 88 insertions(+), 58 deletions(-)

arch/arm/kernel/devtree.c +88 -58

index 0905502..80d6cf24 100644
@@ -23,6 +23,7 @@
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/smp_plat.h>
+#include <asm/system_info.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 

@@ -72,100 +73,129 @@ void __init arm_dt_memblock_reserve(void)
  */
 void __init arm_dt_init_cpu_maps(void)
 {
-	/*
-	 * Temp logical map is initialized with UINT_MAX values that are
-	 * considered invalid logical map entries since the logical map must
-	 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
-	 * read as 0.
-	 */
 	struct device_node *cpu, *cpus;
-	u32 i, j, cpuidx = 1;
+	u32 i, ac, cpuidx = 1;
+	int len;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
 	bool bootcpu_valid = false;
 	cpus = of_find_node_by_path("/cpus");
 
-	if (!cpus)
+	if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
 		return;
 
+	if (of_property_read_u32(cpus, "#address-cells", &ac)) {
+		pr_warn("%s invalid #address-cells\n", cpus->full_name);
+		ac = of_n_addr_cells(cpus);
+	}
+	/*
+	 * The boot CPU knows its MPIDR and initialize it
+	 * to allow DT boot CPU detection.
+	 */
+	cpu_logical_map(0) = mpidr;
+
 	for_each_child_of_node(cpus, cpu) {
-		u32 hwid;
+		u64 hwid64;
+		u32 hwid32;
+		const __be32 *prop;
 
 		if (of_node_cmp(cpu->type, "cpu"))
 			continue;
 
 		pr_debug(" * %s...\n", cpu->full_name);
 		/*
-		 * A device tree containing CPU nodes with missing "reg"
-		 * properties is considered invalid to build the
-		 * cpu_logical_map.
+		 * A CPU node with missing or wrong "reg" property is
+		 * considered invalid to build a cpu_logical_map entry.
 		 */
-		if (of_property_read_u32(cpu, "reg", &hwid)) {
-			pr_debug(" * %s missing reg property\n",
-				     cpu->full_name);
-			return;
+		prop = of_get_property(cpu, "reg", &len);
+		if (!prop || len < (ac * sizeof(*prop))) {
+			pr_warn(" * %s node missing/wrong reg property, skipped\n",
+				cpu->full_name);
+				goto next;
 		}
 
 		/*
-		 * 8 MSBs must be set to 0 in the DT since the reg property
-		 * defines the MPIDR[23:0].
+		 * Always read reg as u64 value.
+		 * For dts with #address-cells == 1 hwid64[63:32]
+		 * will be set to 0 by of_read_number.
+		 * Toss away the top 32 bits and store value in hwid32.
 		 */
-		if (hwid & ~MPIDR_HWID_BITMASK)
-			return;
-
+		hwid32 = hwid64 = of_read_number(prop, ac);
+		/*
+		 * hwid64[63:24] must be always be 0 since the reg
+		 * property defines the MPIDR[23:0] bits regardless
+		 * of the cpus node #address-cells value.
+		 */
+		if (hwid64 & ~MPIDR_HWID_BITMASK) {
+			pr_warn(" * %s node reg[63:24] must be 0 on 32-bit dts, got %#016llx, skipped\n",
+				cpu->full_name, hwid64);
+			goto next;
+		}
 		/*
 		 * Duplicate MPIDRs are a recipe for disaster.
 		 * Scan all initialized entries and check for
-		 * duplicates. If any is found just bail out.
-		 * temp values were initialized to UINT_MAX
-		 * to avoid matching valid MPIDR[23:0] values.
+		 * duplicates. If any is found just ignore the CPU.
+		 * Boot CPU at logical index 0 is not checked to
+		 * allow self contained boot CPU detection logic.
 		 */
-		for (j = 0; j < cpuidx; j++)
-			if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
-						     "properties in the DT\n"))
-				return;
+		for (i = 1; i < cpuidx; i++)
+			if (cpu_logical_map(i) == hwid32) {
+				pr_warn(" * %s node duplicate cpu reg property, skipped\n",
+					cpu->full_name);
+				goto next;
+			}
 
 		/*
-		 * Build a stashed array of MPIDR values. Numbering scheme
-		 * requires that if detected the boot CPU must be assigned
-		 * logical id 0. Other CPUs get sequential indexes starting
-		 * from 1. If a CPU node with a reg property matching the
-		 * boot CPU MPIDR is detected, this is recorded so that the
-		 * logical map built from DT is validated and can be used
-		 * to override the map created in smp_setup_processor_id().
+		 * If a CPU node with a reg property matching the
+		 * cpu_logical_map(0) is detected, this is recorded so
+		 * that the bootcpu_valid condition can be checked when
+		 * DT scanning is completed. Duplicate boot cpu entries
+		 * are flagged up if detected.
 		 */
-		if (hwid == mpidr) {
-			i = 0;
-			bootcpu_valid = true;
-		} else {
-			i = cpuidx++;
+		if (hwid32 == cpu_logical_map(0)) {
+			if (bootcpu_valid) {
+				pr_warn(" * %s node duplicate boot cpu reg property, skipped\n",
+					cpu->full_name);
+			} else {
+				bootcpu_valid = true;
+			}
+			goto next;
 		}
+		/*
+		 * Build cpu_logical_map array. Numbering scheme
+		 * requires that boot CPU is assigned logical id 0.
+		 * Other CPUs get sequential indexes starting from 1.
+		 */
+		i = cpuidx++;
 
-		if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
-					       "max cores %u, capping them\n",
-					       cpuidx, nr_cpu_ids)) {
+		if (cpuidx > nr_cpu_ids) {
+			pr_warn_once("DT cpu %u nodes greater than max cores %u, capping them\n",
+				cpuidx, nr_cpu_ids);
 			cpuidx = nr_cpu_ids;
-			break;
+			goto next;
 		}
 
-		tmp_map[i] = hwid;
+		cpu_logical_map(i) = hwid32;
+		set_cpu_possible(i, true);
+		pr_debug("cpu_logical_map(%u) 0x%x\n", i, cpu_logical_map(i));
+next:	;
 	}
-
-	if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
-				 "fall back to default cpu_logical_map\n"))
-		return;
+	/*
+	 * A DT missing the boot CPU MPIDR is a really bad omen
+	 * Flag it up as such.
+	 */
+	if (!bootcpu_valid)
+		pr_warn("DT missing boot cpu node\n");
 
 	/*
-	 * Since the boot CPU node contains proper data, and all nodes have
-	 * a reg property, the DT CPU list can be considered valid and the
-	 * logical map created in smp_setup_processor_id() can be overridden
+	 * Since the DT might contain fewer entries than NR_CPUS,
+	 * cpu_logical_map entries initialized in smp_setup_processor_id()
+	 * but not found in the DT must be overriden with MPIDR_INVALID
+	 * values to make sure the cpu_logical_map does not contain stale
+	 * MPIDR values.
 	 */
-	for (i = 0; i < cpuidx; i++) {
-		set_cpu_possible(i, true);
-		cpu_logical_map(i) = tmp_map[i];
-		pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
-	}
+	for (i = cpuidx; i < nr_cpu_ids; i++)
+		cpu_logical_map(i) = MPIDR_INVALID;
 }
 
 /**

Signature · 1 line

1.8.2.2