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Enable ethernet support for SOCFPGA

PATCH New dinguyen at altera.com 3 participants 10 messages Jul 17, 2013 – Jul 18, 2013

Subsystems (4)
Device tree bindings Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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dinguyen at altera.com

author
#0 lore raw

cover Enable ethernet support for SOCFPGA

From: Dinh Nguyen <[email protected]>

Hello,

These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA platform.

patch (1/4): Adds select ARM_TWD for the platform
patch (2/4): Add platform specific initialization for the ethernet controller. patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr.
Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated.
patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS.

Thanks,

Dinh Nguyen (4):
arm: socfpga: Enable ARM_TWD for socfpga
arm: socfpga: Add platform initialization for ethernet
ARM: socfpga: dts: Fix entries for the ethernet entries.
arm: socfpga: Add support for SD/MMC and ethernet to defconfig

 arch/arm/boot/dts/socfpga.dtsi         |    4 +-
 arch/arm/boot/dts/socfpga_cyclone5.dts |    2 +-
 arch/arm/configs/socfpga_defconfig     |    8 +++
 arch/arm/mach-socfpga/Kconfig          |    1 +
 arch/arm/mach-socfpga/core.h           |    8 +++
 arch/arm/mach-socfpga/socfpga.c        |   85 +++++++++++++++++++++++++++++++-
 6 files changed, 104 insertions(+), 4 deletions(-)
CC Arnd Bergmann <[email protected]>
CC Olof Johansson <[email protected]>
Cc Rob Herring <[email protected]>
Cc Thomas Petazzoni <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Jack Mitchell <[email protected]>
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH 1/4 arm: socfpga: Enable ARM_TWD for socfpga

From: Dinh Nguyen <[email protected]>

Update Kconfig to enable TWD.

Signed-off-by Dinh Nguyen <[email protected]>
CC Arnd Bergmann <[email protected]>
CC Olof Johansson <[email protected]>
Cc Rob Herring <[email protected]>
Cc Thomas Petazzoni <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Jack Mitchell <[email protected]>
---
 arch/arm/mach-socfpga/Kconfig |    1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-socfpga/Kconfig +1 -0
index dd86db4..efad818 100644
@@ -11,6 +11,7 @@ config ARCH_SOCFPGA
 	select GENERIC_CLOCKEVENTS
 	select GPIO_PL061 if GPIOLIB
 	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD if LOCAL_TIMERS
 	select HAVE_SMP
 	select MFD_SYSCON
 	select SPARSE_IRQ
Signature · 1 line
1.7.9.5
author
#2 lore raw

PATCH 2/4 arm: socfpga: Add platform initialization for ethernet

In reply to dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Use the PHYLIB to set the correct clock and skew values to the Micrel PHY. Add platform specific intilization to put the STMMAC ethernet controller into the correct PHY mode.

Signed-off-by Dinh Nguyen <[email protected]>
CC Arnd Bergmann <[email protected]>
CC Olof Johansson <[email protected]>
Cc Rob Herring <[email protected]>
Cc Thomas Petazzoni <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Jack Mitchell <[email protected]>
---
 arch/arm/mach-socfpga/core.h    |    8 ++++
 arch/arm/mach-socfpga/socfpga.c |   85 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 92 insertions(+), 1 deletion(-)
arch/arm/mach-socfpga/core.h +8 -0
index 572b8f7..505b8fe5 100644
@@ -28,6 +28,14 @@
 #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
 #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
 
+#define SYSMGR_EMACGRP_CTRL_OFFSET 0x60
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
+
 extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
arch/arm/mach-socfpga/socfpga.c +84 -1

115 lines not on this page · raw message

Signature · 1 line
1.7.9.5
author
#3 lore raw

PATCH 3/4 ARM: socfpga: dts: Fix entries for the ethernet entries.

In reply to dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Use the gate-clock emac_0_clk and emac_1_clk. Fix phy-addr binding to the correct snps,phy-addr binding.

Signed-off-by Dinh Nguyen <[email protected]>
CC Arnd Bergmann <[email protected]>
CC Olof Johansson <[email protected]>
Cc Rob Herring <[email protected]>
Cc Thomas Petazzoni <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Jack Mitchell <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi         |    4 ++--
 arch/arm/boot/dts/socfpga_cyclone5.dts |    2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/boot/dts/socfpga.dtsi +2 -2
index dbf7f22..93ee655 100644
@@ -444,7 +444,7 @@
 			interrupts = <0 115 4>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-			clocks = <&emac0_clk>;
+			clocks = <&emac_0_clk>;
 			clock-names = "stmmaceth";
 			status = "disabled";
 		};

@@ -455,7 +455,7 @@
 			interrupts = <0 120 4>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-			clocks = <&emac1_clk>;
+			clocks = <&emac_1_clk>;
 			clock-names = "stmmaceth";
 			status = "disabled";
 		};
arch/arm/boot/dts/socfpga_cyclone5.dts +1 -1
index 1853cb1..102c4d8 100644
@@ -50,7 +50,7 @@
 
 		ethernet at ff702000 {
 			phy-mode = "rgmii";
-			phy-addr = <0xffffffff>; /* probe for phy addr */
+			snps,phy-addr = <0xffffffff>; /* probe for phy addr */
 			status = "okay";
 		};
Signature · 1 line
1.7.9.5
author
#4 lore raw

PATCH 4/4 arm: socfpga: Add support for SD/MMC and ethernet to defconfig

In reply to dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Update the socfpga_defconfig to include dw_mmc driver and Micrel PHY. Also enable EXT3 and NFS FS support.

Signed-off-by Dinh Nguyen <[email protected]>
CC Arnd Bergmann <[email protected]>
CC Olof Johansson <[email protected]>
Cc Rob Herring <[email protected]>
Cc Thomas Petazzoni <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Jack Mitchell <[email protected]>
---
 arch/arm/configs/socfpga_defconfig |    8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/configs/socfpga_defconfig +8 -0
index 4e1ce21..dcca3a1 100644
@@ -52,6 +52,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_STMMAC_ETH=y
+CONFIG_MICREL_PHY=y
 # CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_SERPORT is not set

@@ -66,6 +67,9 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT3_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
 CONFIG_VFAT_FS=y

@@ -82,3 +86,7 @@ CONFIG_DEBUG_INFO=y
 CONFIG_ENABLE_DEFAULT_TRACERS=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
+CONFIG_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_SOCFPGA=y
Signature · 1 line
1.7.9.5
#5 lore raw

cover Enable ethernet support for SOCFPGA

In reply to dinguyen at altera.com
Quoted 29 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Hello,

These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA platform.

patch (1/4): Adds select ARM_TWD for the platform
patch (2/4): Add platform specific initialization for the ethernet controller. patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr.
Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated.
patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS.

Thanks,

Dinh Nguyen (4):
arm: socfpga: Enable ARM_TWD for socfpga
arm: socfpga: Add platform initialization for ethernet
ARM: socfpga: dts: Fix entries for the ethernet entries.
arm: socfpga: Add support for SD/MMC and ethernet to defconfig

  arch/arm/boot/dts/socfpga.dtsi         |    4 +-
  arch/arm/boot/dts/socfpga_cyclone5.dts |    2 +-
  arch/arm/configs/socfpga_defconfig     |    8 +++
  arch/arm/mach-socfpga/Kconfig          |    1 +
  arch/arm/mach-socfpga/core.h           |    8 +++
  arch/arm/mach-socfpga/socfpga.c        |   85 +++++++++++++++++++++++++++++++-
  6 files changed, 104 insertions(+), 4 deletions(-)
Quoted 7 lines
CC Arnd Bergmann <[email protected]>
CC Olof Johansson <[email protected]>
Cc Rob Herring <[email protected]>
Cc Thomas Petazzoni <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Jack Mitchell <[email protected]>

Hi Dinh,

What tree is this based against, or what patches are a pre-requisite to this series? I applied the patches to linux-arm/master but the compile failed.

arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup':
arch/arm/mach-socfpga/socfpga.c:85:21: error:
'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function)

    phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
                      ^

arch/arm/mach-socfpga/socfpga.c:85:21: note: each undeclared identifier is reported only once for each function it appears in arch/arm/mach-socfpga/socfpga.c:86:4: error:
'MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW' undeclared (first use in this function)

     MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000);
     ^
arch/arm/mach-socfpga/socfpga.c:87:21: error: 
'MICREL_KSZ9021_EXTREG_DATA_WRITE' undeclared (first use in this function)
    phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
                      ^
arch/arm/mach-socfpga/socfpga.c:91:4: error: 
'MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW' undeclared (first use in this 
function)
     MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000);
     ^
arch/arm/mach-socfpga/socfpga.c: In function 'socfpga_cyclone5_init':
arch/arm/mach-socfpga/socfpga.c:193:30: error: 'PHY_ID_KSZ9021RLRN' 
undeclared (first use in this function)
    phy_register_fixup_for_uid(PHY_ID_KSZ9021RLRN,
                               ^

Cheers,
Jack.

Signature · 5 lines
   Jack Mitchell (jack at embed.me.uk)
   Embedded Systems Engineer
   http://www.embed.me.uk

--
#6 lore raw

cover Enable ethernet support for SOCFPGA

Quoted 69 lines · Jack Mitchell
Quoted 33 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Hello,

These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA platform.

patch (1/4): Adds select ARM_TWD for the platform
patch (2/4): Add platform specific initialization for the ethernet controller.
patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr.
Set the ethernet clocks to be emac_0_clk and emac_1_clk so it
be gated.
patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS.

Thanks,

Dinh Nguyen (4):
arm: socfpga: Enable ARM_TWD for socfpga
arm: socfpga: Add platform initialization for ethernet
ARM: socfpga: dts: Fix entries for the ethernet entries.
arm: socfpga: Add support for SD/MMC and ethernet to defconfig

  arch/arm/boot/dts/socfpga.dtsi         |    4 +-
  arch/arm/boot/dts/socfpga_cyclone5.dts |    2 +-
  arch/arm/configs/socfpga_defconfig     |    8 +++
  arch/arm/mach-socfpga/Kconfig          |    1 +
  arch/arm/mach-socfpga/core.h           |    8 +++
  arch/arm/mach-socfpga/socfpga.c        |   85
+++++++++++++++++++++++++++++++-
  6 files changed, 104 insertions(+), 4 deletions(-)
Quoted 7 lines
CC Arnd Bergmann <[email protected]>
CC Olof Johansson <[email protected]>
Cc Rob Herring <[email protected]>
Cc Thomas Petazzoni <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Jack Mitchell <[email protected]>

Hi Dinh,

What tree is this based against, or what patches are a pre-requisite to this series? I applied the patches to linux-arm/master but the compile failed.

arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup':
arch/arm/mach-socfpga/socfpga.c:85:21: error:
'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function)
phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,

                     ^

arch/arm/mach-socfpga/socfpga.c:85:21: note: each undeclared identifier is reported only once for each function it appears in arch/arm/mach-socfpga/socfpga.c:86:4: error:
'MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW' undeclared (first use in this function)

    MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000);
    ^
arch/arm/mach-socfpga/socfpga.c:87:21: error:
'MICREL_KSZ9021_EXTREG_DATA_WRITE' undeclared (first use in this function)
   phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
                     ^
arch/arm/mach-socfpga/socfpga.c:91:4: error:
'MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW' undeclared (first use in this
function)
    MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000);
    ^
Quoted 8 lines

arch/arm/mach-socfpga/socfpga.c: In function 'socfpga_cyclone5_init':
arch/arm/mach-socfpga/socfpga.c:193:30: error: 'PHY_ID_KSZ9021RLRN' undeclared (first use in this function)
phy_register_fixup_for_uid(PHY_ID_KSZ9021RLRN,

                              ^

Cheers,
Jack.

Dinh,

So I found your patch "phy: micrel: Add definitions for common Micrel PHY registers" and applied it, now the kernel compiles. I do however still run into the "Waiting for root device" issue. This is still on my Arrow SoCkit board, which may be a bit different to the Altera devkit; so please don't let this be a blocker if it works find with your kit. It is strange though that both boards can share the same 3.9-vendor dts/kernel without any changes...

Synopsys Designware Multimedia Card Interface Driver
oprofile: no performance counters
oprofile: using timer interrupt.
TCP: cubic registered
NET: Registered protocol family 17
NET: Registered protocol family 15
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
Waiting for root device /dev/mmcblk0p2...

Cheers,
Jack.

Signature · 5 lines
  Jack Mitchell (jack at embed.me.uk)
  Embedded Systems Engineer
  http://www.embed.me.uk

--
#7 lore raw

cover Enable ethernet support for SOCFPGA

In reply to Jack Mitchell

Hi!

Quoted 13 lines
Quoted 8 lines

These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA platform.

patch (1/4): Adds select ARM_TWD for the platform
patch (2/4): Add platform specific initialization for the ethernet controller. patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr.
Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated.
patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS.

What tree is this based against, or what patches are a pre-requisite to this series? I applied the patches to linux-arm/master but the compile failed.

Quoted 5 lines

arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup':
arch/arm/mach-socfpga/socfpga.c:85:21: error:
'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function)
phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,

                     ^

It seems it depends on:

Date: Mon, 15 Jul 2013 18:08:50 -0500
From: [email protected]
To: dinh.linux at gmail.com, netdev at vger.kernel.org
Cc: Pavel Machek <[email protected]>, Nicolas Ferre <[email protected]>,
"David S. Miller" <[email protected]>, linux-arm-kernel at lists.infradead.org,
Shawn Guo <[email protected]>, Jean-Christophe Plagniol-Villard <[email protected]>, Andrew Victor <[email protected]>,
Dinh Nguyen <[email protected]>
Subject: [PATCH] phy: micrel: Add definitions for common Micrel PHY registers
X-Mailer: git-send-email 1.7.9.5

From: Dinh Nguyen <[email protected]>

Add defines for common Micrel PHY setups so that other platforms can use them. Update imx61 and sama5 hardware to use the micrel_phy.h PHY defines.

Also add support for the KSZ9021RLRN PHY.

Signed-off-by Dinh Nguyen <[email protected]>

Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#8 lore raw

cover Enable ethernet support for SOCFPGA

Hi Jack,

Quoted 40 lines · ZY - pavel

Hi!

Quoted 13 lines
Quoted 8 lines

These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA platform.

patch (1/4): Adds select ARM_TWD for the platform
patch (2/4): Add platform specific initialization for the ethernet controller. patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr.
Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated.
patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS.

What tree is this based against, or what patches are a pre-requisite to this series? I applied the patches to linux-arm/master but the compile failed.

Quoted 5 lines

arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup':
arch/arm/mach-socfpga/socfpga.c:85:21: error:
'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function)
phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,

                     ^

It seems it depends on:

Date: Mon, 15 Jul 2013 18:08:50 -0500
From: dinguyen at altera.com
To: dinh.linux at gmail.com, netdev at vger.kernel.org
Cc: Pavel Machek <[email protected]>, Nicolas Ferre <[email protected]>,
"David S. Miller" <[email protected]>, linux-arm-kernel at lists.infradead.org,
Shawn Guo <[email protected]>, Jean-Christophe Plagniol-Villard <[email protected]>, Andrew Victor <[email protected]>,
Dinh Nguyen <[email protected]>
Subject: [PATCH] phy: micrel: Add definitions for common Micrel PHY registers
X-Mailer: git-send-email 1.7.9.5

From: Dinh Nguyen <[email protected]>

Quoted 7 lines

Add defines for common Micrel PHY setups so that other platforms can use them. Update imx61 and sama5 hardware to use the micrel_phy.h PHY defines.

Also add support for the KSZ9021RLRN PHY.

Signed-off-by Dinh Nguyen <[email protected]>

Yes, the above patch is necessary. I was hoping that patch can go into either Shawn's or Nicolas' tree. I have received ACKs from both. There is also the SD/MMC bindings patch that has not been applied to the arm-soc tree yet. I have started collecting the patches at github in the meantime:

git at github.com:dinh-linux/linux-socfpga.git for-next

Dinh

Quoted 2 lines

Pavel

#9 lore raw

cover Enable ethernet support for SOCFPGA

Quoted 57 lines · Dinh Nguyen

Hi Jack,

Quoted 40 lines · ZY - pavel

Hi!

Quoted 13 lines
Quoted 8 lines

These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA platform.

patch (1/4): Adds select ARM_TWD for the platform
patch (2/4): Add platform specific initialization for the ethernet controller. patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr.
Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated.
patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS.

What tree is this based against, or what patches are a pre-requisite to this series? I applied the patches to linux-arm/master but the compile failed.

Quoted 5 lines

arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup':
arch/arm/mach-socfpga/socfpga.c:85:21: error:
'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function)
phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,

                     ^

It seems it depends on:

Date: Mon, 15 Jul 2013 18:08:50 -0500
From: dinguyen at altera.com
To: dinh.linux at gmail.com, netdev at vger.kernel.org
Cc: Pavel Machek <[email protected]>, Nicolas Ferre <[email protected]>,
"David S. Miller" <[email protected]>, linux-arm-kernel at lists.infradead.org,
Shawn Guo <[email protected]>, Jean-Christophe Plagniol-Villard <[email protected]>, Andrew Victor <[email protected]>,
Dinh Nguyen <[email protected]>
Subject: [PATCH] phy: micrel: Add definitions for common Micrel PHY registers
X-Mailer: git-send-email 1.7.9.5

From: Dinh Nguyen <[email protected]>

Quoted 7 lines

Add defines for common Micrel PHY setups so that other platforms can use them. Update imx61 and sama5 hardware to use the micrel_phy.h PHY defines.

Also add support for the KSZ9021RLRN PHY.

Signed-off-by Dinh Nguyen <[email protected]>

Yes, the above patch is necessary. I was hoping that patch can go into either Shawn's or Nicolas' tree. I have received ACKs from both. There is also the SD/MMC bindings patch that has not been applied to the arm-soc tree yet. I have started collecting the patches at github in the meantime:

Quoted 3 lines

git at github.com:dinh-linux/linux-socfpga.git for-next

Dinh

Dinh,

Perfect, that boots from the mmc! For what it's worth, for the whole series + pre-requisite patches on an Arrow SoCkit devkit:

Tested-by Jack Mitchell <[email protected]>
Signature · 5 lines
  Jack Mitchell (jack at embed.me.uk)
  Embedded Systems Engineer
  http://www.embed.me.uk

--