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ARM: tegra: Make cache line size SoC specific

PATCH New Thierry Reding 3 participants 7 messages Jul 18, 2013 – Aug 14, 2013 Tegra architecture support

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#0 lore raw

PATCH 1/2 ARM: tegra: Make cache line size SoC specific

From: Thierry Reding <[email protected]>

Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file.

Signed-off-by Thierry Reding <[email protected]>
---
 include/configs/tegra-common.h    | 2 --
 include/configs/tegra114-common.h | 3 +++
 include/configs/tegra20-common.h  | 3 +++
 include/configs/tegra30-common.h  | 3 +++
 4 files changed, 9 insertions(+), 2 deletions(-)
include/configs/tegra-common.h +0 -2
index cb9e7c3..056207b 100644
@@ -33,8 +33,6 @@
 #define CONFIG_TEGRA			/* which is a Tegra generic machine */
 #define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #include <asm/arch/tegra.h>		/* get chip and board defs */
 
 /*
include/configs/tegra114-common.h +3 -0
index 44e98e5..c3de9a9 100644
@@ -18,6 +18,9 @@
 #define _TEGRA114_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * NS16550 Configuration
  */
include/configs/tegra20-common.h +3 -0
index d5abecb..b334b33 100644
@@ -25,6 +25,9 @@
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */
include/configs/tegra30-common.h +3 -0
index 7ea36be..a72dc13 100644
@@ -25,6 +25,9 @@
 #define _TEGRA30_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */
Signature · 1 line
1.8.1.5
author
#1 lore raw

PATCH 2/2 ARM: tegra: Enable data cache on Dalmore

From: Thierry Reding <[email protected]>

Disabling the data cache is no longer required to boot Dalmore, so enable it. This results in notably better performance when loading and booting the Linux kernel.

Signed-off-by Thierry Reding <[email protected]>
---
 include/configs/dalmore.h | 3 ---
 1 file changed, 3 deletions(-)
include/configs/dalmore.h +0 -3
index 2723843..3d3619f 100644
@@ -21,9 +21,6 @@
 
 #include "tegra114-common.h"
 
-/* Must be off for Dalmore to boot !?!? FIXME */
-#define CONFIG_SYS_DCACHE_OFF
-
 /* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
 #define CONFIG_DEFAULT_DEVICE_TREE	tegra114-dalmore
 #define CONFIG_OF_CONTROL
Signature · 1 line
1.8.1.5
#2 lore raw

PATCH 1/2 ARM: tegra: Make cache line size SoC specific

In reply to Thierry Reding
Quoted 6 lines · Thierry Reding

From: Thierry Reding <[email protected]>

Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file.

Tested-by Stephen Warren <[email protected]>
Reviewed-by Stephen Warren <[email protected]>
author
#3 lore raw

PATCH 1/2 ARM: tegra: Make cache line size SoC specific

Quoted 10 lines · Stephen Warren
Quoted 6 lines · Thierry Reding

From: Thierry Reding <[email protected]>

Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file.

Tested-by Stephen Warren <[email protected]>
Reviewed-by Stephen Warren <[email protected]>

Do these apply to patch 2 of this series as well?

Thierry
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#4 lore raw

PATCH 1/2 ARM: tegra: Make cache line size SoC specific

Quoted 10 lines · Thierry Reding
Quoted 9 lines · Stephen Warren
Quoted 7 lines · Thierry Reding

From: Thierry Reding <[email protected]>

Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file.

Quoted 4 lines
Quoted 2 lines
Tested-by Stephen Warren <[email protected]> Reviewed-by:

Stephen Warren <[email protected]>

Do these apply to patch 2 of this series as well?

Yes, the whole series.

#5 lore raw

PATCH 1/2 ARM: tegra: Make cache line size SoC specific

In reply to Thierry Reding
Quoted 6 lines · Thierry Reding

From: Thierry Reding <[email protected]>

Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file.

Tom, can these two patches be applied please?

#6 lore raw

PATCH 1/2 ARM: tegra: Make cache line size SoC specific

Sure, your mkimage patch, and Thierry's 2 cache patches have been applied to u-boot-tegra/next (after rebasing next against Albert's ARM master), build tested (all Tegra boards build fine), and pushed to denx. Also updated u-boot-tegra/master w/Albert's ARM TOT.

Sorry for the delay, really busy w/new stuff. Ping me if I get behind again.

Thanks,

Tom

Quoted 9 lines

-----Original Message-----
From: Stephen Warren [mailto:swarren at wwwdotorg.org]
Sent: Wednesday, August 14, 2013 9:05 AM
To: Tom Warren
Cc: Thierry Reding; u-boot at lists.denx.de; Thierry Reding; Stephen Warren
Subject: Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific

On 07/18/2013 01:13 PM, Thierry Reding wrote:

Quoted 8 lines
Quoted 6 lines

From: Thierry Reding <[email protected]>

Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file.

Tom, can these two patches be applied please?

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