ddr cfg: DRAM_RESET needs 0x00020030
PATCH 1/1 ddr cfg: DRAM_RESET needs 0x00020030
The old value of 0x000e0030 will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021.
I have no explanation as to why.
But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of DRAM_RESET.
My thanks go to Liu Hui(Jason) for this information.
--- board/boundary/nitrogen6x/ddr-setup.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
board/boundary/nitrogen6x/ddr-setup.cfg +1 -1
@@ -74,7 +74,7 @@ DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
Signature · 1 line
1.8.1.2
PATCH 1/1 ddr cfg: DRAM_RESET needs 0x00020030
Hi Troy,
Quoted 5 lines · Troy Kisky
The old value of
0x000e0030will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021.
I have no explanation as to why.
Quoted 7 lines
But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of
DRAM_RESET.My thanks go to Liu Hui(Jason) for this information.
Signed-off-by Troy Kisky <[email protected]>
Should this go into 2013.07?
PATCH 1/1 ddr cfg: DRAM_RESET needs 0x00020030
Quoted 9 lines · Fabio Estevam
Hi Troy,
Quoted 5 lines · Troy Kisky
The old value of
0x000e0030will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021.
I have no explanation as to why.
Quoted 9 lines
Quoted 7 lines
But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of
DRAM_RESET.My thanks go to Liu Hui(Jason) for this information.
Signed-off-by Troy Kisky <[email protected]>Should this go into 2013.07?
If not too late. It only affect Nitrogen6x, at least until Sabrelite is combined with it.
And Sabrelite is already using this value.
Troy
PATCH 1/1 ddr cfg: DRAM_RESET needs 0x00020030
Quoted 16 lines · Troy Kisky
Quoted 15 lines · Fabio Estevam
Hi Troy,
Quoted 11 lines · Troy Kisky
The old value of
0x000e0030will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021.
I have no explanation as to why.But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of
DRAM_RESET.My thanks go to Liu Hui(Jason) for this information.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Troy Kisky <[email protected]>Should this go into 2013.07?
If not too late. It only affect Nitrogen6x, at least until Sabrelite is combined with it.
And Sabrelite is already using this value.
Whose acks should I wait for on this?
Signature · 8 lines
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PATCH 1/1 ddr cfg: DRAM_RESET needs 0x00020030
Hi Tom,
Quoted 18 lines · Tom Rini
Quoted 17 lines · Troy Kisky
Quoted 16 lines · Fabio Estevam
Hi Troy,
Quoted 12 lines · Troy Kisky
The old value of
0x000e0030will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021.
I have no explanation as to why.But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of
DRAM_RESET.My thanks go to Liu Hui(Jason) for this information.
Signed-off-by Troy Kisky <[email protected]>
Quoted 8 lines
Quoted 6 lines
Quoted 2 lines
Should this go into 2013.07?
If not too late. It only affect Nitrogen6x, at least until Sabrelite is combined with it.
And Sabrelite is already using this value.Whose acks should I wait for on this?
Just realized I acked in the original message and you were not on Cc, so
As Jason Liu explained the mx6 reference manual will be updated to fix the incorrect setting.
Thanks,
Fabio Estevam
PATCH 1/1 ddr cfg: DRAM_RESET needs 0x00020030
In reply to Tom RiniHi Tom,
Am 19/07/2013 23:50, schrieb Tom Rini:
Quoted 19 lines · Troy Kisky
Quoted 18 lines · Fabio Estevam
Quoted 16 lines
Hi Troy,
Quoted 12 lines · Troy Kisky
The old value of
0x000e0030will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021.
I have no explanation as to why.But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of
DRAM_RESET.My thanks go to Liu Hui(Jason) for this information.
Signed-off-by Troy Kisky <[email protected]>
Quoted 8 lines
Quoted 6 lines
Quoted 2 lines
Should this go into 2013.07?
If not too late. It only affect Nitrogen6x, at least until Sabrelite is combined with it.
And Sabrelite is already using this value.Whose acks should I wait for on this?
PATCH 1/1 ddr cfg: DRAM_RESET needs 0x00020030
Quoted 29 lines · Stefano Babic
Hi Tom,
Am 19/07/2013 23:50, schrieb Tom Rini:
Quoted 26 lines · Troy Kisky
Quoted 24 lines · Fabio Estevam
Quoted 9 lines
Hi Troy,
Quoted 5 lines · Troy Kisky
The old value of
0x000e0030will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021.
I have no explanation as to why.Quoted 9 lines
Quoted 7 lines
But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of
DRAM_RESET.My thanks go to Liu Hui(Jason) for this information.
Signed-off-by Troy Kisky <[email protected]>Should this go into 2013.07?
If not too late. It only affect Nitrogen6x, at least until Sabrelite is combined with it.
And Sabrelite is already using this value.
Quoted 8 lines
Quoted 1 line
Whose acks should I wait for on this?
Acked-by Stefano Babic <[email protected]>From the i.MX point of view, the patch is a fix for the RAM configuration and does not affects other boards but only the nitrogen. I had merged this in u-boot-imx, but it is too late for PR. If it is not too late, please merge it for release.
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH 1/1 ddr cfg: DRAM_RESET needs 0x00020030
In reply to Troy KiskyQuoted 5 lines · Troy Kisky
The old value of
0x000e0030will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021.
I have no explanation as to why.
Quoted 7 lines
But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of
DRAM_RESET.My thanks go to Liu Hui(Jason) for this information.
Signed-off-by Troy Kisky <[email protected]>
PATCH 1/1 ddr cfg: DRAM_RESET needs 0x00020030
In reply to Troy KiskyQuoted 5 lines · Troy Kisky
The old value of
0x000e0030will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021.
I have no explanation as to why.
Quoted 7 lines
But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of
DRAM_RESET.My thanks go to Liu Hui(Jason) for this information.
Signed-off-by Troy Kisky <[email protected]>
Thanks
Dirk
Quoted 16 lines
--- board/boundary/nitrogen6x/ddr-setup.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)board/boundary/nitrogen6x/ddr-setup.cfg +1
-1@@ -74,7 +74,7 @@ DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000