Common Clock Framework support for Samsung S3C64xx
Subsystems (8)
v2 cover Common Clock Framework support for Samsung S3C64xx
This series is an attempt to move clock support on Samsung S3C64xx SoCs to Common Clock Framework.
First, support for PLL types present on S3C64xx SoCs is added to Samsung Common Clock Framework driver. Then the main clock driver for mentioned SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.
Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanup
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856
On S3C6410-based Tiny6410 board (Mini6410-compatible):
For v1:
Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- defined mout_syncmux as read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.
Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code
.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt delete mode 100644 arch/arm/mach-s3c64xx/clock.c create mode 100644 drivers/clk/samsung/clk-s3c64xx.c create mode 100644 include/dt-bindings/clock/samsung,s3c64xx-clock.h
Signature · 1 line
1.8.3.2
PATCH v2 1/8 clk: mux: Add support for read-only muxes.
Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new CLK_MUX_READ_ONLY mux flag.
--- drivers/clk/clk-mux.c | 10 +++++++++- include/linux/clk-provider.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-)
drivers/clk/clk-mux.c +9 -1
@@ -107,6 +107,11 @@ const struct clk_ops clk_mux_ops = { };EXPORT_SYMBOL_GPL (clk_mux_ops); +const struct clk_ops clk_mux_ro_ops = { + .get_parent = clk_mux_get_parent, +}; +EXPORT_SYMBOL_GPL (clk_mux_ro_ops); + struct clk *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
@@ -133,7 +138,10 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, } init.name = name; - init.ops = &clk_mux_ops; +if (clk_mux_flags &CLK_MUX_READ_ONLY ) + init.ops = &clk_mux_ro_ops; +else + init.ops = &clk_mux_ops; init.flags = flags |CLK_IS_BASIC ; init.parent_names = parent_names; init.num_parents = num_parents;
include/linux/clk-provider.h +2 -0
@@ -327,8 +327,10 @@ struct clk_mux {#define CLK_MUX_INDEX_ONE BIT(0)#define CLK_MUX_INDEX_BIT BIT(1)#define CLK_MUX_HIWORD_MASK BIT(2) +#define CLK_MUX_READ_ONLY BIT(3)/* mux setting cannot be changed */ extern const struct clk_ops clk_mux_ops; +extern const struct clk_ops clk_mux_ro_ops; struct clk *clk_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags,
Signature · 1 line
1.8.3.2
PATCH v2 1/8 clk: mux: Add support for read-only muxes.
Hello.
Quoted 6 lines · Tomasz Figa
Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new
CLK_MUX_READ_ONLYmux flag.Signed-off-by Tomasz Figa <[email protected]>
[...]
include/linux/clk-provider.h struct clk_mux { · line 330
Quoted 9 lines
include/linux/clk-provider.h +1
-0@@ -327,8 +327,10 @@ struct clk_mux {#define CLK_MUX_INDEX_ONE BIT(0)#define CLK_MUX_INDEX_BIT BIT(1)#define CLK_MUX_HIWORD_MASK BIT(2) +#define CLK_MUX_READ_ONLY BIT(3)/* mux setting cannot be changed */
Please align BIT(3) with the above BIT() invocations.
WBR, Sergei
PATCH v2 1/8 clk: mux: Add support for read-only muxes.
Hi Sergei,
Quoted 12 lines · On Tuesday 23 of July 2013 15:22:44 Sergei Shtylyov wrote:
Hello.
Quoted 6 lines · Tomasz Figa
Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new
CLK_MUX_READ_ONLYmux flag.Signed-off-by Tomasz Figa <[email protected]>[...]
Quoted 12 lines
include/linux/clk-provider.h struct clk_mux { · line 330
Quoted 10 lines
include/linux/clk-provider.h +1
-0@@ -327,8 +327,10 @@ struct clk_mux {#define CLK_MUX_INDEX_ONE BIT(0)#define CLK_MUX_INDEX_BIT BIT(1)#define CLK_MUX_HIWORD_MASK BIT(2) +#define CLK_MUX_READ_ONLY BIT(3)/* mux setting cannot be changed */ Please align BIT(3) with the above
BIT()invocations.
Different indentation was intended here to fit the comment, like in case of generic flags. IMHO remaining flags should be changed to this way as well, but this is probably material for another patch.
Best regards,
Tomasz
PATCH v2 1/8 clk: mux: Add support for read-only muxes.
In reply to Tomasz FigaHi Mike,
Quoted 44 lines · On Tuesday 23 of July 2013 01:49:18 Tomasz Figa wrote:
Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new
CLK_MUX_READ_ONLYmux flag.Signed-off-by Tomasz Figa <[email protected]>--- drivers/clk/clk-mux.c | 10 +++++++++- include/linux/clk-provider.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-)drivers/clk/clk-mux.c +9
-1@@ -107,6 +107,11 @@ const struct clk_ops clk_mux_ops = { };EXPORT_SYMBOL_GPL (clk_mux_ops); +const struct clk_ops clk_mux_ro_ops = { + .get_parent = clk_mux_get_parent, +}; +EXPORT_SYMBOL_GPL (clk_mux_ro_ops); + struct clk *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask,@@ -133,7 +138,10 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, } init.name = name; - init.ops = &clk_mux_ops; +if (clk_mux_flags &CLK_MUX_READ_ONLY ) + init.ops = &clk_mux_ro_ops; +else + init.ops = &clk_mux_ops; init.flags = flags |CLK_IS_BASIC ; init.parent_names = parent_names; init.num_parents = num_parents;include/linux/clk-provider.h +0
-0
include/linux/clk-provider.h struct clk_mux { · line 336
Quoted 10 lines
include/linux/clk-provider.h +2
-0@@ -327,8 +327,10 @@ struct clk_mux {#define CLK_MUX_INDEX_ONE BIT(0)#define CLK_MUX_INDEX_BIT BIT(1)#define CLK_MUX_HIWORD_MASK BIT(2) +#define CLK_MUX_READ_ONLY BIT(3)/* mux setting cannot be changed */ extern const struct clk_ops clk_mux_ops; +extern const struct clk_ops clk_mux_ro_ops;struct clk *clk_register_mux (struct device *dev,const char *name, const char **parent_names, u8 num_parents, unsigned long
flags,
What do you think about this?
Best regards,
Tomasz
PATCH v2 1/8 clk: mux: Add support for read-only muxes.
Quoting Tomasz Figa (2013-07-27 05:41:05)
Quoted 52 lines
Hi Mike,
Quoted 49 lines · On Tuesday 23 of July 2013 01:49:18 Tomasz Figa wrote:
Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new
CLK_MUX_READ_ONLYmux flag.Signed-off-by Tomasz Figa <[email protected]>--- drivers/clk/clk-mux.c | 10 +++++++++- include/linux/clk-provider.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-)drivers/clk/clk-mux.c +9
-1@@ -107,6 +107,11 @@ const struct clk_ops clk_mux_ops = { };EXPORT_SYMBOL_GPL (clk_mux_ops); +const struct clk_ops clk_mux_ro_ops = { + .get_parent = clk_mux_get_parent, +}; +EXPORT_SYMBOL_GPL (clk_mux_ro_ops); + struct clk *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask,@@ -133,7 +138,10 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, } init.name = name; - init.ops = &clk_mux_ops; +if (clk_mux_flags &CLK_MUX_READ_ONLY ) + init.ops = &clk_mux_ro_ops; +else + init.ops = &clk_mux_ops; init.flags = flags |CLK_IS_BASIC ; init.parent_names = parent_names; init.num_parents = num_parents;include/linux/clk-provider.h +1
-0@@ -327,8 +327,10 @@ struct clk_mux {#define CLK_MUX_INDEX_ONE BIT(0)#define CLK_MUX_INDEX_BIT BIT(1)#define CLK_MUX_HIWORD_MASK BIT(2) +#define CLK_MUX_READ_ONLY BIT(3)/* mux setting cannot be changed */
Quoted 8 lines
include/linux/clk-provider.h struct clk_mux {
Quoted 5 lines
include/linux/clk-provider.h +1
-0extern const struct clk_ops clk_mux_ops; +extern const struct clk_ops clk_mux_ro_ops;struct clk *clk_register_mux (struct device *dev,const char *name, const char **parent_names, u8 num_parents, unsigned longflags,
What do you think about this?
Looks good to me. This makes sense for OMAP's sys_clkin clock, probably a common pattern.
Quoted 3 lines
Best regards,
Tomasz
PATCH v2 2/8 clk: samsung: pll: Add support for PLL6552 and PLL6553
In reply to Tomasz FigaThis patch adds support for PLL6552 and PLL6553 PLLs present on Samsung S3C64xx SoCs.
--- drivers/clk/samsung/clk-pll.c | 160 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 4 ++ 2 files changed, 164 insertions(+)
drivers/clk/samsung/clk-pll.c +160 -0
@@ -337,6 +337,166 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name, }/* +* PLL6552 Clock Type +*/ + +#define PLL6552_LOCK_REG 0x00 +#define PLL6552_CON_REG 0x0c + +#define PLL6552_MDIV_MASK 0x3ff +#define PLL6552_PDIV_MASK 0x3f +#define PLL6552_SDIV_MASK 0x7 +#define PLL6552_MDIV_SHIFT 16 +#define PLL6552_PDIV_SHIFT 8 +#define PLL6552_SDIV_SHIFT 0 + +struct samsung_clk_pll6552 { +struct clk_hw hw; +void __iomem *reg_base; +}; + +#define to_clk_pll6552 (_hw) container_of(_hw, struct samsung_clk_pll6552, hw) + +static unsigned long samsung_pll6552_recalc_rate (struct clk_hw *hw, +unsigned long parent_rate) +{ +struct samsung_clk_pll6552 *pll =to_clk_pll6552 (hw); +u32 mdiv, pdiv, sdiv, pll_con; +u64 fvco = parent_rate; + + pll_con =__raw_readl (pll->reg_base +PLL6552_CON_REG ); + mdiv = (pll_con >>PLL6552_MDIV_SHIFT ) &PLL6552_MDIV_MASK ; + pdiv = (pll_con >>PLL6552_PDIV_SHIFT ) &PLL6552_PDIV_MASK ; + sdiv = (pll_con >>PLL6552_SDIV_SHIFT ) &PLL6552_SDIV_MASK ; + + fvco *= mdiv; +do_div (fvco, (pdiv << sdiv)); + +return (unsigned long )fvco; +} + +static const struct clk_ops samsung_pll6552_clk_ops = { + .recalc_rate = samsung_pll6552_recalc_rate, +}; + +struct clk *__init samsung_clk_register_pll6552 (const char *name, +const char *pname,void __iomem *base) +{ +struct samsung_clk_pll6552 *pll; +struct clk *clk; +struct clk_init_data init; + + pll =kzalloc (sizeof (*pll),GFP_KERNEL ); +if (!pll) { +pr_err ("%s: could not allocate pll clk %s\n" , __func__, name); +return NULL ; + } + + init.name = name; + init.ops = &samsung_pll6552_clk_ops; + init.parent_names = &pname; + init.num_parents =1 ; + + pll->hw.init = &init; + pll->reg_base = base; + + clk =clk_register (NULL , &pll->hw); +if (IS_ERR (clk)) { +pr_err ("%s: failed to register pll clock %s\n" , __func__, + name); +kfree (pll); + } + +if (clk_register_clkdev (clk, name,NULL )) +pr_err ("%s: failed to register lookup for %s" , __func__, name); + +return clk; +} + +/* +* PLL6553 Clock Type +*/ + +#define PLL6553_LOCK_REG 0x00 +#define PLL6553_CON0_REG 0x0c +#define PLL6553_CON1_REG 0x10 + +#define PLL6553_MDIV_MASK 0xff +#define PLL6553_PDIV_MASK 0x3f +#define PLL6553_SDIV_MASK 0x7 +#define PLL6553_KDIV_MASK 0xffff +#define PLL6553_MDIV_SHIFT 16 +#define PLL6553_PDIV_SHIFT 8 +#define PLL6553_SDIV_SHIFT 0 +#define PLL6553_KDIV_SHIFT 0 + +struct samsung_clk_pll6553 { +struct clk_hw hw; +void __iomem *reg_base; +}; + +#define to_clk_pll6553 (_hw) container_of(_hw, struct samsung_clk_pll6553, hw) + +static unsigned long samsung_pll6553_recalc_rate (struct clk_hw *hw, +unsigned long parent_rate) +{ +struct samsung_clk_pll6553 *pll =to_clk_pll6553 (hw); +u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; +u64 fvco = parent_rate; + + pll_con0 =__raw_readl (pll->reg_base +PLL6553_CON0_REG ); + pll_con1 =__raw_readl (pll->reg_base +PLL6553_CON1_REG ); + mdiv = (pll_con0 >>PLL6553_MDIV_SHIFT ) &PLL6553_MDIV_MASK ; + pdiv = (pll_con0 >>PLL6553_PDIV_SHIFT ) &PLL6553_PDIV_MASK ; + sdiv = (pll_con0 >>PLL6553_SDIV_SHIFT ) &PLL6553_SDIV_MASK ; + kdiv = (pll_con1 >>PLL6553_KDIV_SHIFT ) &PLL6553_KDIV_MASK ; + + fvco *= (mdiv <<16 ) + kdiv; +do_div (fvco, (pdiv << sdiv)); + fvco >>=16 ; + +return (unsigned long )fvco; +} + +static const struct clk_ops samsung_pll6553_clk_ops = { + .recalc_rate = samsung_pll6553_recalc_rate, +}; + +struct clk *__init samsung_clk_register_pll6553 (const char *name, +const char *pname,void __iomem *base) +{ +struct samsung_clk_pll6553 *pll; +struct clk *clk; +struct clk_init_data init; + + pll =kzalloc (sizeof (*pll),GFP_KERNEL ); +if (!pll) { +pr_err ("%s: could not allocate pll clk %s\n" , __func__, name); +return NULL ; + } + + init.name = name; + init.ops = &samsung_pll6553_clk_ops; + init.parent_names = &pname; + init.num_parents =1 ; + + pll->hw.init = &init; + pll->reg_base = base; + + clk =clk_register (NULL , &pll->hw); +if (IS_ERR (clk)) { +pr_err ("%s: failed to register pll clock %s\n" , __func__, + name); +kfree (pll); + } + +if (clk_register_clkdev (clk, name,NULL )) +pr_err ("%s: failed to register lookup for %s" , __func__, name); + +return clk; +} + +/* * PLL2550x Clock Type */
drivers/clk/samsung/clk-pll.h +4 -0
@@ -34,6 +34,10 @@ extern struct clk * __init samsung_clk_register_pll45xx(const char *name,extern struct clk *__init samsung_clk_register_pll46xx (const char *name,const char *pname,const void __iomem *con_reg,enum pll46xx_type type); +extern struct clk *samsung_clk_register_pll6552 (const char *name, +const char *pname,void __iomem *base); +extern struct clk *samsung_clk_register_pll6553 (const char *name, +const char *pname,void __iomem *base);extern struct clk *__init samsung_clk_register_pll2550x (const char *name,const char *pname,const void __iomem *reg_base,const unsigned long offset);
Signature · 1 line
1.8.3.2
PATCH v3 2/8 clk: samsung: pll: Add support for PLL6552 and PLL6553
This patch adds support for PLL6552 and PLL6553 PLLs present on Samsung S3C64xx SoCs.
--- drivers/clk/samsung/clk-pll.c | 77 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 2 ++ 2 files changed, 79 insertions(+)
Changes since v2:
- Reworked to use new PLL registration method introduced by Yadwinder Singh Brar's patch series:
( http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20041 )
drivers/clk/samsung/clk-pll.c +77 -0
@@ -438,6 +438,77 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name, }/* +* PLL6552 Clock Type +*/ + +#define PLL6552_MDIV_MASK 0x3ff +#define PLL6552_PDIV_MASK 0x3f +#define PLL6552_SDIV_MASK 0x7 +#define PLL6552_MDIV_SHIFT 16 +#define PLL6552_PDIV_SHIFT 8 +#define PLL6552_SDIV_SHIFT 0 + +static unsigned long samsung_pll6552_recalc_rate (struct clk_hw *hw, +unsigned long parent_rate) +{ +struct samsung_clk_pll *pll =to_clk_pll (hw); +u32 mdiv, pdiv, sdiv, pll_con; +u64 fvco = parent_rate; + + pll_con =__raw_readl (pll->con_reg); + mdiv = (pll_con >>PLL6552_MDIV_SHIFT ) &PLL6552_MDIV_MASK ; + pdiv = (pll_con >>PLL6552_PDIV_SHIFT ) &PLL6552_PDIV_MASK ; + sdiv = (pll_con >>PLL6552_SDIV_SHIFT ) &PLL6552_SDIV_MASK ; + + fvco *= mdiv; +do_div (fvco, (pdiv << sdiv)); + +return (unsigned long )fvco; +} + +static const struct clk_ops samsung_pll6552_clk_ops = { + .recalc_rate = samsung_pll6552_recalc_rate, +}; + +/* +* PLL6553 Clock Type +*/ + +#define PLL6553_MDIV_MASK 0xff +#define PLL6553_PDIV_MASK 0x3f +#define PLL6553_SDIV_MASK 0x7 +#define PLL6553_KDIV_MASK 0xffff +#define PLL6553_MDIV_SHIFT 16 +#define PLL6553_PDIV_SHIFT 8 +#define PLL6553_SDIV_SHIFT 0 +#define PLL6553_KDIV_SHIFT 0 + +static unsigned long samsung_pll6553_recalc_rate (struct clk_hw *hw, +unsigned long parent_rate) +{ +struct samsung_clk_pll *pll =to_clk_pll (hw); +u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; +u64 fvco = parent_rate; + + pll_con0 =__raw_readl (pll->con_reg); + pll_con1 =__raw_readl (pll->con_reg +0x4 ); + mdiv = (pll_con0 >>PLL6553_MDIV_SHIFT ) &PLL6553_MDIV_MASK ; + pdiv = (pll_con0 >>PLL6553_PDIV_SHIFT ) &PLL6553_PDIV_MASK ; + sdiv = (pll_con0 >>PLL6553_SDIV_SHIFT ) &PLL6553_SDIV_MASK ; + kdiv = (pll_con1 >>PLL6553_KDIV_SHIFT ) &PLL6553_KDIV_MASK ; + + fvco *= (mdiv <<16 ) + kdiv; +do_div (fvco, (pdiv << sdiv)); + fvco >>=16 ; + +return (unsigned long )fvco; +} + +static const struct clk_ops samsung_pll6553_clk_ops = { + .recalc_rate = samsung_pll6553_recalc_rate, +}; + +/* * PLL2550x Clock Type */
@@ -572,6 +643,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,else init.ops = &samsung_pll36xx_clk_ops;break ; +case pll_6552: + init.ops = &samsung_pll6552_clk_ops; +break ; +case pll_6553: + init.ops = &samsung_pll6553_clk_ops; +break ;default :pr_warn ("%s: Unknown pll type for pll clk %s\n" , __func__, pll_clk->name);
drivers/clk/samsung/clk-pll.h +2 -0
@@ -17,6 +17,8 @@ enum samsung_pll_type { pll_36xx, pll_2550, pll_2650, + pll_6552, + pll_6553, };#define PLL_35XX_RATE (_rate, _m, _p, _s) \
Signature · 1 line
1.8.3.2
PATCH v3 2/8 clk: samsung: pll: Add support for PLL6552 and PLL6553
Quoted 4 lines · Tomasz Figa
Changes since v2:
- Reworked to use new PLL registration method introduced by Yadwinder Singh Brar's patch series:( http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20041 )
I'm not able to test this series since that lot isn't in -next and I
didn't get a copy.
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PATCH v3 2/8 clk: samsung: pll: Add support for PLL6552 and PLL6553
Quoted 9 lines · On Sunday 28 of July 2013 13:30:51 Mark Brown wrote:
Quoted 5 lines · Tomasz Figa
Changes since v2:
- Reworked to use new PLL registration method introduced by YadwinderSingh Brar's patch series:
( http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20041 )I'm not able to test this series since that lot isn't in -next and I didn't get a copy.
Hmm, I wonder what happened with that series, as Mike was supposed to try applying it to clk tree [1].
Mike, could you shed some light on this?
Best regards,
Tomasz
[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20041/focus=21003
PATCH v3 2/8 clk: samsung: pll: Add support for PLL6552 and PLL6553
Quoting Tomasz Figa (2013-07-28 05:38:25)
Quoted 8 lines · On Sunday 28 of July 2013 13:30:51 Mark Brown wrote:
Quoted 7 lines · Tomasz Figa
Quoted 5 lines
Changes since v2:
- Reworked to use new PLL registration method introduced by YadwinderSingh Brar's patch series:
( http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20041 )
Quoted 7 lines
Quoted 2 lines
I'm not able to test this series since that lot isn't in -next and I didn't get a copy.
Hmm, I wonder what happened with that series, as Mike was supposed to try applying it to clk tree [1].
Mike, could you shed some light on this?
It's merged and available from my tree.
Regards,
Mike
Quoted 5 lines
Best regards,
Tomasz[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20041/focus=21003
PATCH v2 3/8 clk: samsung: Add clock driver for S3C64xx SoCs
In reply to Tomasz FigaThis patch adds new, Common Clock Framework-based clock driver for Samsung S3C64xx SoCs. The driver is just added, without actually letting the platforms use it yet, since this requires more intermediate steps.
--- .../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++++ drivers/clk/samsung/Makefile | 3 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++++++++++++++ include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++++++ 4 files changed, 723 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt create mode 100644 drivers/clk/samsung/clk-s3c64xx.c create mode 100644 include/dt-bindings/clock/samsung,s3c64xx-clock.h
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt new file +77 -0
@@ -0,0 +1,77 @@ +* Samsung S3C64xx Clock Controller + +The S3C64xx clock controller generates and supplies clock to various controllers +within the SoC. The clock binding described here is applicable to all SoCs in +the S3C64xx family. + +Required Properties: + +- compatible: should be one of the following. + - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC. + - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. Some of the clocks are available only +on a particular S3C64xx SoC and this is specified where applicable. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device +tree sources. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "fin_pll" - PLL input clock (xtal/extclk) - required, + - "xusbxti" - USB xtal - required, + - "iiscdclk0" - I2S0 codec clock - optional, + - "iiscdclk1" - I2S1 codec clock - optional, + - "iiscdclk2" - I2S2 codec clock - optional, + - "pcmcdclk0" - PCM0 codec clock - optional, + - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410. + +Example: Clock controller node: + + clock: clock-controller at 7e00f000 { + compatible = "samsung,s3c6410-clock"; + reg = <0x7e00f000 0x1000>; + #clock-cells = <1>; + }; + +Example: Required external clocks: + + fin_pll: clock-fin-pll { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + clock-frequency = <12000000>; + #clock-cells = <0>; + }; + + xusbxti: clock-xusbxti { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller (refer to the standard clock bindings for information about + "clocks" and "clock-names" properties): + + uart0: serial at 7f005000 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <5>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>, + <&clock SCLK_UART>; + status = "disabled"; + };
drivers/clk/samsung/Makefile +3 -0
@@ -8,3 +8,6 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o +ifdef CONFIG_COMMON_CLK +obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o +endif
drivers/clk/samsung/clk-s3c64xx.c new file +465 -0
465 lines not on this page · raw message
include/dt-bindings/clock/samsung,s3c64xx-clock.h new file +178 -0
178 lines not on this page · raw message
Signature · 1 line
1.8.3.2
PATCH v3 3/8 clk: samsung: Add clock driver for S3C64xx SoCs
This patch adds new, Common Clock Framework-based clock driver for Samsung S3C64xx SoCs. The driver is just added, without actually letting the platforms use it yet, since this requires more intermediate steps.
--- .../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++++ drivers/clk/samsung/Makefile | 3 + drivers/clk/samsung/clk-s3c64xx.c | 473 +++++++++++++++++++++ include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++++++ 4 files changed, 731 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt create mode 100644 drivers/clk/samsung/clk-s3c64xx.c create mode 100644 include/dt-bindings/clock/samsung,s3c64xx-clock.h
Changes since v2:
- Reworked to use new PLL registration method introduced by Yadwinder Singh Brar's patch series:
( http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20041 )
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt new file +77 -0
@@ -0,0 +1,77 @@ +* Samsung S3C64xx Clock Controller + +The S3C64xx clock controller generates and supplies clock to various controllers +within the SoC. The clock binding described here is applicable to all SoCs in +the S3C64xx family. + +Required Properties: + +- compatible: should be one of the following. + - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC. + - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. Some of the clocks are available only +on a particular S3C64xx SoC and this is specified where applicable. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device +tree sources. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "fin_pll" - PLL input clock (xtal/extclk) - required, + - "xusbxti" - USB xtal - required, + - "iiscdclk0" - I2S0 codec clock - optional, + - "iiscdclk1" - I2S1 codec clock - optional, + - "iiscdclk2" - I2S2 codec clock - optional, + - "pcmcdclk0" - PCM0 codec clock - optional, + - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410. + +Example: Clock controller node: + + clock: clock-controller at 7e00f000 { + compatible = "samsung,s3c6410-clock"; + reg = <0x7e00f000 0x1000>; + #clock-cells = <1>; + }; + +Example: Required external clocks: + + fin_pll: clock-fin-pll { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + clock-frequency = <12000000>; + #clock-cells = <0>; + }; + + xusbxti: clock-xusbxti { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller (refer to the standard clock bindings for information about + "clocks" and "clock-names" properties): + + uart0: serial at 7f005000 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <5>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>, + <&clock SCLK_UART>; + status = "disabled"; + };
drivers/clk/samsung/Makefile +3 -0
@@ -8,3 +8,6 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o +ifdef CONFIG_COMMON_CLK +obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o +endif
drivers/clk/samsung/clk-s3c64xx.c new file +473 -0
473 lines not on this page · raw message
include/dt-bindings/clock/samsung,s3c64xx-clock.h new file +178 -0
178 lines not on this page · raw message
Signature · 1 line
1.8.3.2
PATCH v2 4/8 ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
In reply to Tomasz FigaThis patch adds soc_is_s3c6400() and soc_is_s3c6410() macros that allow to distinguish between specific SoCs from s3c64xx series that is needed to handle differences between them.
--- arch/arm/plat-samsung/include/plat/cpu.h | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/plat-samsung/include/plat/cpu.h +4 -0
@@ -87,8 +87,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)#endif #if defined(CONFIG_CPU_S3C6400 ) || defined(CONFIG_CPU_S3C6410 ) +# define soc_is_s3c6400 () is_samsung_s3c6400() +# define soc_is_s3c6410 () is_samsung_s3c6410()# define soc_is_s3c64xx () (is_samsung_s3c6400() || is_samsung_s3c6410())#else +# define soc_is_s3c6400 () 0 +# define soc_is_s3c6410 () 0# define soc_is_s3c64xx () 0#endif
Signature · 1 line
1.8.3.2
PATCH v2 5/8 ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
In reply to Tomasz FigaThis patch modifies s3c64xx DMA driver to prepare and unprepare clocks in addition to enableind and disabling, since it is required by common clock framework.
--- arch/arm/mach-s3c64xx/dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/mach-s3c64xx/dma.c +2 -2
@@ -677,7 +677,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, goto err_map; } -clk_enable (dmac->clk); +clk_prepare_enable (dmac->clk); dmac->regs = regs; dmac->chanbase = chbase;
@@ -711,7 +711,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,return 0 ; err_clk: -clk_disable (dmac->clk); +clk_disable_unprepare (dmac->clk);clk_put (dmac->clk); err_map:iounmap (regs);
Signature · 1 line
1.8.3.2
PATCH v2 5/8 ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
Quoted 3 lines · Tomasz Figa
This patch modifies s3c64xx DMA driver to prepare and unprepare clocks in addition to enableind and disabling, since it is required by common clock framework.
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PATCH v2 6/8 usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
In reply to Tomasz FigaThis patch modifies the ohci-s3c2410 driver to prepare and unprepare clocks in addition to enabling and disabling, since it is required by common clock framework.
--- drivers/usb/host/ohci-s3c2410.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/usb/host/ohci-s3c2410.c +4 -4
@@ -47,10 +47,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)dev_dbg (&dev->dev,"s3c2410_start_hc:\n" ); -clk_enable (usb_clk); +clk_prepare_enable (usb_clk);mdelay (2 );/* let the bus clock stabilise */ -clk_enable (clk); +clk_prepare_enable (clk);if (info !=NULL ) { info->hcd = hcd;
@@ -75,8 +75,8 @@ static void s3c2410_stop_hc(struct platform_device *dev) (info->enable_oc)(info,0 ); } -clk_disable (clk); -clk_disable (usb_clk); +clk_disable_unprepare (clk); +clk_disable_unprepare (usb_clk); }/* ohci_s3c2410_hub_status_data
Signature · 1 line
1.8.3.2
PATCH v2 6/8 usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
drivers/usb/host/ohci-s3c2410.c static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd) · line 50
Quoted 4 lines · Tomasz Figa
dev_dbg(&dev->dev, "s3c2410_start_hc:\n");drivers/usb/host/ohci-s3c2410.c +1
-1-clk_enable (usb_clk); +clk_prepare_enable (usb_clk);
clk_prepare_enable may fail, so you would better check its return value.
PATCH v2 6/8 usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
Quoted 1 line · On Monday 22 of July 2013 21:15:12 Fabio Estevam wrote:
On Mon, Jul 22, 2013 at 8:49 PM, Tomasz Figa <[email protected]>
Quoted 7 lines · wrote:
drivers/usb/host/ohci-s3c2410.c static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd) · line 50
Quoted 4 lines
dev_dbg(&dev->dev, "s3c2410_start_hc:\n");drivers/usb/host/ohci-s3c2410.c +1
-1-clk_enable (usb_clk); +clk_prepare_enable (usb_clk);
clk_prepare_enablemay fail, so you would better check its return
value.
Well, ideally yes, but since this driver doesn't have any error path here anyway and on Samsung platforms clk_prepare_enable() simply can't fail, I'd keep it this way until somebody fixes this driver, as it has more issues than just this one.
Best regards,
Tomasz
PATCH v2 6/8 usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
In reply to Tomasz FigaAlan, Greg,
Quoted 28 lines · On Tuesday 23 of July 2013 01:49:23 Tomasz Figa wrote:
This patch modifies the ohci-s3c2410 driver to prepare and unprepare clocks in addition to enabling and disabling, since it is required by common clock framework.
Signed-off-by Tomasz Figa <[email protected]>--- drivers/usb/host/ohci-s3c2410.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)(quoted diff) +0
-0
b/drivers/usb/host/ohci-s3c2410.cindex e125770..db096bf 100644drivers/usb/host/ohci-s3c2410.c +2
-2@@ -47,10 +47,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)dev_dbg (&dev->dev,"s3c2410_start_hc:\n" ); -clk_enable (usb_clk); +clk_prepare_enable (usb_clk);mdelay (2 );/* let the bus clock stabilise */ -clk_enable (clk); +clk_prepare_enable (clk);if (info !=NULL ) {drivers/usb/host/ohci-s3c2410.c +0
-0info->hcd = hcd;
drivers/usb/host/ohci-s3c2410.c static void s3c2410_stop_hc(struct platform_device · line 82
Quoted 10 lines
drivers/usb/host/ohci-s3c2410.c +2
-2@@ -75,8 +75,8 @@ static void s3c2410_stop_hc(struct platform_device *dev) (info->enable_oc)(info, 0); } -clk_disable (clk); -clk_disable (usb_clk); +clk_disable_unprepare (clk); +clk_disable_unprepare (usb_clk); }/* ohci_s3c2410_hub_status_data
Any chance to get your ack on this?
Best regards,
Tomasz
Alan Stern
maintainerPATCH v2 6/8 usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
Quoted 40 lines · Tomasz Figa
Alan, Greg,
Quoted 37 lines · On Tuesday 23 of July 2013 01:49:23 Tomasz Figa wrote:
This patch modifies the ohci-s3c2410 driver to prepare and unprepare clocks in addition to enabling and disabling, since it is required by common clock framework.
Signed-off-by Tomasz Figa <[email protected]>--- drivers/usb/host/ohci-s3c2410.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)(quoted diff) +0
-0
b/drivers/usb/host/ohci-s3c2410.cindex e125770..db096bf 100644drivers/usb/host/ohci-s3c2410.c +2
-2@@ -47,10 +47,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)dev_dbg (&dev->dev,"s3c2410_start_hc:\n" ); -clk_enable (usb_clk); +clk_prepare_enable (usb_clk);mdelay (2 );/* let the bus clock stabilise */ -clk_enable (clk); +clk_prepare_enable (clk);if (info !=NULL ) {drivers/usb/host/ohci-s3c2410.c +2
-2info->hcd = hcd;@@ -75,8 +75,8 @@ static void s3c2410_stop_hc(struct platform_device *dev) (info->enable_oc)(info, 0); } -clk_disable (clk); -clk_disable (usb_clk); +clk_disable_unprepare (clk); +clk_disable_unprepare (usb_clk); }
Quoted 3 lines
drivers/usb/host/ohci-s3c2410.c static void s3c2410_stop_hc(struct platform_device *dev) · line 82
Quoted 1 line
drivers/usb/host/ohci-s3c2410.c +0
-0/* ohci_s3c2410_hub_status_data Any chance to get your ack on this?
Sorry, this must have slipped past. It's fine with me.
Alan Stern
Greg KH
maintainerPATCH v2 6/8 usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
Quoted 42 lines · Alan Stern
Quoted 40 lines · Tomasz Figa
Alan, Greg,
Quoted 37 lines · On Tuesday 23 of July 2013 01:49:23 Tomasz Figa wrote:
This patch modifies the ohci-s3c2410 driver to prepare and unprepare clocks in addition to enabling and disabling, since it is required by common clock framework.
Signed-off-by Tomasz Figa <[email protected]>--- drivers/usb/host/ohci-s3c2410.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)(quoted diff) +0
-0
b/drivers/usb/host/ohci-s3c2410.cindex e125770..db096bf 100644drivers/usb/host/ohci-s3c2410.c +2
-2@@ -47,10 +47,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)dev_dbg (&dev->dev,"s3c2410_start_hc:\n" ); -clk_enable (usb_clk); +clk_prepare_enable (usb_clk);mdelay (2 );/* let the bus clock stabilise */ -clk_enable (clk); +clk_prepare_enable (clk);if (info !=NULL ) {drivers/usb/host/ohci-s3c2410.c +2
-2info->hcd = hcd;@@ -75,8 +75,8 @@ static void s3c2410_stop_hc(struct platform_device *dev) (info->enable_oc)(info, 0); } -clk_disable (clk); -clk_disable (usb_clk); +clk_disable_unprepare (clk); +clk_disable_unprepare (usb_clk); }
Quoted 5 lines
Quoted 3 lines
drivers/usb/host/ohci-s3c2410.c static void s3c2410_stop_hc(struct platform_device *dev) · line 82
Quoted 1 line
drivers/usb/host/ohci-s3c2410.c +0
-0/* ohci_s3c2410_hub_status_data Any chance to get your ack on this?
Sorry, this must have slipped past. It's fine with me.
PATCH v2 7/8 ARM: s3c64xx: Migrate clock handling to Common Clock Framework
In reply to Tomasz FigaThis patch migrates the s3c64xx platform to use the new clock driver using Common Clock Framework.
--- arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/common.c | 21 +++++++++++++++++---- arch/arm/mach-s3c64xx/common.h | 10 +++++----- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 ++--------- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/s3c6400.c | 6 ------ arch/arm/mach-s3c64xx/s3c6410.c | 7 ------- drivers/clk/samsung/Makefile | 2 -- 15 files changed, 33 insertions(+), 42 deletions(-)
arch/arm/Kconfig +1 -1
@@ -724,6 +724,7 @@ config ARCH_S3C64XX select ARM_VIC select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM + select COMMON_CLK select CPU_V6 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG
@@ -737,7 +738,6 @@ config ARCH_S3C64XX select S3C_DEV_NAND select S3C_GPIO_TRACK select SAMSUNG_ATAGS - select SAMSUNG_CLKSRC select SAMSUNG_GPIOLIB_4BIT select SAMSUNG_WDT_RESET select USB_ARCH_HAS_OHCI
arch/arm/mach-s3c64xx/Makefile +1 -1
@@ -12,7 +12,7 @@ obj- := # Core -obj-y += common.o clock.o +obj-y += common.o # Core support
arch/arm/mach-s3c64xx/common.c +17 -4
@@ -17,6 +17,7 @@#include <linux/kernel.h> #include <linux/init.h> #include <linux/module.h> +#include <linux/clk-provider.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/serial_core.h>
@@ -38,7 +39,6 @@#include <mach/regs-gpio.h> #include <plat/cpu.h> -#include <plat/clock.h> #include <plat/devs.h> #include <plat/pm.h> #include <plat/gpio-cfg.h>
@@ -50,6 +50,19 @@#include "common.h" +/* External clock frequency */ +static unsigned long xtal_f =12000000 , xusbxti_f =48000000 ; + +void __init s3c64xx_set_xtal_freq (unsigned long freq) +{ + xtal_f = freq; +} + +void __init s3c64xx_set_xusbxti_freq (unsigned long freq) +{ + xusbxti_f = freq; +} +/* uart registration process */ static void __init s3c64xx_init_uarts (struct s3c2410_uartcfg *cfg,int no)
@@ -67,7 +80,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = S3C6400_CPU_ID, .idmask = S3C64XX_CPU_MASK, .map_io = s3c6400_map_io, - .init_clocks = s3c6400_init_clocks, .init_uarts = s3c64xx_init_uarts, .init = s3c6400_init, .name = name_s3c6400,
@@ -75,7 +87,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = S3C6410_CPU_ID, .idmask = S3C64XX_CPU_MASK, .map_io = s3c6410_map_io, - .init_clocks = s3c6410_init_clocks, .init_uarts = s3c64xx_init_uarts, .init = s3c6410_init, .name = name_s3c6410,
@@ -213,8 +224,10 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) {/* * FIXME: there is no better place to put this at the moment -* (samsung_wdt_reset_init needs clocks) +* (s3c64xx_clk_init needs ioremap and must happen before init_time +* samsung_wdt_reset_init needs clocks) */ +s3c64xx_clk_init (NULL , xtal_f, xusbxti_f,soc_is_s3c6400 (),S3C_VA_SYS );samsung_wdt_reset_init (S3C_VA_WATCHDOG );printk (KERN_DEBUG "%s: initialising interrupts\n" , __func__);
arch/arm/mach-s3c64xx/common.h +5 -5
@@ -22,18 +22,19 @@void s3c64xx_init_irq (u32 vic0,u32 vic1);void s3c64xx_init_io (struct map_desc *mach_desc,int size); -void s3c64xx_register_clocks (unsigned long xtal,unsigned armclk_limit); -void s3c64xx_setup_clocks (void ); -void s3c64xx_restart (enum reboot_mode mode,const char *cmd);void s3c64xx_init_late (void ); +void s3c64xx_clk_init (struct device_node *np,unsigned long xtal_f, +unsigned long xusbxti_f,bool is_s3c6400,void __iomem *reg_base); +void s3c64xx_set_xtal_freq (unsigned long freq); +void s3c64xx_set_xusbxti_freq (unsigned long freq); +#ifdef CONFIG_CPU_S3C6400 extern int s3c6400_init (void );extern void s3c6400_init_irq (void );extern void s3c6400_map_io (void ); -extern void s3c6400_init_clocks (int xtal);#else #define s3c6400_init_clocks NULL
@@ -46,7 +47,6 @@ extern void s3c6400_init_clocks(int xtal);extern int s3c6410_init (void );extern void s3c6410_init_irq (void );extern void s3c6410_map_io (void ); -extern void s3c6410_init_clocks (int xtal);#else #define s3c6410_init_clocks NULL
arch/arm/mach-s3c64xx/mach-anw6410.c +1 -1
@@ -207,7 +207,7 @@ static struct platform_device *anw6410_devices[] __initdata = {static void __init anw6410_map_io (void ) {s3c64xx_init_io (anw6410_iodesc,ARRAY_SIZE (anw6410_iodesc)); -s3c24xx_init_clocks (12000000 ); +s3c64xx_set_xtal_freq (12000000 );s3c24xx_init_uarts (anw6410_uartcfgs,ARRAY_SIZE (anw6410_uartcfgs));samsung_set_timer_source (SAMSUNG_PWM3 ,SAMSUNG_PWM4 );
arch/arm/mach-s3c64xx/mach-crag6410.c +1 -1
@@ -743,7 +743,7 @@ static struct s3c2410_platform_i2c i2c1_pdata = {static void __init crag6410_map_io (void ) {s3c64xx_init_io (NULL ,0 ); -s3c24xx_init_clocks (12000000 ); +s3c64xx_set_xtal_freq (12000000 );s3c24xx_init_uarts (crag6410_uartcfgs,ARRAY_SIZE (crag6410_uartcfgs));samsung_set_timer_source (SAMSUNG_PWM3 ,SAMSUNG_PWM4 );
arch/arm/mach-s3c64xx/mach-hmt.c +1 -1
@@ -247,7 +247,7 @@ static struct platform_device *hmt_devices[] __initdata = {static void __init hmt_map_io (void ) {s3c64xx_init_io (hmt_iodesc,ARRAY_SIZE (hmt_iodesc)); -s3c24xx_init_clocks (12000000 ); +s3c64xx_set_xtal_freq (12000000 );s3c24xx_init_uarts (hmt_uartcfgs,ARRAY_SIZE (hmt_uartcfgs));samsung_set_timer_source (SAMSUNG_PWM3 ,SAMSUNG_PWM4 ); }
arch/arm/mach-s3c64xx/mach-mini6410.c +1 -1
@@ -231,7 +231,7 @@ static void __init mini6410_map_io(void)u32 tmp;s3c64xx_init_io (NULL ,0 ); -s3c24xx_init_clocks (12000000 ); +s3c64xx_set_xtal_freq (12000000 );s3c24xx_init_uarts (mini6410_uartcfgs,ARRAY_SIZE (mini6410_uartcfgs));samsung_set_timer_source (SAMSUNG_PWM3 ,SAMSUNG_PWM4 );
arch/arm/mach-s3c64xx/mach-ncp.c +1 -1
@@ -86,7 +86,7 @@ static struct map_desc ncp_iodesc[] __initdata = {};static void __init ncp_map_io (void ) {s3c64xx_init_io (ncp_iodesc,ARRAY_SIZE (ncp_iodesc)); -s3c24xx_init_clocks (12000000 ); +s3c64xx_set_xtal_freq (12000000 );s3c24xx_init_uarts (ncp_uartcfgs,ARRAY_SIZE (ncp_uartcfgs));samsung_set_timer_source (SAMSUNG_PWM3 ,SAMSUNG_PWM4 ); }
arch/arm/mach-s3c64xx/mach-smartq.c +2 -9
@@ -337,13 +337,6 @@ err:return ret; } -static int __init smartq_usb_otg_init (void ) -{ - clk_xusbxti.rate =12000000 ; - -return 0 ; -} -static int __init smartq_wifi_init (void ) {int ret;
@@ -377,7 +370,8 @@ static struct map_desc smartq_iodesc[] __initdata = {};void __init smartq_map_io (void ) {s3c64xx_init_io (smartq_iodesc,ARRAY_SIZE (smartq_iodesc)); -s3c24xx_init_clocks (12000000 ); +s3c64xx_set_xtal_freq (12000000 ); +s3c64xx_set_xusbxti_freq (12000000 );s3c24xx_init_uarts (smartq_uartcfgs,ARRAY_SIZE (smartq_uartcfgs));samsung_set_timer_source (SAMSUNG_PWM3 ,SAMSUNG_PWM4 );
@@ -399,7 +393,6 @@ void __init smartq_machine_init(void)WARN_ON (smartq_lcd_setup_gpio ());WARN_ON (smartq_power_off_init ());WARN_ON (smartq_usb_host_init ()); -WARN_ON (smartq_usb_otg_init ());WARN_ON (smartq_wifi_init ());platform_add_devices (smartq_devices,ARRAY_SIZE (smartq_devices));
arch/arm/mach-s3c64xx/mach-smdk6400.c +1 -1
@@ -65,7 +65,7 @@ static struct map_desc smdk6400_iodesc[] = {};static void __init smdk6400_map_io (void ) {s3c64xx_init_io (smdk6400_iodesc,ARRAY_SIZE (smdk6400_iodesc)); -s3c24xx_init_clocks (12000000 ); +s3c64xx_set_xtal_freq (12000000 );s3c24xx_init_uarts (smdk6400_uartcfgs,ARRAY_SIZE (smdk6400_uartcfgs));samsung_set_timer_source (SAMSUNG_PWM3 ,SAMSUNG_PWM4 ); }
arch/arm/mach-s3c64xx/mach-smdk6410.c +1 -1
@@ -634,7 +634,7 @@ static void __init smdk6410_map_io(void)u32 tmp;s3c64xx_init_io (smdk6410_iodesc,ARRAY_SIZE (smdk6410_iodesc)); -s3c24xx_init_clocks (12000000 ); +s3c64xx_set_xtal_freq (12000000 );s3c24xx_init_uarts (smdk6410_uartcfgs,ARRAY_SIZE (smdk6410_uartcfgs));samsung_set_timer_source (SAMSUNG_PWM3 ,SAMSUNG_PWM4 );
arch/arm/mach-s3c64xx/s3c6400.c +0 -6
@@ -58,12 +58,6 @@ void __init s3c6400_map_io(void)s3c64xx_onenand1_setname ("s3c6400-onenand" ); } -void __init s3c6400_init_clocks (int xtal) -{ -s3c64xx_register_clocks (xtal,S3C6400_CLKDIV0_ARM_MASK ); -s3c64xx_setup_clocks (); -} -void __init s3c6400_init_irq (void ) {/* VIC0 does not have IRQS 5..7,
arch/arm/mach-s3c64xx/s3c6410.c +0 -7
@@ -62,13 +62,6 @@ void __init s3c6410_map_io(void)s3c_cfcon_setname ("s3c64xx-pata" ); } -void __init s3c6410_init_clocks (int xtal) -{ -printk (KERN_DEBUG "%s: initialising clocks\n" , __func__); -s3c64xx_register_clocks (xtal,S3C6410_CLKDIV0_ARM_MASK ); -s3c64xx_setup_clocks (); -} -void __init s3c6410_init_irq (void ) {/* VIC0 is missing IRQ7, VIC1 is fully populated. */
drivers/clk/samsung/Makefile +0 -2
@@ -8,6 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o -ifdef CONFIG_COMMON_CLK obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o -endif
Signature · 1 line
1.8.3.2
PATCH v2 8/8 ARM: s3c64xx: Remove old clock management code
In reply to Tomasz FigaThis patch removes old clock management code of S3C64xx, since the platform has been already moved to the new clock driver using Common Clock Framework.
--- arch/arm/mach-s3c64xx/clock.c | 1007 ----------------------- arch/arm/mach-s3c64xx/common.h | 2 - arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/pm.c | 21 - 4 files changed, 4 insertions(+), 1158 deletions(-) delete mode 100644 arch/arm/mach-s3c64xx/clock.c
arch/arm/mach-s3c64xx/clock.c deleted +0 -1007
@@ -1,1007 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/clock.c -* -* Copyright 2008 Openmoko, Inc. -* Copyright 2008 Simtec Electronics -* Ben Dooks <[email protected]> -* http://armlinux.simtec.co.uk/ -* -* S3C64XX Base clock support -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <mach/regs-clock.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/cpu-freq.h> -#include <plat/clock.h> -#include <plat/clock-clksrc.h> -#include <plat/pll.h> - -#include "regs-sys.h" - -/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call -* ext_xtal_mux for want of an actual name from the manual. -*/ - -static struct clk clk_ext_xtal_mux = { - .name ="ext_xtal" , -}; - -#define clk_fin_apll clk_ext_xtal_mux -#define clk_fin_mpll clk_ext_xtal_mux -#define clk_fin_epll clk_ext_xtal_mux - -#define clk_fout_mpll clk_mpll -#define clk_fout_epll clk_epll - -struct clk clk_h2 = { - .name ="hclk2" , - .rate =0 , -}; - -struct clk clk_27m = { - .name ="clk_27m" , - .rate =27000000 , -}; - -static int clk_48m_ctrl (struct clk *clk,int enable) -{ -unsigned long flags; -u32 val; - -/* can't rely on clock lock, this register has other usages */ -local_irq_save (flags); - - val =__raw_readl (S3C64XX_OTHERS ); -if (enable) - val |=S3C64XX_OTHERS_USBMASK ; -else - val &= ~S3C64XX_OTHERS_USBMASK ; - -__raw_writel (val,S3C64XX_OTHERS ); -local_irq_restore (flags); - -return 0 ; -} - -struct clk clk_48m = { - .name ="clk_48m" , - .rate =48000000 , - .enable = clk_48m_ctrl, -}; - -struct clk clk_xusbxti = { - .name ="xusbxti" , - .rate =48000000 , -}; - -static int inline s3c64xx_gate (void __iomem *reg, -struct clk *clk, -int enable) -{ -unsigned int ctrlbit = clk->ctrlbit; -u32 con; - - con =__raw_readl (reg); - -if (enable) - con |= ctrlbit; -else - con &= ~ctrlbit; - -__raw_writel (con, reg); -return 0 ; -} - -static int s3c64xx_pclk_ctrl (struct clk *clk,int enable) -{ -return s3c64xx_gate (S3C_PCLK_GATE , clk, enable); -} - -static int s3c64xx_hclk_ctrl (struct clk *clk,int enable) -{ -return s3c64xx_gate (S3C_HCLK_GATE , clk, enable); -} - -int s3c64xx_sclk_ctrl (struct clk *clk,int enable) -{ -return s3c64xx_gate (S3C_SCLK_GATE , clk, enable); -} - -static struct clk init_clocks_off[] = { - { - .name ="nand" , - .parent = &clk_h, - }, { - .name ="rtc" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_RTC , - }, { - .name ="adc" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_TSADC , - }, { - .name ="i2c" , - .devname ="s3c2440-i2c.0" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_IIC , - }, { - .name ="i2c" , - .devname ="s3c2440-i2c.1" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C6410_CLKCON_PCLK_I2C1 , - }, { - .name ="keypad" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_KEYPAD , - }, { - .name ="spi" , - .devname ="s3c6410-spi.0" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_SPI0 , - }, { - .name ="spi" , - .devname ="s3c6410-spi.1" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_SPI1 , - }, { - .name ="48m" , - .devname ="s3c-sdhci.0" , - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_MMC0_48 , - }, { - .name ="48m" , - .devname ="s3c-sdhci.1" , - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_MMC1_48 , - }, { - .name ="48m" , - .devname ="s3c-sdhci.2" , - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_MMC2_48 , - }, { - .name ="ac97" , - .parent = &clk_p, - .ctrlbit =S3C_CLKCON_PCLK_AC97 , - }, { - .name ="cfcon" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_IHOST , - }, { - .name ="dma0" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_DMA0 , - }, { - .name ="dma1" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_DMA1 , - }, { - .name ="3dse" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_3DSE , - }, { - .name ="hclk_secur" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_SECUR , - }, { - .name ="sdma1" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_SDMA1 , - }, { - .name ="sdma0" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_SDMA0 , - }, { - .name ="hclk_jpeg" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_JPEG , - }, { - .name ="camif" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_CAMIF , - }, { - .name ="hclk_scaler" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_SCALER , - }, { - .name ="2d" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_2D , - }, { - .name ="tv" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_TV , - }, { - .name ="post0" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_POST0 , - }, { - .name ="rot" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_ROT , - }, { - .name ="hclk_mfc" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_MFC , - }, { - .name ="pclk_mfc" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_MFC , - }, { - .name ="dac27" , - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_DAC27 , - }, { - .name ="tv27" , - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_TV27 , - }, { - .name ="scaler27" , - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_SCALER27 , - }, { - .name ="sclk_scaler" , - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_SCALER , - }, { - .name ="post0_27" , - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_POST0_27 , - }, { - .name ="secur" , - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_SECUR , - }, { - .name ="sclk_mfc" , - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_MFC , - }, { - .name ="sclk_jpeg" , - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_JPEG , - }, -}; - -static struct clk clk_48m_spi0 = { - .name ="spi_48m" , - .devname ="s3c6410-spi.0" , - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_SPI0_48 , -}; - -static struct clk clk_48m_spi1 = { - .name ="spi_48m" , - .devname ="s3c6410-spi.1" , - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit =S3C_CLKCON_SCLK_SPI1_48 , -}; - -static struct clk clk_i2s0 = { - .name ="iis" , - .devname ="samsung-i2s.0" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_IIS0 , -}; - -static struct clk clk_i2s1 = { - .name ="iis" , - .devname ="samsung-i2s.1" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_IIS1 , -}; - -#ifdef CONFIG_CPU_S3C6410 -static struct clk clk_i2s2 = { - .name ="iis" , - .devname ="samsung-i2s.2" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C6410_CLKCON_PCLK_IIS2 , -}; -#endif - -static struct clk init_clocks[] = { - { - .name ="lcd" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_LCD , - }, { - .name ="gpio" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_GPIO , - }, { - .name ="usb-host" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_UHOST , - }, { - .name ="otg" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_USB , - }, { - .name ="timers" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_PWM , - }, { - .name ="uart" , - .devname ="s3c6400-uart.0" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_UART0 , - }, { - .name ="uart" , - .devname ="s3c6400-uart.1" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_UART1 , - }, { - .name ="uart" , - .devname ="s3c6400-uart.2" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_UART2 , - }, { - .name ="uart" , - .devname ="s3c6400-uart.3" , - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit =S3C_CLKCON_PCLK_UART3 , - }, { - .name ="watchdog" , - .parent = &clk_p, - .ctrlbit =S3C_CLKCON_PCLK_WDT , - }, -}; - -static struct clk clk_hsmmc0 = { - .name ="hsmmc" , - .devname ="s3c-sdhci.0" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_HSMMC0 , -}; - -static struct clk clk_hsmmc1 = { - .name ="hsmmc" , - .devname ="s3c-sdhci.1" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_HSMMC1 , -}; - -static struct clk clk_hsmmc2 = { - .name ="hsmmc" , - .devname ="s3c-sdhci.2" , - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit =S3C_CLKCON_HCLK_HSMMC2 , -}; - -static struct clk clk_fout_apll = { - .name ="fout_apll" , -}; - -static struct clk *clk_src_apll_list[] = { - [0 ] = &clk_fin_apll, - [1 ] = &clk_fout_apll, -}; - -static struct clksrc_sources clk_src_apll = { - .sources = clk_src_apll_list, - .nr_sources =ARRAY_SIZE (clk_src_apll_list), -}; - -static struct clksrc_clk clk_mout_apll = { - .clk = { - .name ="mout_apll" , - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =0 , .size =1 }, - .sources = &clk_src_apll, -}; - -static struct clk *clk_src_epll_list[] = { - [0 ] = &clk_fin_epll, - [1 ] = &clk_fout_epll, -}; - -static struct clksrc_sources clk_src_epll = { - .sources = clk_src_epll_list, - .nr_sources =ARRAY_SIZE (clk_src_epll_list), -}; - -static struct clksrc_clk clk_mout_epll = { - .clk = { - .name ="mout_epll" , - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =2 , .size =1 }, - .sources = &clk_src_epll, -}; - -static struct clk *clk_src_mpll_list[] = { - [0 ] = &clk_fin_mpll, - [1 ] = &clk_fout_mpll, -}; - -static struct clksrc_sources clk_src_mpll = { - .sources = clk_src_mpll_list, - .nr_sources =ARRAY_SIZE (clk_src_mpll_list), -}; - -static struct clksrc_clk clk_mout_mpll = { - .clk = { - .name ="mout_mpll" , - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =1 , .size =1 }, - .sources = &clk_src_mpll, -}; - -static unsigned int armclk_mask; - -static unsigned long s3c64xx_clk_arm_get_rate (struct clk *clk) -{ -unsigned long rate =clk_get_rate (clk->parent); -u32 clkdiv; - -/* divisor mask starts at bit0, so no need to shift */ - clkdiv =__raw_readl (S3C_CLK_DIV0 ) & armclk_mask; - -return rate / (clkdiv +1 ); -} - -static unsigned long s3c64xx_clk_arm_round_rate (struct clk *clk, -unsigned long rate) -{ -unsigned long parent =clk_get_rate (clk->parent); -u32 div; - -if (parent < rate) -return parent; - - div = (parent / rate) -1 ; -if (div > armclk_mask) - div = armclk_mask; - -return parent / (div +1 ); -} - -static int s3c64xx_clk_arm_set_rate (struct clk *clk,unsigned long rate) -{ -unsigned long parent =clk_get_rate (clk->parent); -u32 div; -u32 val; - -if (rate < parent / (armclk_mask +1 )) -return -EINVAL ; - - rate =clk_round_rate (clk, rate); - div =clk_get_rate (clk->parent) / rate; - - val =__raw_readl (S3C_CLK_DIV0 ); - val &= ~armclk_mask; - val |= (div -1 ); -__raw_writel (val,S3C_CLK_DIV0 ); - -return 0 ; - -} - -static struct clk clk_arm = { - .name ="armclk" , - .parent = &clk_mout_apll.clk, - .ops = &(struct clk_ops ) { - .get_rate = s3c64xx_clk_arm_get_rate, - .set_rate = s3c64xx_clk_arm_set_rate, - .round_rate = s3c64xx_clk_arm_round_rate, - }, -}; - -static unsigned long s3c64xx_clk_doutmpll_get_rate (struct clk *clk) -{ -unsigned long rate =clk_get_rate (clk->parent); - -printk (KERN_DEBUG "%s: parent is %ld\n" , __func__, rate); - -if (__raw_readl (S3C_CLK_DIV0 ) &S3C6400_CLKDIV0_MPLL_MASK ) - rate /=2 ; - -return rate; -} - -static struct clk_ops clk_dout_ops = { - .get_rate = s3c64xx_clk_doutmpll_get_rate, -}; - -static struct clk clk_dout_mpll = { - .name ="dout_mpll" , - .parent = &clk_mout_mpll.clk, - .ops = &clk_dout_ops, -}; - -static struct clk *clkset_spi_mmc_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_27m, -}; - -static struct clksrc_sources clkset_spi_mmc = { - .sources = clkset_spi_mmc_list, - .nr_sources =ARRAY_SIZE (clkset_spi_mmc_list), -}; - -static struct clk *clkset_irda_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, -NULL , - &clk_27m, -}; - -static struct clksrc_sources clkset_irda = { - .sources = clkset_irda_list, - .nr_sources =ARRAY_SIZE (clkset_irda_list), -}; - -static struct clk *clkset_uart_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, -NULL , -NULL -}; - -static struct clksrc_sources clkset_uart = { - .sources = clkset_uart_list, - .nr_sources =ARRAY_SIZE (clkset_uart_list), -}; - -static struct clk *clkset_uhost_list[] = { - &clk_48m, - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, -}; - -static struct clksrc_sources clkset_uhost = { - .sources = clkset_uhost_list, - .nr_sources =ARRAY_SIZE (clkset_uhost_list), -}; - -/* The peripheral clocks are all controlled via clocksource followed -* by an optional divider and gate stage. We currently roll this into -* one clock which hides the intermediate clock from the mux. -* -* Note, the JPEG clock can only be an even divider... -* -* The scaler and LCD clocks depend on the S3C64XX version, and also -* have a common parent divisor so are not included here. -*/ - -/* clocks that feed other parts of the clock source tree */ - -static struct clk clk_iis_cd0 = { - .name ="iis_cdclk0" , -}; - -static struct clk clk_iis_cd1 = { - .name ="iis_cdclk1" , -}; - -static struct clk clk_iisv4_cd = { - .name ="iis_cdclk_v4" , -}; - -static struct clk clk_pcm_cd = { - .name ="pcm_cdclk" , -}; - -static struct clk *clkset_audio0_list[] = { - [0 ] = &clk_mout_epll.clk, - [1 ] = &clk_dout_mpll, - [2 ] = &clk_fin_epll, - [3 ] = &clk_iis_cd0, - [4 ] = &clk_pcm_cd, -}; - -static struct clksrc_sources clkset_audio0 = { - .sources = clkset_audio0_list, - .nr_sources =ARRAY_SIZE (clkset_audio0_list), -}; - -static struct clk *clkset_audio1_list[] = { - [0 ] = &clk_mout_epll.clk, - [1 ] = &clk_dout_mpll, - [2 ] = &clk_fin_epll, - [3 ] = &clk_iis_cd1, - [4 ] = &clk_pcm_cd, -}; - -static struct clksrc_sources clkset_audio1 = { - .sources = clkset_audio1_list, - .nr_sources =ARRAY_SIZE (clkset_audio1_list), -}; - -#ifdef CONFIG_CPU_S3C6410 -static struct clk *clkset_audio2_list[] = { - [0 ] = &clk_mout_epll.clk, - [1 ] = &clk_dout_mpll, - [2 ] = &clk_fin_epll, - [3 ] = &clk_iisv4_cd, - [4 ] = &clk_pcm_cd, -}; - -static struct clksrc_sources clkset_audio2 = { - .sources = clkset_audio2_list, - .nr_sources =ARRAY_SIZE (clkset_audio2_list), -}; -#endif - -static struct clksrc_clk clksrcs[] = { - { - .clk = { - .name ="usb-bus-host" , - .ctrlbit =S3C_CLKCON_SCLK_UHOST , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =5 , .size =2 }, - .reg_div = { .reg =S3C_CLK_DIV1 , .shift =20 , .size =4 }, - .sources = &clkset_uhost, - }, { - .clk = { - .name ="irda-bus" , - .ctrlbit =S3C_CLKCON_SCLK_IRDA , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =24 , .size =2 }, - .reg_div = { .reg =S3C_CLK_DIV2 , .shift =20 , .size =4 }, - .sources = &clkset_irda, - }, { - .clk = { - .name ="camera" , - .ctrlbit =S3C_CLKCON_SCLK_CAM , - .enable = s3c64xx_sclk_ctrl, - .parent = &clk_h2, - }, - .reg_div = { .reg =S3C_CLK_DIV0 , .shift =20 , .size =4 }, - }, -}; - -/* Where does UCLK0 come from? */ -static struct clksrc_clk clk_sclk_uclk = { - .clk = { - .name ="uclk1" , - .ctrlbit =S3C_CLKCON_SCLK_UART , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =13 , .size =1 }, - .reg_div = { .reg =S3C_CLK_DIV2 , .shift =16 , .size =4 }, - .sources = &clkset_uart, -}; - -static struct clksrc_clk clk_sclk_mmc0 = { - .clk = { - .name ="mmc_bus" , - .devname ="s3c-sdhci.0" , - .ctrlbit =S3C_CLKCON_SCLK_MMC0 , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =18 , .size =2 }, - .reg_div = { .reg =S3C_CLK_DIV1 , .shift =0 , .size =4 }, - .sources = &clkset_spi_mmc, -}; - -static struct clksrc_clk clk_sclk_mmc1 = { - .clk = { - .name ="mmc_bus" , - .devname ="s3c-sdhci.1" , - .ctrlbit =S3C_CLKCON_SCLK_MMC1 , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =20 , .size =2 }, - .reg_div = { .reg =S3C_CLK_DIV1 , .shift =4 , .size =4 }, - .sources = &clkset_spi_mmc, -}; - -static struct clksrc_clk clk_sclk_mmc2 = { - .clk = { - .name ="mmc_bus" , - .devname ="s3c-sdhci.2" , - .ctrlbit =S3C_CLKCON_SCLK_MMC2 , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =22 , .size =2 }, - .reg_div = { .reg =S3C_CLK_DIV1 , .shift =8 , .size =4 }, - .sources = &clkset_spi_mmc, -}; - -static struct clksrc_clk clk_sclk_spi0 = { - .clk = { - .name ="spi-bus" , - .devname ="s3c6410-spi.0" , - .ctrlbit =S3C_CLKCON_SCLK_SPI0 , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =14 , .size =2 }, - .reg_div = { .reg =S3C_CLK_DIV2 , .shift =0 , .size =4 }, - .sources = &clkset_spi_mmc, -}; - -static struct clksrc_clk clk_sclk_spi1 = { - .clk = { - .name ="spi-bus" , - .devname ="s3c6410-spi.1" , - .ctrlbit =S3C_CLKCON_SCLK_SPI1 , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =16 , .size =2 }, - .reg_div = { .reg =S3C_CLK_DIV2 , .shift =4 , .size =4 }, - .sources = &clkset_spi_mmc, -}; - -static struct clksrc_clk clk_audio_bus0 = { - .clk = { - .name ="audio-bus" , - .devname ="samsung-i2s.0" , - .ctrlbit =S3C_CLKCON_SCLK_AUDIO0 , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =7 , .size =3 }, - .reg_div = { .reg =S3C_CLK_DIV2 , .shift =8 , .size =4 }, - .sources = &clkset_audio0, -}; - -static struct clksrc_clk clk_audio_bus1 = { - .clk = { - .name ="audio-bus" , - .devname ="samsung-i2s.1" , - .ctrlbit =S3C_CLKCON_SCLK_AUDIO1 , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C_CLK_SRC , .shift =10 , .size =3 }, - .reg_div = { .reg =S3C_CLK_DIV2 , .shift =12 , .size =4 }, - .sources = &clkset_audio1, -}; - -#ifdef CONFIG_CPU_S3C6410 -static struct clksrc_clk clk_audio_bus2 = { - .clk = { - .name ="audio-bus" , - .devname ="samsung-i2s.2" , - .ctrlbit =S3C6410_CLKCON_SCLK_AUDIO2 , - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg =S3C6410_CLK_SRC2 , .shift =0 , .size =3 }, - .reg_div = { .reg =S3C_CLK_DIV2 , .shift =24 , .size =4 }, - .sources = &clkset_audio2, -}; -#endif -/* Clock initialisation code */ - -static struct clksrc_clk *init_parents[] = { - &clk_mout_apll, - &clk_mout_epll, - &clk_mout_mpll, -}; - -static struct clksrc_clk *clksrc_cdev[] = { - &clk_sclk_uclk, - &clk_sclk_mmc0, - &clk_sclk_mmc1, - &clk_sclk_mmc2, - &clk_sclk_spi0, - &clk_sclk_spi1, - &clk_audio_bus0, - &clk_audio_bus1, -}; - -static struct clk *clk_cdev[] = { - &clk_hsmmc0, - &clk_hsmmc1, - &clk_hsmmc2, - &clk_48m_spi0, - &clk_48m_spi1, - &clk_i2s0, - &clk_i2s1, -}; - -static struct clk_lookup s3c64xx_clk_lookup[] = { -CLKDEV_INIT (NULL ,"clk_uart_baud2" , &clk_p), -CLKDEV_INIT (NULL ,"clk_uart_baud3" , &clk_sclk_uclk.clk), -CLKDEV_INIT ("s3c-sdhci.0" ,"mmc_busclk.0" , &clk_hsmmc0), -CLKDEV_INIT ("s3c-sdhci.1" ,"mmc_busclk.0" , &clk_hsmmc1), -CLKDEV_INIT ("s3c-sdhci.2" ,"mmc_busclk.0" , &clk_hsmmc2), -CLKDEV_INIT ("s3c-sdhci.0" ,"mmc_busclk.2" , &clk_sclk_mmc0.clk), -CLKDEV_INIT ("s3c-sdhci.1" ,"mmc_busclk.2" , &clk_sclk_mmc1.clk), -CLKDEV_INIT ("s3c-sdhci.2" ,"mmc_busclk.2" , &clk_sclk_mmc2.clk), -CLKDEV_INIT (NULL ,"spi_busclk0" , &clk_p), -CLKDEV_INIT ("s3c6410-spi.0" ,"spi_busclk1" , &clk_sclk_spi0.clk), -CLKDEV_INIT ("s3c6410-spi.0" ,"spi_busclk2" , &clk_48m_spi0), -CLKDEV_INIT ("s3c6410-spi.1" ,"spi_busclk1" , &clk_sclk_spi1.clk), -CLKDEV_INIT ("s3c6410-spi.1" ,"spi_busclk2" , &clk_48m_spi1), -CLKDEV_INIT ("samsung-i2s.0" ,"i2s_opclk0" , &clk_i2s0), -CLKDEV_INIT ("samsung-i2s.0" ,"i2s_opclk1" , &clk_audio_bus0.clk), -CLKDEV_INIT ("samsung-i2s.1" ,"i2s_opclk0" , &clk_i2s1), -CLKDEV_INIT ("samsung-i2s.1" ,"i2s_opclk1" , &clk_audio_bus1.clk), -#ifdef CONFIG_CPU_S3C6410 -CLKDEV_INIT ("samsung-i2s.2" ,"i2s_opclk0" , &clk_i2s2), -CLKDEV_INIT ("samsung-i2s.2" ,"i2s_opclk1" , &clk_audio_bus2.clk), -#endif -}; - -#define GET_DIV (clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) - -void __init_or_cpufreq s3c64xx_setup_clocks(void) -{ -struct clk *xtal_clk; -unsigned long xtal; -unsigned long fclk; -unsigned long hclk; -unsigned long hclk2; -unsigned long pclk; -unsigned long epll; -unsigned long apll; -unsigned long mpll; -unsigned int ptr; -u32 clkdiv0; - -printk (KERN_DEBUG "%s: registering clocks\n" , __func__); - - clkdiv0 =__raw_readl (S3C_CLK_DIV0 ); -printk (KERN_DEBUG "%s: clkdiv0 = %08x\n" , __func__, clkdiv0); - - xtal_clk =clk_get (NULL ,"xtal" ); -BUG_ON (IS_ERR (xtal_clk)); - - xtal =clk_get_rate (xtal_clk); -clk_put (xtal_clk); - -printk (KERN_DEBUG "%s: xtal is %ld\n" , __func__, xtal); - -/* For now assume the mux always selects the crystal */ - clk_ext_xtal_mux.parent = xtal_clk; - - epll =s3c_get_pll6553x (xtal,__raw_readl (S3C_EPLL_CON0 ), -__raw_readl (S3C_EPLL_CON1 )); - mpll =s3c6400_get_pll (xtal,__raw_readl (S3C_MPLL_CON )); - apll =s3c6400_get_pll (xtal,__raw_readl (S3C_APLL_CON )); - - fclk = mpll; - -printk (KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n" , - apll, mpll, epll); - -if (__raw_readl (S3C64XX_OTHERS ) &S3C64XX_OTHERS_SYNCMUXSEL ) -/* Synchronous mode */ - hclk2 = apll /GET_DIV (clkdiv0,S3C6400_CLKDIV0_HCLK2 ); -else -/* Asynchronous mode */ - hclk2 = mpll /GET_DIV (clkdiv0,S3C6400_CLKDIV0_HCLK2 ); - - hclk = hclk2 /GET_DIV (clkdiv0,S3C6400_CLKDIV0_HCLK ); - pclk = hclk2 /GET_DIV (clkdiv0,S3C6400_CLKDIV0_PCLK ); - -printk (KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n" , - hclk2, hclk, pclk); - - clk_fout_mpll.rate = mpll; - clk_fout_epll.rate = epll; - clk_fout_apll.rate = apll; - - clk_h2.rate = hclk2; - clk_h.rate = hclk; - clk_p.rate = pclk; - clk_f.rate = fclk; - -for (ptr =0 ; ptr <ARRAY_SIZE (init_parents); ptr++) -s3c_set_clksrc (init_parents[ptr], true); - -for (ptr =0 ; ptr <ARRAY_SIZE (clksrcs); ptr++) -s3c_set_clksrc (&clksrcs[ptr], true); -} - -static struct clk *clks1[]__initdata = { - &clk_ext_xtal_mux, - &clk_iis_cd0, - &clk_iis_cd1, - &clk_iisv4_cd, - &clk_pcm_cd, - &clk_mout_epll.clk, - &clk_mout_mpll.clk, - &clk_dout_mpll, - &clk_arm, -}; - -static struct clk *clks[]__initdata = { - &clk_ext, - &clk_epll, - &clk_27m, - &clk_48m, - &clk_h2, - &clk_xusbxti, -}; - -/** -* s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410 -* @xtal: The rate for the clock crystal feeding the PLLs. -* @armclk_divlimit: Divisor mask for ARMCLK. -* -* Register the clocks for the S3C6400 and S3C6410 SoC range, such -* as ARMCLK as well as the necessary parent clocks. -* -* This call does not setup the clocks, which is left to the -* s3c64xx_setup_clocks() call which may be needed by the cpufreq -* or resume code to re-set the clocks if the bootloader has changed -* them. -*/ -void __init s3c64xx_register_clocks (unsigned long xtal, -unsigned armclk_divlimit) -{ -unsigned int cnt; - - armclk_mask = armclk_divlimit; - -s3c24xx_register_baseclocks (xtal); -s3c24xx_register_clocks (clks,ARRAY_SIZE (clks)); - -s3c_register_clocks (init_clocks,ARRAY_SIZE (init_clocks)); - -s3c_register_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off)); -s3c_disable_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off)); - -s3c24xx_register_clocks (clk_cdev,ARRAY_SIZE (clk_cdev)); -for (cnt =0 ; cnt <ARRAY_SIZE (clk_cdev); cnt++) -s3c_disable_clocks (clk_cdev[cnt],1 ); - -s3c24xx_register_clocks (clks1,ARRAY_SIZE (clks1)); -s3c_register_clksrc (clksrcs,ARRAY_SIZE (clksrcs)); -for (cnt =0 ; cnt <ARRAY_SIZE (clksrc_cdev); cnt++) -s3c_register_clksrc (clksrc_cdev[cnt],1 ); -clkdev_add_table (s3c64xx_clk_lookup,ARRAY_SIZE (s3c64xx_clk_lookup)); -}
arch/arm/mach-s3c64xx/common.h +0 -2
@@ -37,7 +37,6 @@ extern void s3c6400_init_irq(void);extern void s3c6400_map_io (void );#else -#define s3c6400_init_clocks NULL#define s3c6400_map_io NULL#define s3c6400_init NULL#endif
@@ -49,7 +48,6 @@ extern void s3c6410_init_irq(void);extern void s3c6410_map_io (void );#else -#define s3c6410_init_clocks NULL#define s3c6410_map_io NULL#define s3c6410_init NULL#endif
arch/arm/mach-s3c64xx/include/mach/regs-clock.h +4 -128
149 lines not on this page · raw message
arch/arm/mach-s3c64xx/pm.c +0 -21
@@ -194,29 +194,8 @@ void s3c_pm_debug_smdkled(u32 set, u32 clear)#endif static struct sleep_save core_save[] = { -SAVE_ITEM (S3C_APLL_LOCK ), -SAVE_ITEM (S3C_MPLL_LOCK ), -SAVE_ITEM (S3C_EPLL_LOCK ), -SAVE_ITEM (S3C_CLK_SRC ), -SAVE_ITEM (S3C_CLK_DIV0 ), -SAVE_ITEM (S3C_CLK_DIV1 ), -SAVE_ITEM (S3C_CLK_DIV2 ), -SAVE_ITEM (S3C_CLK_OUT ), -SAVE_ITEM (S3C_HCLK_GATE ), -SAVE_ITEM (S3C_PCLK_GATE ), -SAVE_ITEM (S3C_SCLK_GATE ), -SAVE_ITEM (S3C_MEM0_GATE ), - -SAVE_ITEM (S3C_EPLL_CON1 ), -SAVE_ITEM (S3C_EPLL_CON0 ), -SAVE_ITEM (S3C64XX_MEM0DRVCON ),SAVE_ITEM (S3C64XX_MEM1DRVCON ), - -#ifndef CONFIG_CPU_FREQ -SAVE_ITEM (S3C_APLL_CON ), -SAVE_ITEM (S3C_MPLL_CON ), -#endif };static struct sleep_save misc_save[] = {
Signature · 1 line
1.8.3.2
v2 cover Common Clock Framework support for Samsung S3C64xx
In reply to Tomasz FigaQuoted 74 lines · Tomasz Figa
This series is an attempt to move clock support on Samsung S3C64xx SoCs to Common Clock Framework.
First, support for PLL types present on S3C64xx SoCs is added to Samsung Common Clock Framework driver. Then the main clock driver for mentioned SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.
Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanup
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa <[email protected]>For v1:
Acked-by Mike Turquette <[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external
clocks.Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt delete mode 100644 arch/arm/mach-s3c64xx/clock.c create mode 100644 drivers/clk/samsung/clk-s3c64xx.c create mode 100644 include/dt-bindings/clock/samsung,s3c64xx-clock.h
Quoted 2 lines
--
1.8.3.2
Looks nice series, thanks.
I've applied this whole series including updated v3 2nd and 3rd patches on top of PWM cleanup series. BTW, if I could get ack on 1st and 6th patches, would be helpful :-)
Regards,
Kukjin
v2 cover Common Clock Framework support for Samsung S3C64xx
In reply to Tomasz FigaQuoted 66 lines · Tomasz Figa
This series is an attempt to move clock support on Samsung S3C64xx SoCs to Common Clock Framework.
First, support for PLL types present on S3C64xx SoCs is added to Samsung Common Clock Framework driver. Then the main clock driver for mentioned SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.
Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)
Quoted 5 lines
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txtdelete mode 100644arch/arm/mach-s3c64xx/clock.c
create mode 100644drivers/clk/samsung/clk-s3c64xx.c
create mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.h
Basically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff in clk tree now...
- Kukjin
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 72 lines · Tomasz Figa
Quoted 66 lines
This series is an attempt to move clock support on Samsung S3C64xx SoCs to Common Clock Framework.
First, support for PLL types present on S3C64xx SoCs is added to Samsung Common Clock Framework driver. Then the main clock driver for mentioned SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.
Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)Quoted 5 lines
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txtdelete mode 100644arch/arm/mach-s3c64xx/clock.c
create mode 100644drivers/clk/samsung/clk-s3c64xx.c
create mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.h
Quoted 3 lines
Basically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff in clk tree now...
Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
If you want I can take 7 & 8 through the clk tree.
Alternatively I can provide patches 1-3 in a separate stable topic branch for you to pull in as a dependency. We'll both merge that stable topic branch into our trees and you can make a note of it for the arm-soc folks.
Regards,
Mike
Quoted 2 lines
- Kukjin
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoted 80 lines · Mike Turquette
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 72 lines · Tomasz Figa
Quoted 66 lines
This series is an attempt to move clock support on Samsung S3C64xx SoCs to Common Clock Framework.
First, support for PLL types present on S3C64xx SoCs is added to Samsung Common Clock Framework driver. Then the main clock driver for mentioned SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.
Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)Quoted 5 lines
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txtdelete mode 100644arch/arm/mach-s3c64xx/clock.c
create mode 100644drivers/clk/samsung/clk-s3c64xx.c
create mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.hQuoted 3 lines
Basically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff in clk tree now...
Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
Quoted 7 lines
If you want I can take 7& 8 through the clk tree.
Alternatively I can provide patches 1-3 in a separate stable topic branch for you to pull in as a dependency. We'll both merge that stable topic branch into our trees and you can make a note of it for the arm-soc folks.
Thanks for your quick response. Would be helpful to samsung tree if you could provide a separate stable topic branch what you suggested for clk stuff in this series.
Of course, I will inform when I send pull-request for this series to arm-soc.
Thanks,
Kukjin
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoting Kukjin Kim (2013-08-05 11:13:55)
Quoted 83 lines · Mike Turquette
Quoted 82 lines
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 72 lines · Tomasz Figa
Quoted 66 lines
This series is an attempt to move clock support on Samsung S3C64xx SoCs to Common Clock Framework.
First, support for PLL types present on S3C64xx SoCs is added to Samsung Common Clock Framework driver. Then the main clock driver for mentioned SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.
Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)Quoted 5 lines
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txtdelete mode 100644arch/arm/mach-s3c64xx/clock.c
create mode 100644drivers/clk/samsung/clk-s3c64xx.c
create mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.hQuoted 3 lines
Basically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff in clk tree now...
Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
If you want I can take 7& 8 through the clk tree.
Quoted 8 lines
Quoted 5 lines
Alternatively I can provide patches 1-3 in a separate stable topic branch for you to pull in as a dependency. We'll both merge that stable topic branch into our trees and you can make a note of it for the arm-soc folks.
Thanks for your quick response. Would be helpful to samsung tree if you could provide a separate stable topic branch what you suggested for clk stuff in this series.
git://git.linaro.org/people/mturquette/linux.git clk-next-s3c64xx
Topic branch contains patches 1-3 of this series on top of v3.11-rc2. I have already merged the same into the clk-next branch.
Regards,
Mike
Quoted 6 lines
Of course, I will inform when I send pull-request for this series to arm-soc.
Thanks,
Kukjin
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoted 108 lines · On Monday 05 of August 2013 12:02:16 Mike Turquette wrote:
Quoting Kukjin Kim (2013-08-05 11:13:55)
Quoted 100 lines · Mike Turquette
Quoted 91 lines
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 81 lines · Tomasz Figa
Quoted 73 lines
This series is an attempt to move clock support on Samsung S3C64xx SoCs
to Common Clock Framework.First, support for PLL types present on S3C64xx SoCs is added to Samsung Common Clock Framework driver. Then the main clock driver for mentioned SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.
Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.> >>>
Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)Quoted 6 lines
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock. txt delete mode 100644arch/arm/mach-s3c64xx/clock.ccreate mode 100644drivers/clk/samsung/clk-s3c64xx.ccreate mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.hQuoted 4 lines
Basically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff
in clk tree now...Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
Quoted 7 lines
If you want I can take 7& 8 through the clk tree.
Alternatively I can provide patches 1-3 in a separate stable topic branch for you to pull in as a dependency. We'll both merge that stable
topic branch into our trees and you can make a note of it for the arm-soc folks.Quoted 5 lines
Thanks for your quick response. Would be helpful to samsung tree if you
could provide a separate stable topic branch what you suggested for clk
stuff in this series.
Quoted 4 lines
git://git.linaro.org/people/mturquette/linux.gitclk-next-s3c64xxTopic branch contains patches 1-3 of this series on top of v3.11-rc2. I have already merged the same into the clk-next branch.
What about the dependency on PWM cleanup series? Patches 7-8 must be merged after them, otherwise there will be a regression, because the old PWM clocksource driver will be broken and so s3c64xx won't boot until moved to new one, which is done by mentioned series.
Best regards,
Tomasz
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoting Tomasz Figa (2013-08-05 16:42:16)
Quoted 111 lines · On Monday 05 of August 2013 12:02:16 Mike Turquette wrote:
Quoted 110 lines
Quoting Kukjin Kim (2013-08-05 11:13:55)
Quoted 100 lines · Mike Turquette
Quoted 91 lines
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 81 lines · Tomasz Figa
Quoted 73 lines
This series is an attempt to move clock support on Samsung S3C64xx SoCs
to Common Clock Framework.First, support for PLL types present on S3C64xx SoCs is added to Samsung Common Clock Framework driver. Then the main clock driver for mentioned SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.
Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.> >>>
Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)Quoted 6 lines
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock. txt delete mode 100644arch/arm/mach-s3c64xx/clock.ccreate mode 100644drivers/clk/samsung/clk-s3c64xx.ccreate mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.hQuoted 4 lines
Basically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff
in clk tree now...Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
Quoted 7 lines
If you want I can take 7& 8 through the clk tree.
Alternatively I can provide patches 1-3 in a separate stable topic branch for you to pull in as a dependency. We'll both merge that stable
topic branch into our trees and you can make a note of it for the arm-soc folks.Quoted 5 lines
Thanks for your quick response. Would be helpful to samsung tree if you
could provide a separate stable topic branch what you suggested for clk
stuff in this series.
git://git.linaro.org/people/mturquette/linux.gitclk-next-s3c64xx
Quoted 7 lines
Quoted 2 lines
Topic branch contains patches 1-3 of this series on top of v3.11-rc2. I have already merged the same into the clk-next branch.
What about the dependency on PWM cleanup series? Patches 7-8 must be merged after them, otherwise there will be a regression, because the old PWM clocksource driver will be broken and so s3c64xx won't boot until moved to new one, which is done by mentioned series.
Is this a question for me? I did not take patches 7 or 8 into clk-next. Sounds like those patches should go through Samsung tree into arm-soc, and perhaps be a late-applied branch to get the ordering right.
Regards,
Mike
Quoted 3 lines
Best regards,
Tomasz
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoted 154 lines · On Tuesday 06 of August 2013 12:47:51 Mike Turquette wrote:
Quoting Tomasz Figa (2013-08-05 16:42:16)
Quoted 152 lines · On Monday 05 of August 2013 12:02:16 Mike Turquette wrote:
Quoted 150 lines
Quoting Kukjin Kim (2013-08-05 11:13:55)
Quoted 135 lines · Mike Turquette
Quoted 126 lines
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 111 lines · Tomasz Figa
Quoted 102 lines
This series is an attempt to move clock support on Samsung S3C64xx
SoCs
to Common Clock Framework.First, support for PLL types present on S3C64xx SoCs is added to
Samsung Common Clock Framework driver. Then the main clock driver
for mentioned SoCs is introduced. Further patches contain fixes
for drivers to make them compliant with CCF semantics, migration
of platform code to use the new clock driver and removal of old
clock management code.Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20 856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.> >>>Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007--------------------
arch/arm/mach-s3c64xx/common.c| 21 +-arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)Quoted 7 lines
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.
txt delete mode 100644arch/arm/mach-s3c64xx/clock.ccreate mode 100644drivers/clk/samsung/clk-s3c64xx.ccreate mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.hQuoted 6 lines
Basically, this series looks good to me, but I'm not sure how this
should be handled because of dependency with PWM cleanup and clk
stuff
in clk tree now...Patches 1-3 can go into the clk tree. 4-6 should go through their
respective trees.If you want I can take 7& 8 through the clk tree.
Quoted 7 lines
Alternatively I can provide patches 1-3 in a separate stable topic
branch for you to pull in as a dependency. We'll both merge that stable
topic branch into our trees and you can make a note of it for the
arm-soc folks.Quoted 7 lines
Thanks for your quick response. Would be helpful to samsung tree if
you
could provide a separate stable topic branch what you suggested for
clk
stuff in this series.
git://git.linaro.org/people/mturquette/linux.gitclk-next-s3c64xxTopic branch contains patches 1-3 of this series on top of v3.11-rc2. I
have already merged the same into the clk-next branch.
Quoted 8 lines
Quoted 4 lines
What about the dependency on PWM cleanup series? Patches 7-8 must be merged after them, otherwise there will be a regression, because the old PWM clocksource driver will be broken and so s3c64xx won't boot until moved to new one, which is done by mentioned series.
Is this a question for me? I did not take patches 7 or 8 into clk-next. Sounds like those patches should go through Samsung tree into arm-soc, and perhaps be a late-applied branch to get the ordering right.
It's just continuation of the topic. I guess the question is mostly for Kukjin. Anyway, your suggestion is most likely the right thing, thanks.
Best regards,
Tomasz
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoted 149 lines · Tomasz Figa
Quoted 148 lines · On Tuesday 06 of August 2013 12:47:51 Mike Turquette wrote:
Quoting Tomasz Figa (2013-08-05 16:42:16)
Quoted 146 lines · On Monday 05 of August 2013 12:02:16 Mike Turquette wrote:
Quoted 145 lines
Quoting Kukjin Kim (2013-08-05 11:13:55)
Quoted 142 lines · Mike Turquette
Quoted 126 lines
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 111 lines · Tomasz Figa
Quoted 101 lines
This series is an attempt to move clock support on Samsung S3C64xx
SoCs
to Common Clock Framework.First, support for PLL types present on S3C64xx SoCs is added to
Samsung Common Clock Framework driver. Then the main clock driver
for mentioned SoCs is introduced. Further patches contain fixes
for drivers to make them compliant with CCF semantics, migration
of platform code to use the new clock driver and removal of old
clock management code.Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20
856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.> >>>Tomasz Figa (8):
clk: mux: Add support for read-only muxes. clk: samsung: pll: Add support for PLL6552 and PLL6553 clk: samsung: Add clock driver for S3C64xx SoCs ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare ARM: s3c64xx: Migrate clock handling to Common Clock Framework ARM: s3c64xx: Remove old clock management code .../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 +Quoted 8 lines
28 files changed, 943 insertions(+), 1205 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c64xx-clo ck. txt delete mode 100644 arch/arm/mach-s3c64xx/clock.c create mode 100644 drivers/clk/samsung/clk-s3c64xx.c create mode 100644 include/dt-bindings/clock/samsung,s3c64xx-clock.hQuoted 6 lines
Basically, this series looks good to me, but I'm not sure how this
should be handled because of dependency with PWM cleanup and clk
stuff
in clk tree now...Patches 1-3 can go into the clk tree. 4-6 should go through their
respective trees.If you want I can take 7& 8 through the clk tree.
Quoted 7 lines
Alternatively I can provide patches 1-3 in a separate stable topic
branch for you to pull in as a dependency. We'll both merge that stable
topic branch into our trees and you can make a note of it for the
arm-soc folks.Thanks for your quick response. Would be helpful to samsung tree if
you
could provide a separate stable topic branch what you suggested for
clk
stuff in this series.
Quoted 6 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines
git://git.linaro.org/people/mturquette/linux.gitclk-next-s3c64xxTopic branch contains patches 1-3 of this series on top of v3.11-rc2. I
have already merged the same into the clk-next branch.
Mike, thanks. I've merged the branch 'clk-next-s3c64xx' into the samsung tree :)
Quoted 5 lines
Quoted 5 lines
Quoted 4 lines
What about the dependency on PWM cleanup series? Patches 7-8 must be merged after them, otherwise there will be a regression, because the old PWM clocksource driver will be broken and so s3c64xx won't boot until moved to new one, which is done by mentioned series.
Quoted 7 lines
Quoted 3 lines
Is this a question for me? I did not take patches 7 or 8 into clk-next. Sounds like those patches should go through Samsung tree into arm-soc, and perhaps be a late-applied branch to get the ordering right.
It's just continuation of the topic. I guess the question is mostly for Kukjin. Anyway, your suggestion is most likely the right thing, thanks.
Tomasz, I can handle. Thanks.
- Kukjin
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoted 170 lines · On Wednesday 07 of August 2013 07:11:40 Kukjin Kim wrote:
Quoted 149 lines · Tomasz Figa
Quoted 148 lines · On Tuesday 06 of August 2013 12:47:51 Mike Turquette wrote:
Quoting Tomasz Figa (2013-08-05 16:42:16)
Quoted 146 lines · On Monday 05 of August 2013 12:02:16 Mike Turquette wrote:
Quoted 145 lines
Quoting Kukjin Kim (2013-08-05 11:13:55)
Quoted 142 lines · Mike Turquette
Quoted 126 lines
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 111 lines · Tomasz Figa
Quoted 101 lines
This series is an attempt to move clock support on Samsung S3C64xx
SoCs
to Common Clock Framework.First, support for PLL types present on S3C64xx SoCs is added to
Samsung Common Clock Framework driver. Then the main clock driver
for mentioned SoCs is introduced. Further patches contain fixes
for drivers to make them compliant with CCF semantics, migration
of platform code to use the new clock driver and removal of old
clock management code.Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20
856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.> >>>Tomasz Figa (8):
clk: mux: Add support for read-only muxes. clk: samsung: pll: Add support for PLL6552 and PLL6553 clk: samsung: Add clock driver for S3C64xx SoCs ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare ARM: s3c64xx: Migrate clock handling to Common Clock Framework ARM: s3c64xx: Remove old clock management code .../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 +Quoted 8 lines
28 files changed, 943 insertions(+), 1205 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c64xx-clo ck. txt delete mode 100644 arch/arm/mach-s3c64xx/clock.c create mode 100644 drivers/clk/samsung/clk-s3c64xx.c create mode 100644 include/dt-bindings/clock/samsung,s3c64xx-clock.hQuoted 6 lines
Basically, this series looks good to me, but I'm not sure how this
should be handled because of dependency with PWM cleanup and clk
stuff
in clk tree now...Patches 1-3 can go into the clk tree. 4-6 should go through their
respective trees.If you want I can take 7& 8 through the clk tree.
Quoted 7 lines
Alternatively I can provide patches 1-3 in a separate stable topic
branch for you to pull in as a dependency. We'll both merge that stable
topic branch into our trees and you can make a note of it for the
arm-soc folks.Thanks for your quick response. Would be helpful to samsung tree if
you
could provide a separate stable topic branch what you suggested for
clk
stuff in this series.Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
git://git.linaro.org/people/mturquette/linux.gitclk-next-s3c64xxTopic branch contains patches 1-3 of this series on top of v3.11-rc2. I
have already merged the same into the clk-next branch.Mike, thanks. I've merged the branch 'clk-next-s3c64xx' into the samsung tree :)
Quoted 11 lines
Quoted 10 lines
Quoted 4 lines
What about the dependency on PWM cleanup series? Patches 7-8 must be merged after them, otherwise there will be a regression, because the old PWM clocksource driver will be broken and so s3c64xx won't boot until moved to new one, which is done by mentioned series.
Is this a question for me? I did not take patches 7 or 8 into clk-next.
Sounds like those patches should go through Samsung tree into arm-soc,
and perhaps be a late-applied branch to get the ordering right.
Quoted 6 lines
Quoted 4 lines
It's just continuation of the topic. I guess the question is mostly for
Kukjin. Anyway, your suggestion is most likely the right thing, thanks.Tomasz, I can handle. Thanks.
Good. You're welcome.
Best regards,
Tomasz
v2 cover Common Clock Framework support for Samsung S3C64xx
In reply to Mike TurquetteHi Mike,
Quoted 82 lines · On Monday 05 of August 2013 11:06:25 Mike Turquette wrote:
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 80 lines · Tomasz Figa
Quoted 78 lines
This series is an attempt to move clock support on Samsung S3C64xx SoCs
to Common Clock Framework.First, support for PLL types present on S3C64xx SoCs is added to Samsung
Common Clock Framework driver. Then the main clock driver for mentioned
SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.> >
Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txtdelete mode 100644arch/arm/mach-s3c64xx/clock.ccreate mode 100644drivers/clk/samsung/clk-s3c64xx.ccreate mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.h
Quoted 6 lines
Quoted 3 lines
Basically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff in clk tree now...
Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
It looks like version 2 of patch 2/8 has been applied by mistake, breaking compilation (and operation) of the clock driver added in patch 3/8.
Could you please fix this up? Thanks in advance.
Best regards,
Tomasz
Quoted 10 lines
If you want I can take 7 & 8 through the clk tree.
Alternatively I can provide patches 1-3 in a separate stable topic branch for you to pull in as a dependency. We'll both merge that stable topic branch into our trees and you can make a note of it for the arm-soc folks.
Regards,
Mike
Quoted 6 lines
Quoted 1 line
- Kukjin
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v2 cover Common Clock Framework support for Samsung S3C64xx
Quoting Tomasz Figa (2013-08-16 03:44:44)
Quoted 89 lines
Hi Mike,
Quoted 86 lines · On Monday 05 of August 2013 11:06:25 Mike Turquette wrote:
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 83 lines · Tomasz Figa
Quoted 72 lines
This series is an attempt to move clock support on Samsung S3C64xx SoCs
to Common Clock Framework.First, support for PLL types present on S3C64xx SoCs is added to Samsung
Common Clock Framework driver. Then the main clock driver for mentioned
SoCs is introduced. Further patches contain fixes for drivers to make them compliant with CCF semantics, migration of platform code to use the new clock driver and removal of old clock management code.Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external clocks.> >
Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007 -------------------- arch/arm/mach-s3c64xx/common.c | 21 +- arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)Quoted 6 lines
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txtdelete mode 100644arch/arm/mach-s3c64xx/clock.ccreate mode 100644drivers/clk/samsung/clk-s3c64xx.ccreate mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.hBasically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff in clk tree now...
Quoted 6 lines
Quoted 2 lines
Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
It looks like version 2 of patch 2/8 has been applied by mistake, breaking compilation (and operation) of the clock driver added in patch 3/8.
Ugh. My mistake.
Quoted 1 line
Could you please fix this up? Thanks in advance.
This is a little tricky since I published the clk-next-s3c64xx branch as a stable branch for Samsung which I think has been merged to the Samsung tree already. So what are the options?
One option is to create a fixup patch that just manages the delta between V2 and V3. I can then add this to the top of clk-next-s3c64xx and re-merge it into clk-next. Then the Samsung tree will need to re-merge that dependency branch.
Do you have a better idea?
Regards,
Mike
Quoted 20 lines
Best regards,
TomaszQuoted 16 lines
If you want I can take 7 & 8 through the clk tree.
Alternatively I can provide patches 1-3 in a separate stable topic branch for you to pull in as a dependency. We'll both merge that stable topic branch into our trees and you can make a note of it for the arm-soc folks.
Regards,
MikeQuoted 1 line
- Kukjin
--
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v2 cover Common Clock Framework support for Samsung S3C64xx
Quoted 103 lines · On Friday 16 of August 2013 14:02:03 Mike Turquette wrote:
Quoting Tomasz Figa (2013-08-16 03:44:44)
Quoted 101 lines
Hi Mike,
Quoted 98 lines · On Monday 05 of August 2013 11:06:25 Mike Turquette wrote:
Quoting Kukjin Kim (2013-08-05 10:01:36)
Quoted 95 lines · Tomasz Figa
Quoted 82 lines
This series is an attempt to move clock support on Samsung S3C64xx
SoCs
to Common Clock Framework.First, support for PLL types present on S3C64xx SoCs is added to Samsung
Common Clock Framework driver. Then the main clock driver for mentioned
SoCs is introduced. Further patches contain fixes for drivers to make
them compliant with CCF semantics, migration of platform code to use
the new clock driver and removal of old clock management code.Depends on:
- [PATCH v4 00/20] Samsung PWM support cleanuphttp://thread.gmane.org/gmane.linux.kernel.samsung-soc/20856On S3C6410-based Tiny6410 board (Mini6410-compatible):
Tested-by Tomasz Figa<[email protected]>For v1:
Acked-by Mike Turquette<[email protected]>Changes since v1:
- added patch for read-only muxes,
- exported configurable muxes and dividers,
- definedmout_syncmuxas read-only mux,
- in DT-enabled case fixed-clock binding is used to define external
clocks.> >Tomasz Figa (8):
clk: mux: Add support for read-only muxes.
clk: samsung: pll: Add support for PLL6552 and PLL6553
clk: samsung: Add clock driver for S3C64xx SoCs
ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare
usb: host: ohci-s3c2410 Use clk_prepare_enable/clk_disable_unprepare
ARM: s3c64xx: Migrate clock handling to Common Clock Framework
ARM: s3c64xx: Remove old clock management code.../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++ arch/arm/Kconfig | 2 +- arch/arm/mach-s3c64xx/Makefile | 2 +- arch/arm/mach-s3c64xx/clock.c | 1007--------------------
arch/arm/mach-s3c64xx/common.c| 21 +-arch/arm/mach-s3c64xx/common.h | 12 +- arch/arm/mach-s3c64xx/dma.c | 4 +- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 132 +-- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/mach-s3c64xx/pm.c | 21 - arch/arm/mach-s3c64xx/s3c6400.c | 6 - arch/arm/mach-s3c64xx/s3c6410.c | 7 - arch/arm/plat-samsung/include/plat/cpu.h | 4 + drivers/clk/clk-mux.c | 10 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-pll.c | 160 ++++ drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk-s3c64xx.c | 465 +++++++++ drivers/usb/host/ohci-s3c2410.c | 8 +- include/dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ++++ include/linux/clk-provider.h | 2 + 28 files changed, 943 insertions(+), 1205 deletions(-)Quoted 7 lines
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock. txt
delete mode 100644arch/arm/mach-s3c64xx/clock.ccreate mode 100644drivers/clk/samsung/clk-s3c64xx.ccreate mode 100644include/dt-bindings/clock/samsung,s3c64xx-clock.hBasically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff
in clk tree now...
Quoted 7 lines
Quoted 6 lines
Quoted 2 lines
Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
It looks like version 2 of patch 2/8 has been applied by mistake, breaking compilation (and operation) of the clock driver added in patch 3/8.
Ugh. My mistake.
Happens. Thanks for fast response.
Quoted 5 lines
Quoted 1 line
Could you please fix this up? Thanks in advance.
This is a little tricky since I published the clk-next-s3c64xx branch as a stable branch for Samsung which I think has been merged to the Samsung tree already.
Right, this somewhat limits our options. Although I'm not really sure whether Kukjin already has pushed it to his public tree.
Quoted 6 lines
So what are the options?
One option is to create a fixup patch that just manages the delta between V2 and V3. I can then add this to the top of clk-next-s3c64xx and re-merge it into clk-next. Then the Samsung tree will need to re-merge that dependency branch.
Well, I can make a "convert PLL65xx to new registration method" patch, that would be basically the delta. If this could be merged before patch 7/8, no regression would be introduced.
Quoted 1 line
Do you have a better idea?
Not really. Maybe let's ask Kukjin whether he has already merged it to his tree. Kukjin, have you?
Best regards,
Tomasz
v2 cover Common Clock Framework support for Samsung S3C64xx
Tomasz Figa wrote:
[...]
Quoted 9 lines
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Basically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff
in clk tree now...Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
Quoted 7 lines
Quoted 4 lines
Quoted 3 lines
It looks like version 2 of patch 2/8 has been applied by mistake, breaking compilation (and operation) of the clock driver added in patch 3/8.
Ugh. My mistake.
Happens. Thanks for fast response.
Sorry for late ;-)
Quoted 9 lines
Quoted 5 lines
Quoted 1 line
Could you please fix this up? Thanks in advance.
This is a little tricky since I published the clk-next-s3c64xx branch as a stable branch for Samsung which I think has been merged to the Samsung tree already.
Right, this somewhat limits our options. Although I'm not really sure whether Kukjin already has pushed it to his public tree.
Yeah, I already did sort out in my local but not public tree because of some problem.
Quoted 7 lines
Quoted 6 lines
So what are the options?
One option is to create a fixup patch that just manages the delta between V2 and V3. I can then add this to the top of clk-next-s3c64xx and re-merge it into clk-next. Then the Samsung tree will need to re-merge that dependency branch.
Quoted 9 lines
Well, I can make a "convert PLL65xx to new registration method" patch, that would be basically the delta. If this could be merged before patch 7/8, no regression would be introduced.
Quoted 1 line
Do you have a better idea?
Not really. Maybe let's ask Kukjin whether he has already merged it to his tree. Kukjin, have you?
OK, if new branch is ready, I will replace with that or if re-merge is required, I will. Either way, I'm fine and can handle. Mike, let me know your choice :-)
Thanks,
Kukjin
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoting Kukjin Kim (2013-08-17 03:30:11)
Quoted 45 lines
Tomasz Figa wrote:
[...]
Quoted 9 lines
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Quoted 9 lines
Quoted 8 lines
Quoted 5 lines
Basically, this series looks good to me, but I'm not sure how this should be handled because of dependency with PWM cleanup and clk stuff
in clk tree now...Patches 1-3 can go into the clk tree. 4-6 should go through their respective trees.
Quoted 7 lines
Quoted 4 lines
Quoted 3 lines
It looks like version 2 of patch 2/8 has been applied by mistake, breaking compilation (and operation) of the clock driver added in patch 3/8.
Ugh. My mistake.
Happens. Thanks for fast response.
Sorry for late ;-)
Quoted 9 lines
Quoted 5 lines
Quoted 1 line
Could you please fix this up? Thanks in advance.
This is a little tricky since I published the clk-next-s3c64xx branch as a stable branch for Samsung which I think has been merged to the Samsung tree already.
Right, this somewhat limits our options. Although I'm not really sure whether Kukjin already has pushed it to his public tree.
Yeah, I already did sort out in my local but not public tree because of some problem.
Quoted 11 lines
Quoted 6 lines
So what are the options?
One option is to create a fixup patch that just manages the delta between V2 and V3. I can then add this to the top of clk-next-s3c64xx and re-merge it into clk-next. Then the Samsung tree will need to re-merge that dependency branch.
Well, I can make a "convert PLL65xx to new registration method" patch, that would be basically the delta. If this could be merged before patch 7/8, no regression would be introduced.
Quoted 8 lines
Quoted 5 lines
Quoted 1 line
Do you have a better idea?
Not really. Maybe let's ask Kukjin whether he has already merged it to his tree. Kukjin, have you?
OK, if new branch is ready, I will replace with that or if re-merge is required, I will. Either way, I'm fine and can handle. Mike, let me know your choice :-)
Since I have already published it let's just go with the delta patch. I can create another stable branch named clk-next-s3c64xx-delta that just has this patch on top of clk-next-s3c64xx OR I can apply it on top of the existing clk-next-s3c64xx and re-merge it.
I'm trying to think on whether there are any weird git corner cases with re-merging clk-next-s3c64xx. Let me know if re-merging is somehow unsafe (makes history weird, or whatever).
Let me know what option is better for you. I'll publish as soon as I get the delta patch. Apologies again for creating some extra work!
Thanks,
Mike
Quoted 3 lines
Thanks,
Kukjin
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoted 1 line · Mike Turquette
[...]
Quoted 9 lines
Quoted 3 lines
OK, if new branch is ready, I will replace with that or if re-merge is required, I will. Either way, I'm fine and can handle. Mike, let me know your choice :-)
Since I have already published it let's just go with the delta patch. I can create another stable branch named clk-next-s3c64xx-delta that just has this patch on top of clk-next-s3c64xx OR I can apply it on top of the existing clk-next-s3c64xx and re-merge it.
Sounds good to me. If the branch for the delta is ready, let me know.
Quoted 4 lines
I'm trying to think on whether there are any weird git corner cases with re-merging clk-next-s3c64xx. Let me know if re-merging is somehow unsafe (makes history weird, or whatever).
I don't think it causes some problem.
Quoted 3 lines
Let me know what option is better for you. I'll publish as soon as I get the delta patch. Apologies again for creating some extra work!
No problem.
Thanks,
Kukjin
v2 cover Common Clock Framework support for Samsung S3C64xx
Quoted 9 lines · Kukjin Kim
Quoted 1 line · Mike Turquette
[...]
Quoted 4 lines
Quoted 3 lines
OK, if new branch is ready, I will replace with that or if re-merge is required, I will. Either way, I'm fine and can handle. Mike, let me know your choice :-)
Quoted 7 lines
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Since I have already published it let's just go with the delta patch. I can create another stable branch named clk-next-s3c64xx-delta that just has this patch on top of clk-next-s3c64xx OR I can apply it on top of the existing clk-next-s3c64xx and re-merge it.
Sounds good to me. If the branch for the delta is ready, let me know.
Mike, I'm waiting for your delta branch which includes following from Tomasz.
[PATCH] clk: samsung: pll: Use new registration method for PLL6552 and PLL6553
I couldn't send some branches to arm-soc for upcoming merge window yet because of build compilation breakage of common-clk-s3c64xx branch which has many dependencies...
- Kukjin
Quoted 10 lines
Quoted 4 lines
I'm trying to think on whether there are any weird git corner cases with re-merging clk-next-s3c64xx. Let me know if re-merging is somehow unsafe (makes history weird, or whatever).
I don't think it causes some problem.
Quoted 3 lines
Let me know what option is better for you. I'll publish as soon as I get the delta patch. Apologies again for creating some extra work!
No problem.
PATCH 1/1 clk: samsung: pll: Use new registration method for PLL6552 and PLL6553
In reply to Mike TurquetteThis patch modifies PLL6552 and PLL6553 clock drivers to use recently added common Samsung PLL registration method.
--- drivers/clk/samsung/clk-pll.c | 105 +++++------------------------------------- drivers/clk/samsung/clk-pll.h | 6 +-- 2 files changed, 13 insertions(+), 98 deletions(-)
drivers/clk/samsung/clk-pll.c +11 -94
@@ -441,9 +441,6 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name,* PLL6552 Clock Type */ -#define PLL6552_LOCK_REG 0x00 -#define PLL6552_CON_REG 0x0c -#define PLL6552_MDIV_MASK 0x3ff#define PLL6552_PDIV_MASK 0x3f#define PLL6552_SDIV_MASK 0x7
@@ -451,21 +448,14 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name,#define PLL6552_PDIV_SHIFT 8#define PLL6552_SDIV_SHIFT 0 -struct samsung_clk_pll6552 { -struct clk_hw hw; -void __iomem *reg_base; -}; - -#define to_clk_pll6552 (_hw) container_of(_hw, struct samsung_clk_pll6552, hw) -static unsigned long samsung_pll6552_recalc_rate (struct clk_hw *hw,unsigned long parent_rate) { -struct samsung_clk_pll6552 *pll =to_clk_pll6552 (hw); +struct samsung_clk_pll *pll =to_clk_pll (hw);u32 mdiv, pdiv, sdiv, pll_con;u64 fvco = parent_rate; - pll_con =__raw_readl (pll->reg_base +PLL6552_CON_REG ); + pll_con =__raw_readl (pll->con_reg); mdiv = (pll_con >>PLL6552_MDIV_SHIFT ) &PLL6552_MDIV_MASK ; pdiv = (pll_con >>PLL6552_PDIV_SHIFT ) &PLL6552_PDIV_MASK ; sdiv = (pll_con >>PLL6552_SDIV_SHIFT ) &PLL6552_SDIV_MASK ;
@@ -480,48 +470,10 @@ static const struct clk_ops samsung_pll6552_clk_ops = { .recalc_rate = samsung_pll6552_recalc_rate, }; -struct clk *__init samsung_clk_register_pll6552 (const char *name, -const char *pname,void __iomem *base) -{ -struct samsung_clk_pll6552 *pll; -struct clk *clk; -struct clk_init_data init; - - pll =kzalloc (sizeof (*pll),GFP_KERNEL ); -if (!pll) { -pr_err ("%s: could not allocate pll clk %s\n" , __func__, name); -return NULL ; - } - - init.name = name; - init.ops = &samsung_pll6552_clk_ops; - init.parent_names = &pname; - init.num_parents =1 ; - - pll->hw.init = &init; - pll->reg_base = base; - - clk =clk_register (NULL , &pll->hw); -if (IS_ERR (clk)) { -pr_err ("%s: failed to register pll clock %s\n" , __func__, - name); -kfree (pll); - } - -if (clk_register_clkdev (clk, name,NULL )) -pr_err ("%s: failed to register lookup for %s" , __func__, name); - -return clk; -} -/* * PLL6553 Clock Type */ -#define PLL6553_LOCK_REG 0x00 -#define PLL6553_CON0_REG 0x0c -#define PLL6553_CON1_REG 0x10 -#define PLL6553_MDIV_MASK 0xff#define PLL6553_PDIV_MASK 0x3f#define PLL6553_SDIV_MASK 0x7
@@ -531,22 +483,15 @@ struct clk * __init samsung_clk_register_pll6552(const char *name,#define PLL6553_SDIV_SHIFT 0#define PLL6553_KDIV_SHIFT 0 -struct samsung_clk_pll6553 { -struct clk_hw hw; -void __iomem *reg_base; -}; - -#define to_clk_pll6553 (_hw) container_of(_hw, struct samsung_clk_pll6553, hw) -static unsigned long samsung_pll6553_recalc_rate (struct clk_hw *hw,unsigned long parent_rate) { -struct samsung_clk_pll6553 *pll =to_clk_pll6553 (hw); +struct samsung_clk_pll *pll =to_clk_pll (hw);u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;u64 fvco = parent_rate; - pll_con0 =__raw_readl (pll->reg_base +PLL6553_CON0_REG ); - pll_con1 =__raw_readl (pll->reg_base +PLL6553_CON1_REG ); + pll_con0 =__raw_readl (pll->con_reg); + pll_con1 =__raw_readl (pll->con_reg +0x4 ); mdiv = (pll_con0 >>PLL6553_MDIV_SHIFT ) &PLL6553_MDIV_MASK ; pdiv = (pll_con0 >>PLL6553_PDIV_SHIFT ) &PLL6553_PDIV_MASK ; sdiv = (pll_con0 >>PLL6553_SDIV_SHIFT ) &PLL6553_SDIV_MASK ;
@@ -563,40 +508,6 @@ static const struct clk_ops samsung_pll6553_clk_ops = { .recalc_rate = samsung_pll6553_recalc_rate, }; -struct clk *__init samsung_clk_register_pll6553 (const char *name, -const char *pname,void __iomem *base) -{ -struct samsung_clk_pll6553 *pll; -struct clk *clk; -struct clk_init_data init; - - pll =kzalloc (sizeof (*pll),GFP_KERNEL ); -if (!pll) { -pr_err ("%s: could not allocate pll clk %s\n" , __func__, name); -return NULL ; - } - - init.name = name; - init.ops = &samsung_pll6553_clk_ops; - init.parent_names = &pname; - init.num_parents =1 ; - - pll->hw.init = &init; - pll->reg_base = base; - - clk =clk_register (NULL , &pll->hw); -if (IS_ERR (clk)) { -pr_err ("%s: failed to register pll clock %s\n" , __func__, - name); -kfree (pll); - } - -if (clk_register_clkdev (clk, name,NULL )) -pr_err ("%s: failed to register lookup for %s" , __func__, name); - -return clk; -} -/* * PLL2550x Clock Type */
@@ -732,6 +643,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,else init.ops = &samsung_pll36xx_clk_ops;break ; +case pll_6552: + init.ops = &samsung_pll6552_clk_ops; +break ; +case pll_6553: + init.ops = &samsung_pll6553_clk_ops; +break ;default :pr_warn ("%s: Unknown pll type for pll clk %s\n" , __func__, pll_clk->name);
drivers/clk/samsung/clk-pll.h +2 -4
@@ -17,6 +17,8 @@ enum samsung_pll_type { pll_36xx, pll_2550, pll_2650, + pll_6552, + pll_6553, };#define PLL_35XX_RATE (_rate, _m, _p, _s) \
@@ -64,10 +66,6 @@ extern struct clk * __init samsung_clk_register_pll45xx(const char *name,extern struct clk *__init samsung_clk_register_pll46xx (const char *name,const char *pname,const void __iomem *con_reg,enum pll46xx_type type); -extern struct clk *samsung_clk_register_pll6552 (const char *name, -const char *pname,void __iomem *base); -extern struct clk *samsung_clk_register_pll6553 (const char *name, -const char *pname,void __iomem *base);extern struct clk *__init samsung_clk_register_pll2550x (const char *name,const char *pname,const void __iomem *reg_base,const unsigned long offset);
Signature · 1 line
1.8.3.2
PATCH 1/1 clk: samsung: pll: Use new registration method for PLL6552 and PLL6553
Quoting Tomasz Figa (2013-08-20 17:33:21)
Quoted 4 lines
This patch modifies PLL6552 and PLL6553 clock drivers to use recently added common Samsung PLL registration method.
Signed-off-by Tomasz Figa <[email protected]>
Sigh. This change won't apply on top of clk-next-s3c64xx since it requires Yadwinder's change (amongst) others.
The best I could do was spin out another topic branch with the relevant changes and apply this patch on top. It is a subset of clk-next but it is almost entirely Samsung patches:
git://git.linaro.org/people/mturquette/linux.git clk-next-s3c64xx-delta
Kukjin & Tomasz, let me know if this OK for you to add as a dependency to the Samsung tree. If it is I will merge it into clk-next, but I want your OK that this branch is OK for you to take.
Regards,
Mike
Quoted 198 lines
--- drivers/clk/samsung/clk-pll.c | 105 +++++------------------------------------- drivers/clk/samsung/clk-pll.h | 6 +-- 2 files changed, 13 insertions(+), 98 deletions(-)drivers/clk/samsung/clk-pll.c +11
-94@@ -441,9 +441,6 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name,* PLL6552 Clock Type */ -#define PLL6552_LOCK_REG 0x00 -#define PLL6552_CON_REG 0x0c -#define PLL6552_MDIV_MASK 0x3ff#define PLL6552_PDIV_MASK 0x3f#define PLL6552_SDIV_MASK 0x7@@ -451,21 +448,14 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name,#define PLL6552_PDIV_SHIFT 8#define PLL6552_SDIV_SHIFT 0 -struct samsung_clk_pll6552 { -struct clk_hw hw; -void __iomem *reg_base; -}; - -#define to_clk_pll6552 (_hw) container_of(_hw, struct samsung_clk_pll6552, hw) -static unsigned long samsung_pll6552_recalc_rate (struct clk_hw *hw,unsigned long parent_rate) { -struct samsung_clk_pll6552 *pll =to_clk_pll6552 (hw); +struct samsung_clk_pll *pll =to_clk_pll (hw);u32 mdiv, pdiv, sdiv, pll_con;u64 fvco = parent_rate; - pll_con =__raw_readl (pll->reg_base +PLL6552_CON_REG ); + pll_con =__raw_readl (pll->con_reg); mdiv = (pll_con >>PLL6552_MDIV_SHIFT ) &PLL6552_MDIV_MASK ; pdiv = (pll_con >>PLL6552_PDIV_SHIFT ) &PLL6552_PDIV_MASK ; sdiv = (pll_con >>PLL6552_SDIV_SHIFT ) &PLL6552_SDIV_MASK ;@@ -480,48 +470,10 @@ static const struct clk_ops samsung_pll6552_clk_ops = { .recalc_rate = samsung_pll6552_recalc_rate, }; -struct clk *__init samsung_clk_register_pll6552 (const char *name, -const char *pname,void __iomem *base) -{ -struct samsung_clk_pll6552 *pll; -struct clk *clk; -struct clk_init_data init; - - pll =kzalloc (sizeof (*pll),GFP_KERNEL ); -if (!pll) { -pr_err ("%s: could not allocate pll clk %s\n" , __func__, name); -return NULL ; - } - - init.name = name; - init.ops = &samsung_pll6552_clk_ops; - init.parent_names = &pname; - init.num_parents =1 ; - - pll->hw.init = &init; - pll->reg_base = base; - - clk =clk_register (NULL , &pll->hw); -if (IS_ERR (clk)) { -pr_err ("%s: failed to register pll clock %s\n" , __func__, - name); -kfree (pll); - } - -if (clk_register_clkdev (clk, name,NULL )) -pr_err ("%s: failed to register lookup for %s" , __func__, name); - -return clk; -} -/* * PLL6553 Clock Type */ -#define PLL6553_LOCK_REG 0x00 -#define PLL6553_CON0_REG 0x0c -#define PLL6553_CON1_REG 0x10 -#define PLL6553_MDIV_MASK 0xff#define PLL6553_PDIV_MASK 0x3f#define PLL6553_SDIV_MASK 0x7@@ -531,22 +483,15 @@ struct clk * __init samsung_clk_register_pll6552(const char *name,#define PLL6553_SDIV_SHIFT 0#define PLL6553_KDIV_SHIFT 0 -struct samsung_clk_pll6553 { -struct clk_hw hw; -void __iomem *reg_base; -}; - -#define to_clk_pll6553 (_hw) container_of(_hw, struct samsung_clk_pll6553, hw) -static unsigned long samsung_pll6553_recalc_rate (struct clk_hw *hw,unsigned long parent_rate) { -struct samsung_clk_pll6553 *pll =to_clk_pll6553 (hw); +struct samsung_clk_pll *pll =to_clk_pll (hw);u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;u64 fvco = parent_rate; - pll_con0 =__raw_readl (pll->reg_base +PLL6553_CON0_REG ); - pll_con1 =__raw_readl (pll->reg_base +PLL6553_CON1_REG ); + pll_con0 =__raw_readl (pll->con_reg); + pll_con1 =__raw_readl (pll->con_reg +0x4 ); mdiv = (pll_con0 >>PLL6553_MDIV_SHIFT ) &PLL6553_MDIV_MASK ; pdiv = (pll_con0 >>PLL6553_PDIV_SHIFT ) &PLL6553_PDIV_MASK ; sdiv = (pll_con0 >>PLL6553_SDIV_SHIFT ) &PLL6553_SDIV_MASK ;@@ -563,40 +508,6 @@ static const struct clk_ops samsung_pll6553_clk_ops = { .recalc_rate = samsung_pll6553_recalc_rate, }; -struct clk *__init samsung_clk_register_pll6553 (const char *name, -const char *pname,void __iomem *base) -{ -struct samsung_clk_pll6553 *pll; -struct clk *clk; -struct clk_init_data init; - - pll =kzalloc (sizeof (*pll),GFP_KERNEL ); -if (!pll) { -pr_err ("%s: could not allocate pll clk %s\n" , __func__, name); -return NULL ; - } - - init.name = name; - init.ops = &samsung_pll6553_clk_ops; - init.parent_names = &pname; - init.num_parents =1 ; - - pll->hw.init = &init; - pll->reg_base = base; - - clk =clk_register (NULL , &pll->hw); -if (IS_ERR (clk)) { -pr_err ("%s: failed to register pll clock %s\n" , __func__, - name); -kfree (pll); - } - -if (clk_register_clkdev (clk, name,NULL )) -pr_err ("%s: failed to register lookup for %s" , __func__, name); - -return clk; -} -/* * PLL2550x Clock Type */ @@ -732,6 +643,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,else init.ops = &samsung_pll36xx_clk_ops;break ; +case pll_6552: + init.ops = &samsung_pll6552_clk_ops; +break ; +case pll_6553: + init.ops = &samsung_pll6553_clk_ops; +break ;default :pr_warn ("%s: Unknown pll type for pll clk %s\n" , __func__, pll_clk->name);drivers/clk/samsung/clk-pll.h +2
-4@@ -17,6 +17,8 @@ enum samsung_pll_type { pll_36xx, pll_2550, pll_2650, + pll_6552, + pll_6553, };#define PLL_35XX_RATE (_rate, _m, _p, _s) \@@ -64,10 +66,6 @@ extern struct clk * __init samsung_clk_register_pll45xx(const char *name,extern struct clk *__init samsung_clk_register_pll46xx (const char *name,const char *pname,const void __iomem *con_reg,enum pll46xx_type type); -extern struct clk *samsung_clk_register_pll6552 (const char *name, -const char *pname,void __iomem *base); -extern struct clk *samsung_clk_register_pll6553 (const char *name, -const char *pname,void __iomem *base);extern struct clk *__init samsung_clk_register_pll2550x (const char *name,const char *pname,const void __iomem *reg_base,const unsigned long offset);Signature · 1 line
1.8.3.2
PATCH 1/1 clk: samsung: pll: Use new registration method for PLL6552 and PLL6553
Quoted 13 lines · Mike Turquette
Quoting Tomasz Figa (2013-08-20 17:33:21)
Quoted 4 lines
This patch modifies PLL6552 and PLL6553 clock drivers to use recently added common Samsung PLL registration method.
Signed-off-by Tomasz Figa<[email protected]>Sigh. This change won't apply on top of clk-next-s3c64xx since it requires Yadwinder's change (amongst) others.
The best I could do was spin out another topic branch with the relevant changes and apply this patch on top. It is a subset of clk-next but it is almost entirely Samsung patches:
Quoted 6 lines
git://git.linaro.org/people/mturquette/linux.gitclk-next-s3c64xx-deltaKukjin& Tomasz, let me know if this OK for you to add as a dependency to the Samsung tree. If it is I will merge it into clk-next, but I want your OK that this branch is OK for you to take.
Hi Mike,
I merged the branch clk-next-s3c64xx-delta you provided on top of previous clk-next-s3c64xx for common-clk-s3c64xx and dt-s3c64xx and it looks fine to me.
Thanks,
Kukjin
PATCH 1/1 clk: samsung: pll: Use new registration method for PLL6552 and PLL6553
Quoting Kukjin Kim (2013-08-27 10:16:14)
Quoted 20 lines · Mike Turquette
Quoted 13 lines
Quoting Tomasz Figa (2013-08-20 17:33:21)
Quoted 4 lines
This patch modifies PLL6552 and PLL6553 clock drivers to use recently added common Samsung PLL registration method.
Signed-off-by Tomasz Figa<[email protected]>Sigh. This change won't apply on top of clk-next-s3c64xx since it requires Yadwinder's change (amongst) others.
The best I could do was spin out another topic branch with the relevant changes and apply this patch on top. It is a subset of clk-next but it is almost entirely Samsung patches:
Quoted 6 lines
git://git.linaro.org/people/mturquette/linux.gitclk-next-s3c64xx-deltaKukjin& Tomasz, let me know if this OK for you to add as a dependency to the Samsung tree. If it is I will merge it into clk-next, but I want your OK that this branch is OK for you to take.
Quoted 5 lines
Hi Mike,
I merged the branch clk-next-s3c64xx-delta you provided on top of previous clk-next-s3c64xx for common-clk-s3c64xx and dt-s3c64xx and it looks fine to me.
Cool. I've merged it into clk-next as well.
Regards,
Mike
Quoted 3 lines
Thanks,
Kukjin