Skip to contentSkip to conversation

mx6: Factor out common HDMI setup code

PATCH New Pardeep Kumar Singla 3 participants 6 messages Jul 25, 2013 – Jul 27, 2013

Subsystems (2)
Arm (32-bit) Arm i.MX and Layerscape
lore
Share & tools
lore

Pardeep Kumar Singla

author
#0 lore raw

PATCH v4 1/2 mx6: Factor out common HDMI setup code

Instead of duplicating HDMI setup code for every mx6 board, factor out the common code

Signed-off-by Pardeep Kumar Singla <[email protected]>

---
Changes since v3:
Added declaration of enable_ipu_clock().
Made enable_ipu_clock() function public.

 arch/arm/cpu/armv7/mx6/clock.c                |    8 +++++
 arch/arm/cpu/armv7/mx6/soc.c                  |   43 +++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/clock.h         |    2 +-
 arch/arm/include/asm/arch-mx6/mxc_hdmi.h      |    5 +++
 board/boundary/nitrogen6x/nitrogen6x.c        |   44 ++++-------------------
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   46 +++++--------------------
 board/wandboard/wandboard.c                   |   44 +++--------------------
 include/configs/mx6qsabrelite.h               |    1 +
 include/configs/nitrogen6x.h                  |    1 +
 include/configs/wandboard.h                   |    1 +
 10 files changed, 79 insertions(+), 116 deletions(-)
arch/arm/cpu/armv7/mx6/clock.c +8 -0
index 3c0d908..a724e66 100644
@@ -468,6 +468,14 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+void enable_ipu_clock()
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+	writel(reg, &mxc_ccm->CCGR3);
+}
 /***************************************************/
 
 U_BOOT_CMD(
arch/arm/cpu/armv7/mx6/soc.c +43 -0

52 lines not on this page · raw message

arch/arm/include/asm/arch-mx6/clock.h +1 -1
index cfd4edc..d9f7fc5 100644
@@ -65,5 +65,5 @@ void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
 int enable_sata_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
-
+void enable_ipu_clock();
 #endif /* __ASM_ARCH_CLOCK_H */
arch/arm/include/asm/arch-mx6/mxc_hdmi.h +5 -0
index 9dccb3f..5cd6aa6 100644
@@ -21,6 +21,11 @@
 #ifndef __MXC_HDMI_H__
 #define __MXC_HDMI_H__
 
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void);
+void imx_setup_hdmi(void);
+#endif
+
 /*
  * Hdmi controller registers
  */
board/boundary/nitrogen6x/nitrogen6x.c +7 -37

76 lines not on this page · raw message

board/freescale/mx6qsabrelite/mx6qsabrelite.c +8 -38

79 lines not on this page · raw message

board/wandboard/wandboard.c +4 -40

67 lines not on this page · raw message

include/configs/mx6qsabrelite.h +1 -0
index c7db81d..6127347 100644
@@ -141,6 +141,7 @@
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
include/configs/nitrogen6x.h +1 -0
index 74df66c..0b665dc 100644
@@ -154,6 +154,7 @@
 #define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_CMD_HDMIDETECT
 #define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
include/configs/wandboard.h +1 -0
index dd06bd7..1f83e89 100644
@@ -100,6 +100,7 @@
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
 
 #if defined(CONFIG_MX6DL)
 #define CONFIG_DEFAULT_FDT_FILE		"imx6dl-wandboard.dtb"
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH v4 2/2 mx6qsabresd: Add splash screen support via HDMI

Signed-off-by Pardeep Kumar Singla <[email protected]>

---
Changes since v3:
Added enable_ipu_clock() function for ipu clock setting

 board/freescale/mx6sabresd/mx6sabresd.c |   64 ++++++++++++++++++++++++++++++-
 include/configs/mx6sabre_common.h       |    3 +-
 include/configs/mx6sabresd.h            |   19 +++++++++
 3 files changed, 84 insertions(+), 2 deletions(-)
board/freescale/mx6sabresd/mx6sabresd.c +63 -1
index 222ee98..4694b5c 100644
@@ -29,7 +29,12 @@
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
-
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\

@@ -239,6 +244,60 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
+#if defined(CONFIG_VIDEO_IPUV3)
+static struct fb_videomode const hdmi = {
+	.name           = "HDMI",
+	.refresh        = 60,
+	.xres           = 1024,
+	.yres           = 768,
+	.pixclock       = 15385,
+	.left_margin    = 220,
+	.right_margin   = 40,
+	.upper_margin   = 21,
+	.lower_margin   = 7,
+	.hsync_len      = 60,
+	.vsync_len      = 10,
+	.sync           = FB_SYNC_EXT,
+	.vmode          = FB_VMODE_NONINTERLACED
+};
+
+int board_video_skip(void)
+{
+	int ret;
+
+	ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
+
+	if (ret)
+		printf("HDMI cannot be configured: %d\n", ret);
+
+	imx_enable_hdmi_phy();
+	return ret;
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	int ret;

@@ -255,6 +314,9 @@ int board_eth_init(bd_t *bis)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
 
 	return 0;
 }
include/configs/mx6sabre_common.h +2 -1
index 53cc559..dd93fff 100644
@@ -20,6 +20,7 @@
 #define CONFIG_MX6
 
 #include "mx6_common.h"
+#include <asm/sizes.h>
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

@@ -32,7 +33,7 @@
 #define CONFIG_REVISION_TAG
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
include/configs/mx6sabresd.h +19 -0
index 76675f4..5637c19 100644
@@ -17,6 +17,9 @@
 #ifndef __MX6QSABRESD_CONFIG_H
 #define __MX6QSABRESD_CONFIG_H
 
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
 #define CONFIG_MACH_TYPE	3980
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_CONSOLE_DEV		"ttymxc0"

@@ -31,4 +34,20 @@
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SDHC3 */
 #endif
 
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+
 #endif                         /* __MX6QSABRESD_CONFIG_H */
Signature · 1 line
1.7.9.5
#2 lore raw

PATCH v4 2/2 mx6qsabresd: Add splash screen support via HDMI

Quoted 2 lines · Pardeep Kumar Singla
Signed-off-by Pardeep Kumar Singla <[email protected]>

---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
#3 lore raw

PATCH v4 1/2 mx6: Factor out common HDMI setup code

In reply to Pardeep Kumar Singla
Quoted 399 lines · Pardeep Kumar Singla

Instead of duplicating HDMI setup code for every mx6 board, factor out the common code

Signed-off-by Pardeep Kumar Singla <[email protected]>

---
Changes since v3:
Added declaration of enable_ipu_clock().
Made enable_ipu_clock() function public.

  arch/arm/cpu/armv7/mx6/clock.c                |    8 +++++
  arch/arm/cpu/armv7/mx6/soc.c                  |   43 +++++++++++++++++++++++
  arch/arm/include/asm/arch-mx6/clock.h         |    2 +-
  arch/arm/include/asm/arch-mx6/mxc_hdmi.h      |    5 +++
  board/boundary/nitrogen6x/nitrogen6x.c        |   44 ++++-------------------
  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   46 +++++--------------------
  board/wandboard/wandboard.c                   |   44 +++--------------------
  include/configs/mx6qsabrelite.h               |    1 +
  include/configs/nitrogen6x.h                  |    1 +
  include/configs/wandboard.h                   |    1 +
  10 files changed, 79 insertions(+), 116 deletions(-)
arch/arm/cpu/armv7/mx6/clock.c +8 -0
index 3c0d908..a724e66 100644
@@ -468,6 +468,14 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  	return 0;
  }
 
+void enable_ipu_clock()
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+	writel(reg, &mxc_ccm->CCGR3);
+}
  /***************************************************/
 
  U_BOOT_CMD(
arch/arm/cpu/armv7/mx6/soc.c +43 -0
index fc436fb..a79369f 100644
@@ -32,6 +32,8 @@
  #include <asm/imx-common/boot_mode.h>
  #include <asm/imx-common/dma.h>
  #include <stdbool.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
 
  struct scu_regs {
  	u32	ctrl;

@@ -228,3 +230,44 @@ const struct boot_mode soc_boot_modes[] = {
  void s_init(void)
  {
  }
+
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void)
+{
+	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	u8 reg;
+	reg = readb(&hdmi->phy_conf0);
+	reg |= HDMI_PHY_CONF0_PDZ_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+void imx_setup_hdmi(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	int reg;
+
+	/* Turn on HDMI PHY clock */
+	reg = readl(&mxc_ccm->CCGR2);
+	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
+		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+	writel(reg, &mxc_ccm->CCGR2);
+	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+	reg = readl(&mxc_ccm->chsccdr);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
+		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
+		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
+		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+}
+#endif
arch/arm/include/asm/arch-mx6/clock.h +1 -1
index cfd4edc..d9f7fc5 100644
@@ -65,5 +65,5 @@ void enable_ocotp_clk(unsigned char enable);
  void enable_usboh3_clk(unsigned char enable);
  int enable_sata_clock(void);
  int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
-
+void enable_ipu_clock();
  #endif /* __ASM_ARCH_CLOCK_H */
arch/arm/include/asm/arch-mx6/mxc_hdmi.h +5 -0
index 9dccb3f..5cd6aa6 100644
@@ -21,6 +21,11 @@
  #ifndef __MXC_HDMI_H__
  #define __MXC_HDMI_H__
 
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void);
+void imx_setup_hdmi(void);
+#endif
+
  /*
   * Hdmi controller registers
   */
board/boundary/nitrogen6x/nitrogen6x.c +7 -37
index 8f0f9b8..1b82633 100644
@@ -480,22 +480,9 @@ static int detect_hdmi(struct display_info_t const *dev)
  	return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
  }
 
-static void enable_hdmi(struct display_info_t const *dev)
+static void do_enable_hdmi(struct display_info_t const *dev)
  {
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-	u8 reg;
-	printf("%s: setup HDMI monitor\n", __func__);
-	reg = readb(&hdmi->phy_conf0);
-	reg |= HDMI_PHY_CONF0_PDZ_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+	imx_enable_hdmi_phy();
  }
 
  static int detect_i2c(struct display_info_t const *dev)

@@ -528,7 +515,7 @@ static struct display_info_t const displays[] = {{
  	.addr	= 0,
  	.pixfmt	= IPU_PIX_FMT_RGB24,
  	.detect	= detect_hdmi,
-	.enable	= enable_hdmi,
+	.enable	= do_enable_hdmi,
  	.mode	= {
  		.name           = "HDMI",
  		.refresh        = 60,

@@ -653,25 +640,15 @@ static void setup_display(void)
  	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-
  	int reg;
 
+	enable_ipu_clock();
+	imx_setup_hdmi();
  	/* Turn on LDB0,IPU,IPU DI0 clocks */
  	reg = __raw_readl(&mxc_ccm->CCGR3);
-	reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
-		|MXC_CCM_CCGR3_LDB_DI0_MASK;
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
  	writel(reg, &mxc_ccm->CCGR3);
 
-	/* Turn on HDMI PHY clock */
-	reg = __raw_readl(&mxc_ccm->CCGR2);
-	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
-	       |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
-	writel(reg, &mxc_ccm->CCGR2);
-
-	/* clear HDMI PHY reset */
-	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
-
  	/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
  	writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
  	writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);

@@ -689,15 +666,8 @@ static void setup_display(void)
  	writel(reg, &mxc_ccm->cscmr2);
 
  	reg = readl(&mxc_ccm->chsccdr);
-	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
-		|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
-		|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
-	      |(CHSCCDR_PODF_DIVIDE_BY_3
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
-	      |(CHSCCDR_IPU_PRE_CLK_540M_PFD
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  	writel(reg, &mxc_ccm->chsccdr);
 
  	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
board/freescale/mx6qsabrelite/mx6qsabrelite.c +8 -38
index 862bc30..3ac4f71 100644
@@ -452,24 +452,10 @@ static int detect_hdmi(struct display_info_t const *dev)
  	return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
  }
 
-static void enable_hdmi(struct display_info_t const *dev)
+static void do_enable_hdmi(struct display_info_t const *dev)
  {
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-	u8 reg;
-	printf("%s: setup HDMI monitor\n", __func__);
-	reg = readb(&hdmi->phy_conf0);
-	reg |= HDMI_PHY_CONF0_PDZ_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+	 imx_enable_hdmi_phy();
  }
-
  static int detect_i2c(struct display_info_t const *dev)
  {
  	return ((0 == i2c_set_bus_num(dev->bus))

@@ -500,7 +486,7 @@ static struct display_info_t const displays[] = {{
  	.addr	= 0,
  	.pixfmt	= IPU_PIX_FMT_RGB24,
  	.detect	= detect_hdmi,
-	.enable	= enable_hdmi,
+	.enable	= do_enable_hdmi,
  	.mode	= {
  		.name           = "HDMI",
  		.refresh        = 60,

@@ -625,25 +611,16 @@ static void setup_display(void)
  	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-
  	int reg;
 
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
  	/* Turn on LDB0,IPU,IPU DI0 clocks */
  	reg = __raw_readl(&mxc_ccm->CCGR3);
-	reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
-		|MXC_CCM_CCGR3_LDB_DI0_MASK;
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  	writel(reg, &mxc_ccm->CCGR3);
 
-	/* Turn on HDMI PHY clock */
-	reg = __raw_readl(&mxc_ccm->CCGR2);
-	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
-	       |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
-	writel(reg, &mxc_ccm->CCGR2);
-
-	/* clear HDMI PHY reset */
-	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
-
  	/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
  	writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
  	writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);

@@ -661,15 +638,8 @@ static void setup_display(void)
  	writel(reg, &mxc_ccm->cscmr2);
 
  	reg = readl(&mxc_ccm->chsccdr);
-	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
-		|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
-		|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
-	      |(CHSCCDR_PODF_DIVIDE_BY_3
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
-	      |(CHSCCDR_IPU_PRE_CLK_540M_PFD
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  	writel(reg, &mxc_ccm->chsccdr);
 
  	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
board/wandboard/wandboard.c +4 -40
index 43c02ac..6cd28ed 100644
@@ -211,23 +211,6 @@ int board_phy_config(struct phy_device *phydev)
  }
 
  #if defined(CONFIG_VIDEO_IPUV3)
-static void enable_hdmi(void)
-{
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-	u8 reg;
-	reg = readb(&hdmi->phy_conf0);
-	reg |= HDMI_PHY_CONF0_PDZ_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
-}
-
  static struct fb_videomode const hdmi = {
  	.name           = "HDMI",
  	.refresh        = 60,

@@ -253,7 +236,7 @@ int board_video_skip(void)
  	if (ret)
  		printf("HDMI cannot be configured: %d\n", ret);
 
-	enable_hdmi();
+	imx_enable_hdmi_phy();
 
  	return ret;
  }

@@ -261,33 +244,14 @@ int board_video_skip(void)
  static void setup_display(void)
  {
  	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  	int reg;
 
-	/* Turn on IPU clock */
-	reg = readl(&mxc_ccm->CCGR3);
-	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
-	writel(reg, &mxc_ccm->CCGR3);
-
-	/* Turn on HDMI PHY clock */
-	reg = readl(&mxc_ccm->CCGR2);
-	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
-		| MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
-	writel(reg, &mxc_ccm->CCGR2);
-
-	/* clear HDMI PHY reset */
-	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+	enable_ipu_clock();
+	imx_setup_hdmi();
 
  	reg = readl(&mxc_ccm->chsccdr);
-	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
-		| MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
-		| MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
-	      | (CHSCCDR_PODF_DIVIDE_BY_3
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
-	      | (CHSCCDR_IPU_PRE_CLK_540M_PFD
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  	writel(reg, &mxc_ccm->chsccdr);
  }
  #endif /* CONFIG_VIDEO_IPUV3 */
include/configs/mx6qsabrelite.h +1 -0
index c7db81d..6127347 100644
@@ -141,6 +141,7 @@
  #define CONFIG_BMP_16BPP
  #define CONFIG_VIDEO_LOGO
  #define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
 
  /* allow to overwrite serial and ethaddr */
  #define CONFIG_ENV_OVERWRITE
include/configs/nitrogen6x.h +1 -0
index 74df66c..0b665dc 100644
@@ -154,6 +154,7 @@
  #define CONFIG_IPUV3_CLK 260000000
  #define CONFIG_CMD_HDMIDETECT
  #define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
 
  /* allow to overwrite serial and ethaddr */
  #define CONFIG_ENV_OVERWRITE
include/configs/wandboard.h +0 -0
index dd06bd7..1f83e89 100644

include/configs/wandboard.h line 106

Quoted 7 lines
include/configs/wandboard.h +1 -0
@@ -100,6 +100,7 @@
  #define CONFIG_VIDEO_LOGO
  #define CONFIG_VIDEO_BMP_LOGO
  #define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
 
  #if defined(CONFIG_MX6DL)
  #define CONFIG_DEFAULT_FDT_FILE		"imx6dl-wandboard.dtb"
Acked-by Eric Nelson <[email protected]>
#4 lore raw

PATCH v4 1/2 mx6: Factor out common HDMI setup code

In reply to Pardeep Kumar Singla

Hi Pardeep,

arch/arm/include/asm/arch-mx6/clock.h void enable_ocotp_clk(unsigned char enable); · line 68

Quoted 2 lines · Pardeep Kumar Singla
arch/arm/include/asm/arch-mx6/clock.h +1 -1
-
+void enable_ipu_clock();

This generates a warning:

warning: function declaration isn't a prototype [-Wstrict-prototypes]

I fix it myself.

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
#5 lore raw

PATCH v4 1/2 mx6: Factor out common HDMI setup code

In reply to Pardeep Kumar Singla
Quoted 4 lines · Pardeep Kumar Singla

Instead of duplicating HDMI setup code for every mx6 board, factor out the common code

Signed-off-by Pardeep Kumar Singla <[email protected]>

---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================