zynq: Add new ddrc driver for ECC support

PATCH Superseded Michal Simek 2 participants 4 messages Jul 25, 2013 – Jul 26, 2013

Subsystems (2)

Arm (32-bit) Arm/Zynq architecture

lore

Share & tools

lore

Michal Simek

author

2013-07-25 14:18 UTC #0 lore raw

PATCH 1/3 zynq: Add new ddrc driver for ECC support

The first 1MB is not initialized by first stage bootloader. Check if memory is setup to 16bit mode and ECC is enabled. If it is, clear the first 1MB.
Also u-boot should report only the half size of memory.

Signed-off-by Michal Simek <[email protected]>

Acked-by Jagannadha Sutradharudu Teki <[email protected]>

---
 arch/arm/cpu/armv7/zynq/Makefile           |  1 +
 arch/arm/cpu/armv7/zynq/ddrc.c             | 65 ++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-zynq/hardware.h  |  8 ++++
 arch/arm/include/asm/arch-zynq/sys_proto.h |  1 +
 board/xilinx/zynq/board.c                  |  2 +
 5 files changed, 77 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/zynq/ddrc.c

arch/arm/cpu/armv7/zynq/Makefile +1 -0

index 388085d..f38b3b7 100644
@@ -30,6 +30,7 @@ LIB	= $(obj)lib$(SOC).o
 
 COBJS-y	:= timer.o
 COBJS-y	+= cpu.o
+COBJS-y	+= ddrc.o
 COBJS-y	+= slcr.o
 
 COBJS	:= $(COBJS-y)

arch/arm/cpu/armv7/zynq/ddrc.c new file +65 -0

65 lines not on this page · raw message

arch/arm/include/asm/arch-zynq/hardware.h +8 -0

index 8b8a91a..b0e713d 100644
@@ -33,6 +33,7 @@
 #define ZYNQ_SDHCI_BASEADDR1		0xE0101000
 #define ZYNQ_I2C_BASEADDR0		0xE0004000
 #define ZYNQ_I2C_BASEADDR1		0xE0005000
+#define ZYNQ_DDRC_BASEADDR		0xF8006000
 
 /* Reflect slcr offsets */
 struct slcr_regs {

@@ -100,4 +101,11 @@ struct scu_regs {
 
 #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
 
+struct ddrc_regs {
+	u32 ddrc_ctrl; /* 0x0 */
+	u32 reserved[60];
+	u32 ecc_scrub; /* 0xF4 */
+};
+#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
+
 #endif /* _ASM_ARCH_HARDWARE_H */

arch/arm/include/asm/arch-zynq/sys_proto.h +1 -0

index 2317121..2698846 100644
@@ -30,6 +30,7 @@ extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
 extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
 extern u32 zynq_slcr_get_idcode(void);
+extern void zynq_ddrc_init(void);
 
 /* Driver extern functions */
 extern int zynq_sdhci_init(u32 regbase);

board/xilinx/zynq/board.c +2 -0

index b02c364..61a96b8 100644
@@ -112,5 +112,7 @@ int dram_init(void)
 {
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
+	zynq_ddrc_init();
+
 	return 0;
 }

--
1.8.2.3

-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 198 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20130725/9022a75d/attachment.pgp>

Michal Simek

author

2013-07-25 14:18 UTC #1 lore raw

PATCH 2/3 zynq: slcr: Wait 100ms till clk is properly setup

If you don't wait you will loose the first sent packet even all bits in emacps are correctly setup.

Signed-off-by Michal Simek <[email protected]>

---
 arch/arm/cpu/armv7/zynq/slcr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/cpu/armv7/zynq/slcr.c +1 -1

index 52048c6..1c28e96 100644
@@ -86,7 +86,7 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
 		/* Configure GEM_RCLK_CTRL */
 		writel(rclk, &slcr_base->gem0_rclk_ctrl);
 	}
-
+	udelay(100000);
 out:
 	zynq_slcr_lock();
 }

--
1.8.2.3

Michal Simek

author

2013-07-25 14:18 UTC #2 lore raw

PATCH 3/3 zynq: Enable axi ethernet and emaclite driver initialization

In reply to Michal Simek

Zynq can have axi ethernet and emaclite IPs in programmable logic.

Signed-off-by Michal Simek <[email protected]>

---
 board/xilinx/zynq/board.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

board/xilinx/zynq/board.c +17 -0

index 61a96b8..f9766a1 100644
@@ -77,6 +77,23 @@ int board_eth_init(bd_t *bis)
 {
 	u32 ret = 0;
 
+#ifdef CONFIG_XILINX_AXIEMAC
+	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+						XILINX_AXIDMA_BASEADDR);
+#endif
+#ifdef CONFIG_XILINX_EMACLITE
+	u32 txpp = 0;
+	u32 rxpp = 0;
+# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+	txpp = 1;
+# endif
+# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+	rxpp = 1;
+# endif
+	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+			txpp, rxpp);
+#endif
+
 #if defined(CONFIG_ZYNQ_GEM)
 # if defined(CONFIG_ZYNQ_GEM0)
 	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,

--
1.8.2.3

Michal Simek

2013-07-26 05:49 UTC #3 lore raw

PATCH 1/3 zynq: Add new ddrc driver for ECC support

In reply to Michal Simek

Quoted 46 lines · Michal Simek

Signed-off-by Michal Simek <[email protected]>

Acked-by Jagannadha Sutradharudu Teki <[email protected]>

---
 arch/arm/cpu/armv7/zynq/Makefile           |  1 +
 arch/arm/cpu/armv7/zynq/ddrc.c             | 65 ++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-zynq/hardware.h  |  8 ++++
 arch/arm/include/asm/arch-zynq/sys_proto.h |  1 +
 board/xilinx/zynq/board.c                  |  2 +
 5 files changed, 77 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/zynq/ddrc.c

arch/arm/cpu/armv7/zynq/Makefile +1 -0

index 388085d..f38b3b7 100644
@@ -30,6 +30,7 @@ LIB	= $(obj)lib$(SOC).o
 
 COBJS-y	:= timer.o
 COBJS-y	+= cpu.o
+COBJS-y	+= ddrc.o
 COBJS-y	+= slcr.o
 
 COBJS	:= $(COBJS-y)

arch/arm/cpu/armv7/zynq/ddrc.c new file +12 -0

new file mode 100644
index 0000000..e8f8c19
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2012 Michal Simek <[email protected]>
+ * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *

arch/arm/cpu/armv7/zynq/ddrc.c line 22

Quoted 10 lines

arch/arm/cpu/armv7/zynq/ddrc.c new file +10 -0

+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

Let me NACK this patch by myself.
I will add SPDX License identifier.

Thanks,
Michal

Signature · 14 lines

Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 263 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20130726/ec5dc984/attachment.pgp>