QOM'ification of pci-bridge types
v2 cover QOM'ification of pci-bridge types
Hello Michael et al.,
This series turns PCIBridge, PCIEPort and PCIESlot into abstract QOM types, so that we can use QOM casts to obtain a pointer.
The PCIBridge part was prompted by Don Koch's PCI bridge patch; the remainder by Peter C.'s PCIDevice cast cleanups.
This prepares for turning the two-level qdev PCIDevice initfns into QOM multi-level realizefns, touched upon by Hu Tao's SysBus conversions.
v2 moves qdev properties to PCIEPort/PCIESlot as appropriate.
Regards,
Andreas
v1 -> v2:
* Rebased on PCIBridge change, replacing a new container_of().
* Moved qdev properties to PCIEPort and PCIESlot respectively.
* Don't cleverly avoid parent_obj.parent_obj chains in VMState (mst/aliguori).
Cc Anthony Liguori <[email protected]>
Cc Paolo Bonzini <[email protected]>
Cc Michael S. Tsirkin <[email protected]>
Cc Peter Crosthwaite <[email protected]>
Cc Hu Tao <[email protected]>
Andreas Färber (4):
pci-bridge: Turn PCIBridge into abstract QOM type
pci-bridge-dev: QOM parent field cleanup pci-bridge/i82801b11: Rename parent field
pcie_port: Turn PCIEPort and PCIESlot into abstract QOM types
hw/pci-bridge/dec.c | 4 +-- hw/pci-bridge/i82801b11.c | 10 +++++--- hw/pci-bridge/ioh3420.c | 35 ++++++++----------------- hw/pci-bridge/pci_bridge_dev.c | 26 +++++++++++-------- hw/pci-bridge/xio3130_downstream.c | 35 ++++++++----------------- hw/pci-bridge/xio3130_upstream.c | 26 ++++++------------- hw/pci-host/apb.c | 4 +-- hw/pci/pci.c | 2 +- hw/pci/pci_bridge.c | 40 +++++++++++++++++++++-------- hw/pci/pcie.c | 2 +- hw/pci/pcie_port.c | 52 ++++++++++++++++++++++++++++++++++++++ include/hw/pci/pci_bus.h | 7 ++++- include/hw/pci/pcie_port.h | 14 ++++++++-- 13 files changed, 155 insertions(+), 102 deletions(-)
Signature · 1 line
1.8.1.4
PATCH v2 1/4 pci-bridge: Turn PCIBridge into abstract QOM type
Introduce TYPE_PCI_BRIDGE as base type and use PCI_BRIDGE() casts.
Signed-off-by Andreas Färber <[email protected]>
--- hw/pci-bridge/dec.c | 4 ++-- hw/pci-bridge/i82801b11.c | 6 +++--- hw/pci-bridge/ioh3420.c | 18 ++++++++--------- hw/pci-bridge/pci_bridge_dev.c | 10 +++++----- hw/pci-bridge/xio3130_downstream.c | 18 ++++++++--------- hw/pci-bridge/xio3130_upstream.c | 19 +++++++++--------- hw/pci-host/apb.c | 4 ++-- hw/pci/pci.c | 2 +- hw/pci/pci_bridge.c | 40 +++++++++++++++++++++++++++----------- hw/pci/pcie.c | 2 +- include/hw/pci/pci_bus.h | 7 ++++++- 11 files changed, 77 insertions(+), 53 deletions(-)
hw/pci-bridge/dec.c +2 -2
@@ -74,7 +74,7 @@ static void dec_21154_pci_bridge_class_init(ObjectClass *klass, void *data)static const TypeInfo dec_21154_pci_bridge_info = { .name ="dec-21154-p2p-bridge" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIBridge), .class_init = dec_21154_pci_bridge_class_init, };
@@ -86,7 +86,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) dev =pci_create_multifunction (parent_bus, devfn, false,"dec-21154-p2p-bridge" ); - br =DO_UPCAST (PCIBridge, dev, dev); + br =PCI_BRIDGE (dev);pci_bridge_map_irq (br,"DEC 21154 PCI-PCI bridge" , dec_map_irq);qdev_init_nofail (&dev->qdev);return pci_bridge_get_sec_bus (br);
hw/pci-bridge/i82801b11.c +3 -3
@@ -91,7 +91,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)static const TypeInfo i82801b11_bridge_info = { .name ="i82801b11-bridge" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (I82801b11Bridge), .class_init = i82801b11_bridge_class_init, };
@@ -107,8 +107,8 @@ PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); - qdev = &br->dev.qdev; + br =PCI_BRIDGE (d); + qdev =DEVICE (d);snprintf (buf,sizeof (buf),"pci.%d" , sec_bus);pci_bridge_map_irq (br, buf, pci_swizzle_map_irq_fn);
hw/pci-bridge/ioh3420.c +9 -9
@@ -92,7 +92,7 @@ static void ioh3420_reset(DeviceState *qdev)static int ioh3420_initfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);int rc;
@@ -148,7 +148,7 @@ err_bridge:static void ioh3420_exitfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);
@@ -171,9 +171,9 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); + br =PCI_BRIDGE (d); - qdev = &br->dev.qdev; + qdev =DEVICE (d);pci_bridge_map_irq (br, bus_name, map_irq);qdev_prop_set_uint8 (qdev,"port" , port);qdev_prop_set_uint8 (qdev,"chassis" , chassis);
@@ -190,8 +190,8 @@ static const VMStateDescription vmstate_ioh3420 = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { -VMSTATE_PCIE_DEVICE (port.br.dev, PCIESlot), -VMSTATE_STRUCT (port.br.dev.exp.aer_log, PCIESlot,0 , +VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), +VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () }
@@ -202,8 +202,8 @@ static Property ioh3420_properties[] = {DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ),DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ),DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.dev.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), + port.br.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ), DEFINE_PROP_END_OF_LIST(), };
@@ -228,7 +228,7 @@ static void ioh3420_class_init(ObjectClass *klass, void *data)static const TypeInfo ioh3420_info = { .name ="ioh3420" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIESlot), .class_init = ioh3420_class_init, };
hw/pci-bridge/pci_bridge_dev.c +5 -5
@@ -38,7 +38,7 @@ typedef struct PCIBridgeDev PCIBridgeDev;static int pci_bridge_dev_initfn (PCIDevice *dev) { -PCIBridge *br =DO_UPCAST (PCIBridge, dev, dev); +PCIBridge *br =PCI_BRIDGE (dev);PCIBridgeDev *bridge_dev =DO_UPCAST (PCIBridgeDev, bridge, br);int err;
@@ -81,7 +81,7 @@ bridge_error:static void pci_bridge_dev_exitfn (PCIDevice *dev) { -PCIBridge *br =DO_UPCAST (PCIBridge, dev, dev); +PCIBridge *br =PCI_BRIDGE (dev);PCIBridgeDev *bridge_dev =DO_UPCAST (PCIBridgeDev, bridge, br);if (msi_present (dev)) {msi_uninit (dev);
@@ -120,8 +120,8 @@ static Property pci_bridge_dev_properties[] = {static const VMStateDescription pci_bridge_dev_vmstate = { .name ="pci_bridge" , .fields = (VMStateField []) { -VMSTATE_PCI_DEVICE (bridge.dev, PCIBridgeDev), -SHPC_VMSTATE (bridge.dev.shpc, PCIBridgeDev), +VMSTATE_PCI_DEVICE (bridge.parent_obj, PCIBridgeDev), +SHPC_VMSTATE (bridge.parent_obj.shpc, PCIBridgeDev),VMSTATE_END_OF_LIST () } };
@@ -145,7 +145,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)static const TypeInfo pci_bridge_dev_info = { .name ="pci-bridge" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIBridgeDev), .class_init = pci_bridge_dev_class_init, };
hw/pci-bridge/xio3130_downstream.c +9 -9
@@ -56,7 +56,7 @@ static void xio3130_downstream_reset(DeviceState *qdev)static int xio3130_downstream_initfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);int rc;
@@ -113,7 +113,7 @@ err_bridge:static void xio3130_downstream_exitfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);
@@ -138,9 +138,9 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); + br =PCI_BRIDGE (d); - qdev = &br->dev.qdev; + qdev =DEVICE (d);pci_bridge_map_irq (br, bus_name, map_irq);qdev_prop_set_uint8 (qdev,"port" , port);qdev_prop_set_uint8 (qdev,"chassis" , chassis);
@@ -157,8 +157,8 @@ static const VMStateDescription vmstate_xio3130_downstream = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { -VMSTATE_PCIE_DEVICE (port.br.dev, PCIESlot), -VMSTATE_STRUCT (port.br.dev.exp.aer_log, PCIESlot,0 , +VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), +VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () }
@@ -169,8 +169,8 @@ static Property xio3130_downstream_properties[] = {DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ),DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ),DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.dev.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), + port.br.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ), DEFINE_PROP_END_OF_LIST(), };
@@ -195,7 +195,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)static const TypeInfo xio3130_downstream_info = { .name ="xio3130-downstream" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIESlot), .class_init = xio3130_downstream_class_init, };
hw/pci-bridge/xio3130_upstream.c +10 -9
@@ -53,7 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev)static int xio3130_upstream_initfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);int rc;
@@ -118,9 +118,9 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); + br =PCI_BRIDGE (d); - qdev = &br->dev.qdev; + qdev =DEVICE (d);pci_bridge_map_irq (br, bus_name, map_irq);qdev_prop_set_uint8 (qdev,"port" , port);qdev_init_nofail (qdev);
@@ -134,17 +134,18 @@ static const VMStateDescription vmstate_xio3130_upstream = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { -VMSTATE_PCIE_DEVICE (br.dev, PCIEPort), -VMSTATE_STRUCT (br.dev.exp.aer_log, PCIEPort,0 , vmstate_pcie_aer_log, - PCIEAERLog), +VMSTATE_PCIE_DEVICE (br.parent_obj, PCIEPort), +VMSTATE_STRUCT (br.parent_obj.exp.aer_log, PCIEPort,0 , + vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () } };static Property xio3130_upstream_properties[] = {DEFINE_PROP_UINT8 ("port" , PCIEPort, port,0 ), -DEFINE_PROP_UINT16 ("aer_log_max" , PCIEPort, br.dev.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), +DEFINE_PROP_UINT16 ("aer_log_max" , PCIEPort, + br.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ),DEFINE_PROP_END_OF_LIST (), };
@@ -169,7 +170,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)static const TypeInfo xio3130_upstream_info = { .name ="x3130-upstream" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIEPort), .class_init = xio3130_upstream_class_init, };
hw/pci-host/apb.c +2 -2
@@ -464,7 +464,7 @@ PCIBus *pci_apb_init(hwaddr special_base,/* APB secondary busses */ pci_dev =pci_create_multifunction (d->bus,PCI_DEVFN (1 ,0 ), true,"pbm-bridge" ); - br =DO_UPCAST (PCIBridge, dev, pci_dev); + br =PCI_BRIDGE (pci_dev);pci_bridge_map_irq (br,"Advanced PCI Bus secondary bridge 1" , pci_apb_map_irq);qdev_init_nofail (&pci_dev->qdev);
@@ -472,7 +472,7 @@ PCIBus *pci_apb_init(hwaddr special_base, pci_dev =pci_create_multifunction (d->bus,PCI_DEVFN (1 ,1 ), true,"pbm-bridge" ); - br =DO_UPCAST (PCIBridge, dev, pci_dev); + br =PCI_BRIDGE (pci_dev);pci_bridge_map_irq (br,"Advanced PCI Bus secondary bridge 2" , pci_apb_map_irq);qdev_init_nofail (&pci_dev->qdev);
hw/pci/pci.c +1 -1
@@ -397,7 +397,7 @@ static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)pci_update_mappings (s);if (pc->is_bridge) { -PCIBridge *b =container_of (s, PCIBridge, dev); +PCIBridge *b =PCI_BRIDGE (s);pci_bridge_update_mappings (b); }
hw/pci/pci_bridge.c +29 -11
@@ -141,8 +141,9 @@ static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias, MemoryRegion *parent_space, bool enabled) { -pcibus_t base =pci_bridge_get_base (&bridge->dev, type); -pcibus_t limit =pci_bridge_get_limit (&bridge->dev, type); +PCIDevice *bridge_dev =PCI_DEVICE (bridge); +pcibus_t base =pci_bridge_get_base (bridge_dev, type); +pcibus_t limit =pci_bridge_get_limit (bridge_dev, type);/* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. * Apparently no way to do this with existing memory APIs. */ pcibus_t size = enabled && limit >= base ? limit +1 - base :0 ;
@@ -154,7 +155,8 @@ static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,static void pci_bridge_init_vga_aliases (PCIBridge *br,PCIBus *parent,MemoryRegion *alias_vga) { -uint16_t brctl =pci_get_word (br->dev.config +PCI_BRIDGE_CONTROL ); +PCIDevice *pd =PCI_DEVICE (br); +uint16_t brctl =pci_get_word (pd->config +PCI_BRIDGE_CONTROL ); memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br), "pci_bridge_vga_io_lo", &br->address_space_io,
@@ -167,7 +169,7 @@ static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent, QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);if (brctl &PCI_BRIDGE_CTL_VGA ) { -pci_register_vga (&br->dev, &alias_vga[QEMU_PCI_VGA_MEM ], +pci_register_vga (pd, &alias_vga[QEMU_PCI_VGA_MEM ], &alias_vga[QEMU_PCI_VGA_IO_LO ], &alias_vga[QEMU_PCI_VGA_IO_HI ]); }
@@ -175,9 +177,10 @@ static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,static PCIBridgeWindows *pci_bridge_region_init (PCIBridge *br) { -PCIBus *parent = br->dev.bus; +PCIDevice *pd =PCI_DEVICE (br); +PCIBus *parent = pd->bus;PCIBridgeWindows *w =g_new (PCIBridgeWindows,1 ); -uint16_t cmd =pci_get_word (br->dev.config +PCI_COMMAND ); +uint16_t cmd =pci_get_word (pd->config +PCI_COMMAND ); pci_bridge_init_alias(br, &w->alias_pref_mem, PCI_BASE_ADDRESS_MEM_PREFETCH,
@@ -205,12 +208,13 @@ static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)static void pci_bridge_region_del (PCIBridge *br,PCIBridgeWindows *w) { -PCIBus *parent = br->dev.bus; +PCIDevice *pd =PCI_DEVICE (br); +PCIBus *parent = pd->bus;memory_region_del_subregion (parent->address_space_io, &w->alias_io);memory_region_del_subregion (parent->address_space_mem, &w->alias_mem);memory_region_del_subregion (parent->address_space_mem, &w->alias_pref_mem); -pci_unregister_vga (&br->dev); +pci_unregister_vga (pd); }static void pci_bridge_region_cleanup (PCIBridge *br,PCIBridgeWindows *w)
@@ -241,7 +245,7 @@ void pci_bridge_update_mappings(PCIBridge *br)void pci_bridge_write_config (PCIDevice *d,uint32_t address,uint32_t val,int len) { -PCIBridge *s =container_of (d, PCIBridge, dev); +PCIBridge *s =PCI_BRIDGE (d);uint16_t oldctl =pci_get_word (d->config +PCI_BRIDGE_CONTROL );uint16_t newctl;
@@ -331,7 +335,7 @@ void pci_bridge_reset(DeviceState *qdev)int pci_bridge_initfn (PCIDevice *dev,const char *typename) {PCIBus *parent = dev->bus; -PCIBridge *br =DO_UPCAST (PCIBridge, dev, dev); +PCIBridge *br =PCI_BRIDGE (dev);PCIBus *sec_bus = &br->sec_bus; pci_word_test_and_set_mask(dev->config + PCI_STATUS,
@@ -379,7 +383,7 @@ int pci_bridge_initfn(PCIDevice *dev, const char *typename)/* default qdev clean up function for PCI-to-PCI bridge */ void pci_bridge_exitfn (PCIDevice *pci_dev) { -PCIBridge *s =DO_UPCAST (PCIBridge, dev, pci_dev); +PCIBridge *s =PCI_BRIDGE (pci_dev);assert (QLIST_EMPTY (&s->sec_bus.child));QLIST_REMOVE (&s->sec_bus, sibling);pci_bridge_region_del (s, s->windows);
@@ -400,3 +404,17 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, br->map_irq = map_irq; br->bus_name = bus_name; } + +static const TypeInfo pci_bridge_type_info = { + .name =TYPE_PCI_BRIDGE , + .parent =TYPE_PCI_DEVICE , + .instance_size =sizeof (PCIBridge), + .abstract = true, +}; + +static void pci_bridge_register_types (void ) +{ +type_register_static (&pci_bridge_type_info); +} + +type_init (pci_bridge_register_types)
hw/pci/pcie.c +1 -1
@@ -305,7 +305,7 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) dev->exp.hpev_notified = false; -pci_bus_hotplug (pci_bridge_get_sec_bus (DO_UPCAST (PCIBridge, dev, dev)), +pci_bus_hotplug (pci_bridge_get_sec_bus (PCI_BRIDGE (dev)), pcie_cap_slot_hotplug, &dev->qdev); }
include/hw/pci/pci_bus.h +6 -1
@@ -53,8 +53,13 @@ struct PCIBridgeWindows {MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS ]; }; +#define TYPE_PCI_BRIDGE "base-pci-bridge" +#define PCI_BRIDGE (obj) OBJECT_CHECK(PCIBridge, (obj), TYPE_PCI_BRIDGE) +struct PCIBridge { -PCIDevice dev; +/*< private >*/ +PCIDevice parent_obj; +/*< public >*/ /* private member */ PCIBus sec_bus;
Signature · 1 line
1.8.1.4
Re: [Qemu-devel] [PATCH qom-next v2 1/4] pci-bridge: Turn PCIBridge into abstract QOM type
Quoted 16 lines · Andreas Färber
Introduce
TYPE_PCI_BRIDGEas base type and usePCI_BRIDGE()casts.Signed-off-by Andreas Färber <[email protected]>--- hw/pci-bridge/dec.c | 4 ++-- hw/pci-bridge/i82801b11.c | 6 +++--- hw/pci-bridge/ioh3420.c | 18 ++++++++--------- hw/pci-bridge/pci_bridge_dev.c | 10 +++++----- hw/pci-bridge/xio3130_downstream.c | 18 ++++++++--------- hw/pci-bridge/xio3130_upstream.c | 19 +++++++++--------- hw/pci-host/apb.c | 4 ++-- hw/pci/pci.c | 2 +- hw/pci/pci_bridge.c | 40 +++++++++++++++++++++++++++----------- hw/pci/pcie.c | 2 +- include/hw/pci/pci_bus.h | 7 ++++++- 11 files changed, 77 insertions(+), 53 deletions(-)
Saved me the trouble of doing this myself. Thanks! ;)
Reviewed-by Don Koch <[email protected]>
Re: [Qemu-devel] [PATCH qom-next v2 1/4] pci-bridge: Turn PCIBridge into abstract QOM type
In reply to Andreas FärberQuoted 459 lines · Andreas Färber
Introduce
TYPE_PCI_BRIDGEas base type and usePCI_BRIDGE()casts.Signed-off-by Andreas Färber <[email protected]>--- hw/pci-bridge/dec.c | 4 ++-- hw/pci-bridge/i82801b11.c | 6 +++--- hw/pci-bridge/ioh3420.c | 18 ++++++++--------- hw/pci-bridge/pci_bridge_dev.c | 10 +++++----- hw/pci-bridge/xio3130_downstream.c | 18 ++++++++--------- hw/pci-bridge/xio3130_upstream.c | 19 +++++++++--------- hw/pci-host/apb.c | 4 ++-- hw/pci/pci.c | 2 +- hw/pci/pci_bridge.c | 40 +++++++++++++++++++++++++++----------- hw/pci/pcie.c | 2 +- include/hw/pci/pci_bus.h | 7 ++++++- 11 files changed, 77 insertions(+), 53 deletions(-)hw/pci-bridge/dec.c +2
-2@@ -74,7 +74,7 @@ static void dec_21154_pci_bridge_class_init(ObjectClass *klass, void *data)static const TypeInfo dec_21154_pci_bridge_info = { .name ="dec-21154-p2p-bridge" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIBridge), .class_init = dec_21154_pci_bridge_class_init, };@@ -86,7 +86,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) dev =pci_create_multifunction (parent_bus, devfn, false,"dec-21154-p2p-bridge" ); - br =DO_UPCAST (PCIBridge, dev, dev); + br =PCI_BRIDGE (dev);pci_bridge_map_irq (br,"DEC 21154 PCI-PCI bridge" , dec_map_irq);qdev_init_nofail (&dev->qdev);return pci_bridge_get_sec_bus (br);hw/pci-bridge/i82801b11.c +3
-3@@ -91,7 +91,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)static const TypeInfo i82801b11_bridge_info = { .name ="i82801b11-bridge" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (I82801b11Bridge), .class_init = i82801b11_bridge_class_init, };@@ -107,8 +107,8 @@ PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); - qdev = &br->dev.qdev; + br =PCI_BRIDGE (d); + qdev =DEVICE (d);snprintf (buf,sizeof (buf),"pci.%d" , sec_bus);pci_bridge_map_irq (br, buf, pci_swizzle_map_irq_fn);hw/pci-bridge/ioh3420.c +9
-9@@ -92,7 +92,7 @@ static void ioh3420_reset(DeviceState *qdev)static int ioh3420_initfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);int rc;@@ -148,7 +148,7 @@ err_bridge:static void ioh3420_exitfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);@@ -171,9 +171,9 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); + br =PCI_BRIDGE (d); - qdev = &br->dev.qdev; + qdev =DEVICE (d);pci_bridge_map_irq (br, bus_name, map_irq);qdev_prop_set_uint8 (qdev,"port" , port);qdev_prop_set_uint8 (qdev,"chassis" , chassis);@@ -190,8 +190,8 @@ static const VMStateDescription vmstate_ioh3420 = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { -VMSTATE_PCIE_DEVICE (port.br.dev, PCIESlot), -VMSTATE_STRUCT (port.br.dev.exp.aer_log, PCIESlot,0 , +VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), +VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () }@@ -202,8 +202,8 @@ static Property ioh3420_properties[] = {DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ),DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ),DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.dev.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), + port.br.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ), DEFINE_PROP_END_OF_LIST(), };@@ -228,7 +228,7 @@ static void ioh3420_class_init(ObjectClass *klass, void *data)static const TypeInfo ioh3420_info = { .name ="ioh3420" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIESlot), .class_init = ioh3420_class_init, };hw/pci-bridge/pci_bridge_dev.c +5
-5@@ -38,7 +38,7 @@ typedef struct PCIBridgeDev PCIBridgeDev;static int pci_bridge_dev_initfn (PCIDevice *dev) { -PCIBridge *br =DO_UPCAST (PCIBridge, dev, dev); +PCIBridge *br =PCI_BRIDGE (dev);PCIBridgeDev *bridge_dev =DO_UPCAST (PCIBridgeDev, bridge, br);int err;@@ -81,7 +81,7 @@ bridge_error:static void pci_bridge_dev_exitfn (PCIDevice *dev) { -PCIBridge *br =DO_UPCAST (PCIBridge, dev, dev); +PCIBridge *br =PCI_BRIDGE (dev);PCIBridgeDev *bridge_dev =DO_UPCAST (PCIBridgeDev, bridge, br);if (msi_present (dev)) {msi_uninit (dev);@@ -120,8 +120,8 @@ static Property pci_bridge_dev_properties[] = {static const VMStateDescription pci_bridge_dev_vmstate = { .name ="pci_bridge" , .fields = (VMStateField []) { -VMSTATE_PCI_DEVICE (bridge.dev, PCIBridgeDev), -SHPC_VMSTATE (bridge.dev.shpc, PCIBridgeDev), +VMSTATE_PCI_DEVICE (bridge.parent_obj, PCIBridgeDev), +SHPC_VMSTATE (bridge.parent_obj.shpc, PCIBridgeDev),VMSTATE_END_OF_LIST () } };@@ -145,7 +145,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)static const TypeInfo pci_bridge_dev_info = { .name ="pci-bridge" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIBridgeDev), .class_init = pci_bridge_dev_class_init, };hw/pci-bridge/xio3130_downstream.c +9
-9@@ -56,7 +56,7 @@ static void xio3130_downstream_reset(DeviceState *qdev)static int xio3130_downstream_initfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);int rc;@@ -113,7 +113,7 @@ err_bridge:static void xio3130_downstream_exitfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);@@ -138,9 +138,9 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); + br =PCI_BRIDGE (d); - qdev = &br->dev.qdev; + qdev =DEVICE (d);pci_bridge_map_irq (br, bus_name, map_irq);qdev_prop_set_uint8 (qdev,"port" , port);qdev_prop_set_uint8 (qdev,"chassis" , chassis);@@ -157,8 +157,8 @@ static const VMStateDescription vmstate_xio3130_downstream = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { -VMSTATE_PCIE_DEVICE (port.br.dev, PCIESlot), -VMSTATE_STRUCT (port.br.dev.exp.aer_log, PCIESlot,0 , +VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), +VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () }@@ -169,8 +169,8 @@ static Property xio3130_downstream_properties[] = {DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ),DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ),DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.dev.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), + port.br.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ), DEFINE_PROP_END_OF_LIST(), };@@ -195,7 +195,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)static const TypeInfo xio3130_downstream_info = { .name ="xio3130-downstream" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIESlot), .class_init = xio3130_downstream_class_init, };hw/pci-bridge/xio3130_upstream.c +10
-9@@ -53,7 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev)static int xio3130_upstream_initfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);int rc;@@ -118,9 +118,9 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); + br =PCI_BRIDGE (d); - qdev = &br->dev.qdev; + qdev =DEVICE (d);pci_bridge_map_irq (br, bus_name, map_irq);qdev_prop_set_uint8 (qdev,"port" , port);qdev_init_nofail (qdev);@@ -134,17 +134,18 @@ static const VMStateDescription vmstate_xio3130_upstream = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { -VMSTATE_PCIE_DEVICE (br.dev, PCIEPort), -VMSTATE_STRUCT (br.dev.exp.aer_log, PCIEPort,0 , vmstate_pcie_aer_log, - PCIEAERLog), +VMSTATE_PCIE_DEVICE (br.parent_obj, PCIEPort), +VMSTATE_STRUCT (br.parent_obj.exp.aer_log, PCIEPort,0 , + vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () } };static Property xio3130_upstream_properties[] = {DEFINE_PROP_UINT8 ("port" , PCIEPort, port,0 ), -DEFINE_PROP_UINT16 ("aer_log_max" , PCIEPort, br.dev.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), +DEFINE_PROP_UINT16 ("aer_log_max" , PCIEPort, + br.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ),DEFINE_PROP_END_OF_LIST (), };@@ -169,7 +170,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)static const TypeInfo xio3130_upstream_info = { .name ="x3130-upstream" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIEPort), .class_init = xio3130_upstream_class_init, };hw/pci-host/apb.c +2
-2@@ -464,7 +464,7 @@ PCIBus *pci_apb_init(hwaddr special_base,/* APB secondary busses */ pci_dev =pci_create_multifunction (d->bus,PCI_DEVFN (1 ,0 ), true,"pbm-bridge" ); - br =DO_UPCAST (PCIBridge, dev, pci_dev); + br =PCI_BRIDGE (pci_dev);pci_bridge_map_irq (br,"Advanced PCI Bus secondary bridge 1" , pci_apb_map_irq);qdev_init_nofail (&pci_dev->qdev);@@ -472,7 +472,7 @@ PCIBus *pci_apb_init(hwaddr special_base, pci_dev =pci_create_multifunction (d->bus,PCI_DEVFN (1 ,1 ), true,"pbm-bridge" ); - br =DO_UPCAST (PCIBridge, dev, pci_dev); + br =PCI_BRIDGE (pci_dev);pci_bridge_map_irq (br,"Advanced PCI Bus secondary bridge 2" , pci_apb_map_irq);qdev_init_nofail (&pci_dev->qdev);hw/pci/pci.c +1
-1@@ -397,7 +397,7 @@ static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)pci_update_mappings (s);if (pc->is_bridge) { -PCIBridge *b =container_of (s, PCIBridge, dev); +PCIBridge *b =PCI_BRIDGE (s);pci_bridge_update_mappings (b); }hw/pci/pci_bridge.c +29
-11@@ -141,8 +141,9 @@ static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias, MemoryRegion *parent_space, bool enabled) { -pcibus_t base =pci_bridge_get_base (&bridge->dev, type); -pcibus_t limit =pci_bridge_get_limit (&bridge->dev, type); +PCIDevice *bridge_dev =PCI_DEVICE (bridge); +pcibus_t base =pci_bridge_get_base (bridge_dev, type); +pcibus_t limit =pci_bridge_get_limit (bridge_dev, type);/* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. * Apparently no way to do this with existing memory APIs. */ pcibus_t size = enabled && limit >= base ? limit +1 - base :0 ;@@ -154,7 +155,8 @@ static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,static void pci_bridge_init_vga_aliases (PCIBridge *br,PCIBus *parent,MemoryRegion *alias_vga) { -uint16_t brctl =pci_get_word (br->dev.config +PCI_BRIDGE_CONTROL ); +PCIDevice *pd =PCI_DEVICE (br); +uint16_t brctl =pci_get_word (pd->config +PCI_BRIDGE_CONTROL ); memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br), "pci_bridge_vga_io_lo", &br->address_space_io,@@ -167,7 +169,7 @@ static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent, QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);if (brctl &PCI_BRIDGE_CTL_VGA ) { -pci_register_vga (&br->dev, &alias_vga[QEMU_PCI_VGA_MEM ], +pci_register_vga (pd, &alias_vga[QEMU_PCI_VGA_MEM ], &alias_vga[QEMU_PCI_VGA_IO_LO ], &alias_vga[QEMU_PCI_VGA_IO_HI ]); }@@ -175,9 +177,10 @@ static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,static PCIBridgeWindows *pci_bridge_region_init (PCIBridge *br) { -PCIBus *parent = br->dev.bus; +PCIDevice *pd =PCI_DEVICE (br); +PCIBus *parent = pd->bus;PCIBridgeWindows *w =g_new (PCIBridgeWindows,1 ); -uint16_t cmd =pci_get_word (br->dev.config +PCI_COMMAND ); +uint16_t cmd =pci_get_word (pd->config +PCI_COMMAND ); pci_bridge_init_alias(br, &w->alias_pref_mem, PCI_BASE_ADDRESS_MEM_PREFETCH,@@ -205,12 +208,13 @@ static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)static void pci_bridge_region_del (PCIBridge *br,PCIBridgeWindows *w) { -PCIBus *parent = br->dev.bus; +PCIDevice *pd =PCI_DEVICE (br); +PCIBus *parent = pd->bus;memory_region_del_subregion (parent->address_space_io, &w->alias_io);memory_region_del_subregion (parent->address_space_mem, &w->alias_mem);memory_region_del_subregion (parent->address_space_mem, &w->alias_pref_mem); -pci_unregister_vga (&br->dev); +pci_unregister_vga (pd); }static void pci_bridge_region_cleanup (PCIBridge *br,PCIBridgeWindows *w)@@ -241,7 +245,7 @@ void pci_bridge_update_mappings(PCIBridge *br)void pci_bridge_write_config (PCIDevice *d,uint32_t address,uint32_t val,int len) { -PCIBridge *s =container_of (d, PCIBridge, dev); +PCIBridge *s =PCI_BRIDGE (d);uint16_t oldctl =pci_get_word (d->config +PCI_BRIDGE_CONTROL );uint16_t newctl;@@ -331,7 +335,7 @@ void pci_bridge_reset(DeviceState *qdev)int pci_bridge_initfn (PCIDevice *dev,const char *typename) {PCIBus *parent = dev->bus; -PCIBridge *br =DO_UPCAST (PCIBridge, dev, dev); +PCIBridge *br =PCI_BRIDGE (dev);PCIBus *sec_bus = &br->sec_bus; pci_word_test_and_set_mask(dev->config + PCI_STATUS,@@ -379,7 +383,7 @@ int pci_bridge_initfn(PCIDevice *dev, const char *typename)/* default qdev clean up function for PCI-to-PCI bridge */ void pci_bridge_exitfn (PCIDevice *pci_dev) { -PCIBridge *s =DO_UPCAST (PCIBridge, dev, pci_dev); +PCIBridge *s =PCI_BRIDGE (pci_dev);assert (QLIST_EMPTY (&s->sec_bus.child));QLIST_REMOVE (&s->sec_bus, sibling);pci_bridge_region_del (s, s->windows);@@ -400,3 +404,17 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, br->map_irq = map_irq; br->bus_name = bus_name; } + +static const TypeInfo pci_bridge_type_info = { + .name =TYPE_PCI_BRIDGE , + .parent =TYPE_PCI_DEVICE , + .instance_size =sizeof (PCIBridge), + .abstract = true, +}; + +static void pci_bridge_register_types (void ) +{ +type_register_static (&pci_bridge_type_info); +} + +type_init (pci_bridge_register_types)hw/pci/pcie.c +1
-1@@ -305,7 +305,7 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) dev->exp.hpev_notified = false; -pci_bus_hotplug (pci_bridge_get_sec_bus (DO_UPCAST (PCIBridge, dev, dev)), +pci_bus_hotplug (pci_bridge_get_sec_bus (PCI_BRIDGE (dev)), pcie_cap_slot_hotplug, &dev->qdev); }include/hw/pci/pci_bus.h +1
-0@@ -53,8 +53,13 @@ struct PCIBridgeWindows {MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS ]; }; +#define TYPE_PCI_BRIDGE "base-pci-bridge"
include/hw/pci/pci_bus.h struct PCIBridgeWindows { · line 65
Quoted 10 lines
include/hw/pci/pci_bus.h +5
-1+#define PCI_BRIDGE (obj) OBJECT_CHECK(PCIBridge, (obj), TYPE_PCI_BRIDGE) +struct PCIBridge { -PCIDevice dev; +/*< private >*/ +PCIDevice parent_obj; +/*< public >*/ /* private member */ PCIBus sec_bus;
I'd prefer keeping it called dev as a more descriptive name, but I guess we can live with it as is.
Quoted 2 lines
Signature · 1 line
1.8.1.4
Re: [Qemu-devel] [PATCH qom-next v2 1/4] pci-bridge: Turn PCIBridge into abstract QOM type
In reply to Andreas FärberAm 23.07.2013 00:36, schrieb Andreas Färber:
Quoted 307 lines
Introduce
TYPE_PCI_BRIDGEas base type and usePCI_BRIDGE()casts.Signed-off-by Andreas Färber <[email protected]>--- hw/pci-bridge/dec.c | 4 ++-- hw/pci-bridge/i82801b11.c | 6 +++--- hw/pci-bridge/ioh3420.c | 18 ++++++++--------- hw/pci-bridge/pci_bridge_dev.c | 10 +++++----- hw/pci-bridge/xio3130_downstream.c | 18 ++++++++--------- hw/pci-bridge/xio3130_upstream.c | 19 +++++++++--------- hw/pci-host/apb.c | 4 ++-- hw/pci/pci.c | 2 +- hw/pci/pci_bridge.c | 40 +++++++++++++++++++++++++++----------- hw/pci/pcie.c | 2 +- include/hw/pci/pci_bus.h | 7 ++++++- 11 files changed, 77 insertions(+), 53 deletions(-)hw/pci-bridge/dec.c +2
-2@@ -74,7 +74,7 @@ static void dec_21154_pci_bridge_class_init(ObjectClass *klass, void *data)static const TypeInfo dec_21154_pci_bridge_info = { .name ="dec-21154-p2p-bridge" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIBridge), .class_init = dec_21154_pci_bridge_class_init, };@@ -86,7 +86,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) dev =pci_create_multifunction (parent_bus, devfn, false,"dec-21154-p2p-bridge" ); - br =DO_UPCAST (PCIBridge, dev, dev); + br =PCI_BRIDGE (dev);pci_bridge_map_irq (br,"DEC 21154 PCI-PCI bridge" , dec_map_irq);qdev_init_nofail (&dev->qdev);return pci_bridge_get_sec_bus (br);hw/pci-bridge/i82801b11.c +3
-3@@ -91,7 +91,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)static const TypeInfo i82801b11_bridge_info = { .name ="i82801b11-bridge" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (I82801b11Bridge), .class_init = i82801b11_bridge_class_init, };@@ -107,8 +107,8 @@ PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); - qdev = &br->dev.qdev; + br =PCI_BRIDGE (d); + qdev =DEVICE (d);snprintf (buf,sizeof (buf),"pci.%d" , sec_bus);pci_bridge_map_irq (br, buf, pci_swizzle_map_irq_fn);hw/pci-bridge/ioh3420.c +9
-9@@ -92,7 +92,7 @@ static void ioh3420_reset(DeviceState *qdev)static int ioh3420_initfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);int rc;@@ -148,7 +148,7 @@ err_bridge:static void ioh3420_exitfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);@@ -171,9 +171,9 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); + br =PCI_BRIDGE (d); - qdev = &br->dev.qdev; + qdev =DEVICE (d);pci_bridge_map_irq (br, bus_name, map_irq);qdev_prop_set_uint8 (qdev,"port" , port);qdev_prop_set_uint8 (qdev,"chassis" , chassis);@@ -190,8 +190,8 @@ static const VMStateDescription vmstate_ioh3420 = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { -VMSTATE_PCIE_DEVICE (port.br.dev, PCIESlot), -VMSTATE_STRUCT (port.br.dev.exp.aer_log, PCIESlot,0 , +VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), +VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () }@@ -202,8 +202,8 @@ static Property ioh3420_properties[] = {DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ),DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ),DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.dev.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), + port.br.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ), DEFINE_PROP_END_OF_LIST(), };@@ -228,7 +228,7 @@ static void ioh3420_class_init(ObjectClass *klass, void *data)static const TypeInfo ioh3420_info = { .name ="ioh3420" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIESlot), .class_init = ioh3420_class_init, };hw/pci-bridge/pci_bridge_dev.c +5
-5@@ -38,7 +38,7 @@ typedef struct PCIBridgeDev PCIBridgeDev;static int pci_bridge_dev_initfn (PCIDevice *dev) { -PCIBridge *br =DO_UPCAST (PCIBridge, dev, dev); +PCIBridge *br =PCI_BRIDGE (dev);PCIBridgeDev *bridge_dev =DO_UPCAST (PCIBridgeDev, bridge, br);int err;@@ -81,7 +81,7 @@ bridge_error:static void pci_bridge_dev_exitfn (PCIDevice *dev) { -PCIBridge *br =DO_UPCAST (PCIBridge, dev, dev); +PCIBridge *br =PCI_BRIDGE (dev);PCIBridgeDev *bridge_dev =DO_UPCAST (PCIBridgeDev, bridge, br);if (msi_present (dev)) {msi_uninit (dev);@@ -120,8 +120,8 @@ static Property pci_bridge_dev_properties[] = {static const VMStateDescription pci_bridge_dev_vmstate = { .name ="pci_bridge" , .fields = (VMStateField []) { -VMSTATE_PCI_DEVICE (bridge.dev, PCIBridgeDev), -SHPC_VMSTATE (bridge.dev.shpc, PCIBridgeDev), +VMSTATE_PCI_DEVICE (bridge.parent_obj, PCIBridgeDev), +SHPC_VMSTATE (bridge.parent_obj.shpc, PCIBridgeDev),VMSTATE_END_OF_LIST () } };@@ -145,7 +145,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)static const TypeInfo pci_bridge_dev_info = { .name ="pci-bridge" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIBridgeDev), .class_init = pci_bridge_dev_class_init, };hw/pci-bridge/xio3130_downstream.c +9
-9@@ -56,7 +56,7 @@ static void xio3130_downstream_reset(DeviceState *qdev)static int xio3130_downstream_initfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);int rc;@@ -113,7 +113,7 @@ err_bridge:static void xio3130_downstream_exitfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);PCIESlot *s =DO_UPCAST (PCIESlot, port, p);@@ -138,9 +138,9 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); + br =PCI_BRIDGE (d); - qdev = &br->dev.qdev; + qdev =DEVICE (d);pci_bridge_map_irq (br, bus_name, map_irq);qdev_prop_set_uint8 (qdev,"port" , port);qdev_prop_set_uint8 (qdev,"chassis" , chassis);@@ -157,8 +157,8 @@ static const VMStateDescription vmstate_xio3130_downstream = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { -VMSTATE_PCIE_DEVICE (port.br.dev, PCIESlot), -VMSTATE_STRUCT (port.br.dev.exp.aer_log, PCIESlot,0 , +VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), +VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () }@@ -169,8 +169,8 @@ static Property xio3130_downstream_properties[] = {DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ),DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ),DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.dev.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), + port.br.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ), DEFINE_PROP_END_OF_LIST(), };@@ -195,7 +195,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)static const TypeInfo xio3130_downstream_info = { .name ="xio3130-downstream" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIESlot), .class_init = xio3130_downstream_class_init, };hw/pci-bridge/xio3130_upstream.c +10
-9@@ -53,7 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev)static int xio3130_upstream_initfn (PCIDevice *d) { -PCIBridge * br =DO_UPCAST (PCIBridge, dev, d); +PCIBridge *br =PCI_BRIDGE (d);PCIEPort *p =DO_UPCAST (PCIEPort, br, br);int rc;@@ -118,9 +118,9 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,if (!d) {return NULL ; } - br =DO_UPCAST (PCIBridge, dev, d); + br =PCI_BRIDGE (d); - qdev = &br->dev.qdev; + qdev =DEVICE (d);pci_bridge_map_irq (br, bus_name, map_irq);qdev_prop_set_uint8 (qdev,"port" , port);qdev_init_nofail (qdev);@@ -134,17 +134,18 @@ static const VMStateDescription vmstate_xio3130_upstream = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { -VMSTATE_PCIE_DEVICE (br.dev, PCIEPort), -VMSTATE_STRUCT (br.dev.exp.aer_log, PCIEPort,0 , vmstate_pcie_aer_log, - PCIEAERLog), +VMSTATE_PCIE_DEVICE (br.parent_obj, PCIEPort), +VMSTATE_STRUCT (br.parent_obj.exp.aer_log, PCIEPort,0 , + vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () } };static Property xio3130_upstream_properties[] = {DEFINE_PROP_UINT8 ("port" , PCIEPort, port,0 ), -DEFINE_PROP_UINT16 ("aer_log_max" , PCIEPort, br.dev.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), +DEFINE_PROP_UINT16 ("aer_log_max" , PCIEPort, + br.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ),DEFINE_PROP_END_OF_LIST (), };@@ -169,7 +170,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)static const TypeInfo xio3130_upstream_info = { .name ="x3130-upstream" , - .parent =TYPE_PCI_DEVICE , + .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIEPort), .class_init = xio3130_upstream_class_init, };hw/pci-host/apb.c +1
-1@@ -464,7 +464,7 @@ PCIBus *pci_apb_init(hwaddr special_base,/* APB secondary busses */ pci_dev =pci_create_multifunction (d->bus,PCI_DEVFN (1 ,0 ), true,"pbm-bridge" ); - br =DO_UPCAST (PCIBridge, dev, pci_dev); + br =PCI_BRIDGE (pci_dev);pci_bridge_map_irq (br,"Advanced PCI Bus secondary bridge 1" , pci_apb_map_irq);qdev_init_nofail (&pci_dev->qdev);
hw/pci-host/apb.c PCIBus *pci_apb_init(hwaddr special_base, · line 478
Quoted 8 lines
hw/pci-host/apb.c +1
-1@@ -472,7 +472,7 @@ PCIBus *pci_apb_init(hwaddr special_base, pci_dev =pci_create_multifunction (d->bus,PCI_DEVFN (1 ,1 ), true,"pbm-bridge" ); - br =DO_UPCAST (PCIBridge, dev, pci_dev); + br =PCI_BRIDGE (pci_dev);pci_bridge_map_irq (br,"Advanced PCI Bus secondary bridge 2" , pci_apb_map_irq);qdev_init_nofail (&pci_dev->qdev);
This needs the following fixup. Thanks to Paolo for adding and enabling sparc64 qtests that uncovered this.
Andreas
hw/pci-host/apb.c +0 -0
@@ -564,8 +564,7 @@ static void pbm_pci_bridge_class_init(ObjectClass
*klass, void *data)
static const TypeInfo pbm_pci_bridge_info = {
.name = "pbm-bridge",
- .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PCIBridge), + .parent = TYPE_PCI_BRIDGE,
.class_init = pbm_pci_bridge_class_init,
};
Signature · 2 lines
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
PATCH v2 2/4 pci-bridge-dev: QOM parent field cleanup
In reply to Andreas FärberSigned-off-by Peter Crosthwaite <[email protected]>
Signed-off-by Andreas Färber <[email protected]>
--- hw/pci-bridge/pci_bridge_dev.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-)
hw/pci-bridge/pci_bridge_dev.c +14 -8
@@ -27,8 +27,15 @@#include "exec/memory.h" #include "hw/pci/pci_bus.h" +#define TYPE_PCI_BRIDGE_DEV "pci-bridge" +#define PCI_BRIDGE_DEV (obj) \ + OBJECT_CHECK(PCIBridgeDev, (obj), TYPE_PCI_BRIDGE_DEV) +struct PCIBridgeDev { -PCIBridge bridge; +/*< private >*/ +PCIBridge parent_obj; +/*< public >*/ +MemoryRegion bar;uint8_t chassis_nr;#define PCI_BRIDGE_DEV_F_MSI_REQ 0
@@ -39,7 +46,7 @@ typedef struct PCIBridgeDev PCIBridgeDev;static int pci_bridge_dev_initfn (PCIDevice *dev) {PCIBridge *br =PCI_BRIDGE (dev); -PCIBridgeDev *bridge_dev =DO_UPCAST (PCIBridgeDev, bridge, br); +PCIBridgeDev *bridge_dev =PCI_BRIDGE_DEV (dev);int err; err =pci_bridge_initfn (dev,TYPE_PCI_BUS );
@@ -81,8 +88,7 @@ bridge_error:static void pci_bridge_dev_exitfn (PCIDevice *dev) { -PCIBridge *br =PCI_BRIDGE (dev); -PCIBridgeDev *bridge_dev =DO_UPCAST (PCIBridgeDev, bridge, br); +PCIBridgeDev *bridge_dev =PCI_BRIDGE_DEV (dev);if (msi_present (dev)) {msi_uninit (dev); }
@@ -104,7 +110,7 @@ static void pci_bridge_dev_write_config(PCIDevice *d,static void qdev_pci_bridge_dev_reset (DeviceState *qdev) { -PCIDevice *dev =DO_UPCAST (PCIDevice, qdev, qdev); +PCIDevice *dev =PCI_DEVICE (qdev);pci_bridge_reset (qdev);shpc_reset (dev);
@@ -120,8 +126,8 @@ static Property pci_bridge_dev_properties[] = {static const VMStateDescription pci_bridge_dev_vmstate = { .name ="pci_bridge" , .fields = (VMStateField []) { -VMSTATE_PCI_DEVICE (bridge.parent_obj, PCIBridgeDev), -SHPC_VMSTATE (bridge.parent_obj.shpc, PCIBridgeDev), +VMSTATE_PCI_DEVICE (parent_obj, PCIBridge), +SHPC_VMSTATE (shpc, PCIDevice),VMSTATE_END_OF_LIST () } };
@@ -144,7 +150,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data) }static const TypeInfo pci_bridge_dev_info = { - .name ="pci-bridge" , + .name =TYPE_PCI_BRIDGE_DEV , .parent =TYPE_PCI_BRIDGE , .instance_size =sizeof (PCIBridgeDev), .class_init = pci_bridge_dev_class_init,
Signature · 1 line
1.8.1.4
Re: [Qemu-devel] [PATCH qom-next v2 2/4] pci-bridge-dev: QOM parent field cleanup
Quoted 6 lines · Andreas Färber
Signed-off-by Peter Crosthwaite <[email protected]>Signed-off-by Andreas Färber <[email protected]>--- hw/pci-bridge/pci_bridge_dev.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-)
Reviewed-by Don Koch <[email protected]>
PATCH v2 3/4 pci-bridge/i82801b11: Rename parent field
In reply to Andreas FärberSigned-off-by Andreas Färber <[email protected]>
--- hw/pci-bridge/i82801b11.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
hw/pci-bridge/i82801b11.c +3 -1
@@ -52,7 +52,9 @@#define I82801ba_SSVID_SSID 0typedef struct I82801b11Bridge { -PCIBridge br; +/*< private >*/ +PCIBridge parent_obj; +/*< public >*/ }I82801b11Bridge ;static int i82801b11_bridge_initfn (PCIDevice *d)
Signature · 1 line
1.8.1.4
Re: [Qemu-devel] [PATCH qom-next v2 3/4] pci-bridge/i82801b11: Rename parent field
Quoted 5 lines · Andreas Färber
Signed-off-by Andreas Färber <[email protected]>--- hw/pci-bridge/i82801b11.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by Don Koch <[email protected]>
PATCH v2 4/4 pcie_port: Turn PCIEPort and PCIESlot into abstract QOM types
In reply to Andreas FärberMove PCIEPort's "port" property to the new type, same for "aer_log_max". Move PCIESlot's "chassis" and "slot" properties to the new type.
Signed-off-by Andreas Färber <[email protected]>
--- hw/pci-bridge/ioh3420.c | 31 ++++++----------------- hw/pci-bridge/xio3130_downstream.c | 31 ++++++----------------- hw/pci-bridge/xio3130_upstream.c | 21 ++++----------- hw/pci/pcie_port.c | 52 ++++++++++++++++++++++++++++++++++++++ include/hw/pci/pcie_port.h | 14 ++++++++-- 5 files changed, 85 insertions(+), 64 deletions(-)
hw/pci-bridge/ioh3420.c +8 -23
@@ -92,9 +92,8 @@ static void ioh3420_reset(DeviceState *qdev)static int ioh3420_initfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); -PCIESlot *s =DO_UPCAST (PCIESlot, port, p); +PCIEPort *p =PCIE_PORT (d); +PCIESlot *s =PCIE_SLOT (d);int rc; rc =pci_bridge_initfn (d,TYPE_PCIE_BUS );
@@ -148,9 +147,7 @@ err_bridge:static void ioh3420_exitfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); -PCIESlot *s =DO_UPCAST (PCIESlot, port, p); +PCIESlot *s =PCIE_SLOT (d);pcie_aer_exit (d);pcie_chassis_del_slot (s);
@@ -180,7 +177,7 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,qdev_prop_set_uint16 (qdev,"slot" , slot);qdev_init_nofail (qdev); -return DO_UPCAST (PCIESlot, port,DO_UPCAST (PCIEPort, br, br)); +return PCIE_SLOT (d); }static const VMStateDescription vmstate_ioh3420 = {
@@ -190,23 +187,13 @@ static const VMStateDescription vmstate_ioh3420 = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField []) { -VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), -VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , - vmstate_pcie_aer_log, PCIEAERLog), +VMSTATE_PCIE_DEVICE (parent_obj.parent_obj.parent_obj, PCIESlot), +VMSTATE_STRUCT (parent_obj.parent_obj.parent_obj.exp.aer_log, + PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () } }; -static Property ioh3420_properties[] = { -DEFINE_PROP_UINT8 ("port" , PCIESlot, port.port,0 ), -DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ), -DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ), -DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.parent_obj.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), -DEFINE_PROP_END_OF_LIST (), -}; -static void ioh3420_class_init (ObjectClass *klass,void *data) {DeviceClass *dc =DEVICE_CLASS (klass);
@@ -223,13 +210,11 @@ static void ioh3420_class_init(ObjectClass *klass, void *data) dc->desc ="Intel IOH device id 3420 PCIE Root Port" ; dc->reset = ioh3420_reset; dc->vmsd = &vmstate_ioh3420; - dc->props = ioh3420_properties; }static const TypeInfo ioh3420_info = { .name ="ioh3420" , - .parent =TYPE_PCI_BRIDGE , - .instance_size =sizeof (PCIESlot), + .parent =TYPE_PCIE_SLOT , .class_init = ioh3420_class_init, };
hw/pci-bridge/xio3130_downstream.c +8 -23
@@ -56,9 +56,8 @@ static void xio3130_downstream_reset(DeviceState *qdev)static int xio3130_downstream_initfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); -PCIESlot *s =DO_UPCAST (PCIESlot, port, p); +PCIEPort *p =PCIE_PORT (d); +PCIESlot *s =PCIE_SLOT (d);int rc; rc =pci_bridge_initfn (d,TYPE_PCIE_BUS );
@@ -113,9 +112,7 @@ err_bridge:static void xio3130_downstream_exitfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); -PCIESlot *s =DO_UPCAST (PCIESlot, port, p); +PCIESlot *s =PCIE_SLOT (d);pcie_aer_exit (d);pcie_chassis_del_slot (s);
@@ -147,7 +144,7 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,qdev_prop_set_uint16 (qdev,"slot" , slot);qdev_init_nofail (qdev); -return DO_UPCAST (PCIESlot, port,DO_UPCAST (PCIEPort, br, br)); +return PCIE_SLOT (d); }static const VMStateDescription vmstate_xio3130_downstream = {
@@ -157,23 +154,13 @@ static const VMStateDescription vmstate_xio3130_downstream = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField []) { -VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), -VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , - vmstate_pcie_aer_log, PCIEAERLog), +VMSTATE_PCIE_DEVICE (parent_obj.parent_obj.parent_obj, PCIESlot), +VMSTATE_STRUCT (parent_obj.parent_obj.parent_obj.exp.aer_log, + PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () } }; -static Property xio3130_downstream_properties[] = { -DEFINE_PROP_UINT8 ("port" , PCIESlot, port.port,0 ), -DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ), -DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ), -DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.parent_obj.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), -DEFINE_PROP_END_OF_LIST (), -}; -static void xio3130_downstream_class_init (ObjectClass *klass,void *data) {DeviceClass *dc =DEVICE_CLASS (klass);
@@ -190,13 +177,11 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data) dc->desc ="TI X3130 Downstream Port of PCI Express Switch" ; dc->reset = xio3130_downstream_reset; dc->vmsd = &vmstate_xio3130_downstream; - dc->props = xio3130_downstream_properties; }static const TypeInfo xio3130_downstream_info = { .name ="xio3130-downstream" , - .parent =TYPE_PCI_BRIDGE , - .instance_size =sizeof (PCIESlot), + .parent =TYPE_PCIE_SLOT , .class_init = xio3130_downstream_class_init, };
hw/pci-bridge/xio3130_upstream.c +5 -16
@@ -53,8 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev)static int xio3130_upstream_initfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); +PCIEPort *p =PCIE_PORT (d);int rc; rc =pci_bridge_initfn (d,TYPE_PCIE_BUS );
@@ -125,7 +124,7 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,qdev_prop_set_uint8 (qdev,"port" , port);qdev_init_nofail (qdev); -return DO_UPCAST (PCIEPort, br, br); +return PCIE_PORT (d); }static const VMStateDescription vmstate_xio3130_upstream = {
@@ -134,21 +133,13 @@ static const VMStateDescription vmstate_xio3130_upstream = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { -VMSTATE_PCIE_DEVICE (br.parent_obj, PCIEPort), -VMSTATE_STRUCT (br.parent_obj.exp.aer_log, PCIEPort,0 , +VMSTATE_PCIE_DEVICE (parent_obj.parent_obj, PCIEPort), +VMSTATE_STRUCT (parent_obj.parent_obj.exp.aer_log, PCIEPort,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () } }; -static Property xio3130_upstream_properties[] = { -DEFINE_PROP_UINT8 ("port" , PCIEPort, port,0 ), -DEFINE_PROP_UINT16 ("aer_log_max" , PCIEPort, - br.parent_obj.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), -DEFINE_PROP_END_OF_LIST (), -}; -static void xio3130_upstream_class_init (ObjectClass *klass,void *data) {DeviceClass *dc =DEVICE_CLASS (klass);
@@ -165,13 +156,11 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data) dc->desc ="TI X3130 Upstream Port of PCI Express Switch" ; dc->reset = xio3130_upstream_reset; dc->vmsd = &vmstate_xio3130_upstream; - dc->props = xio3130_upstream_properties; }static const TypeInfo xio3130_upstream_info = { .name ="x3130-upstream" , - .parent =TYPE_PCI_BRIDGE , - .instance_size =sizeof (PCIEPort), + .parent =TYPE_PCIE_PORT , .class_init = xio3130_upstream_class_init, };
hw/pci/pcie_port.c +52 -0
55 lines not on this page · raw message
include/hw/pci/pcie_port.h +12 -2
@@ -24,8 +24,13 @@#include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" +#define TYPE_PCIE_PORT "pcie-port" +#define PCIE_PORT (obj) OBJECT_CHECK(PCIEPort, (obj), TYPE_PCIE_PORT) +struct PCIEPort { -PCIBridge br; +/*< private >*/ +PCIBridge parent_obj; +/*< public >*/ /* pci express switch port */ uint8_t port;
@@ -33,8 +38,13 @@ struct PCIEPort {void pcie_port_init_reg (PCIDevice *d); +#define TYPE_PCIE_SLOT "pcie-slot" +#define PCIE_SLOT (obj) OBJECT_CHECK(PCIESlot, (obj), TYPE_PCIE_SLOT) +struct PCIESlot { -PCIEPort port; +/*< private >*/ +PCIEPort parent_obj; +/*< public >*/ /* pci express switch port with slot */ uint8_t chassis;
Signature · 1 line
1.8.1.4
Re: [Qemu-devel] [PATCH qom-next v2 4/4] pcie_port: Turn PCIEPort and PCIESlot into abstract QOM types
Quoted 12 lines · Andreas Färber
Move PCIEPort's "port" property to the new type, same for "
aer_log_max". Move PCIESlot's "chassis" and "slot" properties to the new type.Signed-off-by Andreas Färber <[email protected]>--- hw/pci-bridge/ioh3420.c | 31 ++++++----------------- hw/pci-bridge/xio3130_downstream.c | 31 ++++++----------------- hw/pci-bridge/xio3130_upstream.c | 21 ++++----------- hw/pci/pcie_port.c | 52 ++++++++++++++++++++++++++++++++++++++ include/hw/pci/pcie_port.h | 14 ++++++++-- 5 files changed, 85 insertions(+), 64 deletions(-)
Reviewed-by Don Koch <[email protected]>
Re: [Qemu-devel] [PATCH qom-next v2 4/4] pcie_port: Turn PCIEPort and PCIESlot into abstract QOM types
In reply to Andreas FärberQuoted 192 lines · Andreas Färber
Move PCIEPort's "port" property to the new type, same for "
aer_log_max". Move PCIESlot's "chassis" and "slot" properties to the new type.Signed-off-by Andreas Färber <[email protected]>--- hw/pci-bridge/ioh3420.c | 31 ++++++----------------- hw/pci-bridge/xio3130_downstream.c | 31 ++++++----------------- hw/pci-bridge/xio3130_upstream.c | 21 ++++----------- hw/pci/pcie_port.c | 52 ++++++++++++++++++++++++++++++++++++++ include/hw/pci/pcie_port.h | 14 ++++++++-- 5 files changed, 85 insertions(+), 64 deletions(-)hw/pci-bridge/ioh3420.c +8
-23@@ -92,9 +92,8 @@ static void ioh3420_reset(DeviceState *qdev)static int ioh3420_initfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); -PCIESlot *s =DO_UPCAST (PCIESlot, port, p); +PCIEPort *p =PCIE_PORT (d); +PCIESlot *s =PCIE_SLOT (d);int rc; rc =pci_bridge_initfn (d,TYPE_PCIE_BUS );@@ -148,9 +147,7 @@ err_bridge:static void ioh3420_exitfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); -PCIESlot *s =DO_UPCAST (PCIESlot, port, p); +PCIESlot *s =PCIE_SLOT (d);pcie_aer_exit (d);pcie_chassis_del_slot (s);@@ -180,7 +177,7 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,qdev_prop_set_uint16 (qdev,"slot" , slot);qdev_init_nofail (qdev); -return DO_UPCAST (PCIESlot, port,DO_UPCAST (PCIEPort, br, br)); +return PCIE_SLOT (d); }static const VMStateDescription vmstate_ioh3420 = {@@ -190,23 +187,13 @@ static const VMStateDescription vmstate_ioh3420 = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField []) { -VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), -VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , - vmstate_pcie_aer_log, PCIEAERLog), +VMSTATE_PCIE_DEVICE (parent_obj.parent_obj.parent_obj, PCIESlot), +VMSTATE_STRUCT (parent_obj.parent_obj.parent_obj.exp.aer_log, + PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () } }; -static Property ioh3420_properties[] = { -DEFINE_PROP_UINT8 ("port" , PCIESlot, port.port,0 ), -DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ), -DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ), -DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.parent_obj.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), -DEFINE_PROP_END_OF_LIST (), -}; -static void ioh3420_class_init (ObjectClass *klass,void *data) {DeviceClass *dc =DEVICE_CLASS (klass);@@ -223,13 +210,11 @@ static void ioh3420_class_init(ObjectClass *klass, void *data) dc->desc ="Intel IOH device id 3420 PCIE Root Port" ; dc->reset = ioh3420_reset; dc->vmsd = &vmstate_ioh3420; - dc->props = ioh3420_properties; }static const TypeInfo ioh3420_info = { .name ="ioh3420" , - .parent =TYPE_PCI_BRIDGE , - .instance_size =sizeof (PCIESlot), + .parent =TYPE_PCIE_SLOT , .class_init = ioh3420_class_init, };hw/pci-bridge/xio3130_downstream.c +8
-23@@ -56,9 +56,8 @@ static void xio3130_downstream_reset(DeviceState *qdev)static int xio3130_downstream_initfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); -PCIESlot *s =DO_UPCAST (PCIESlot, port, p); +PCIEPort *p =PCIE_PORT (d); +PCIESlot *s =PCIE_SLOT (d);int rc; rc =pci_bridge_initfn (d,TYPE_PCIE_BUS );@@ -113,9 +112,7 @@ err_bridge:static void xio3130_downstream_exitfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); -PCIESlot *s =DO_UPCAST (PCIESlot, port, p); +PCIESlot *s =PCIE_SLOT (d);pcie_aer_exit (d);pcie_chassis_del_slot (s);@@ -147,7 +144,7 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,qdev_prop_set_uint16 (qdev,"slot" , slot);qdev_init_nofail (qdev); -return DO_UPCAST (PCIESlot, port,DO_UPCAST (PCIEPort, br, br)); +return PCIE_SLOT (d); }static const VMStateDescription vmstate_xio3130_downstream = {@@ -157,23 +154,13 @@ static const VMStateDescription vmstate_xio3130_downstream = { .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField []) { -VMSTATE_PCIE_DEVICE (port.br.parent_obj, PCIESlot), -VMSTATE_STRUCT (port.br.parent_obj.exp.aer_log, PCIESlot,0 , - vmstate_pcie_aer_log, PCIEAERLog), +VMSTATE_PCIE_DEVICE (parent_obj.parent_obj.parent_obj, PCIESlot), +VMSTATE_STRUCT (parent_obj.parent_obj.parent_obj.exp.aer_log, + PCIESlot,0 , vmstate_pcie_aer_log, PCIEAERLog),VMSTATE_END_OF_LIST () } }; -static Property xio3130_downstream_properties[] = { -DEFINE_PROP_UINT8 ("port" , PCIESlot, port.port,0 ), -DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ), -DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ), -DEFINE_PROP_UINT16 ("aer_log_max" , PCIESlot, - port.br.parent_obj.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), -DEFINE_PROP_END_OF_LIST (), -}; -static void xio3130_downstream_class_init (ObjectClass *klass,void *data) {DeviceClass *dc =DEVICE_CLASS (klass);@@ -190,13 +177,11 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data) dc->desc ="TI X3130 Downstream Port of PCI Express Switch" ; dc->reset = xio3130_downstream_reset; dc->vmsd = &vmstate_xio3130_downstream; - dc->props = xio3130_downstream_properties; }static const TypeInfo xio3130_downstream_info = { .name ="xio3130-downstream" , - .parent =TYPE_PCI_BRIDGE , - .instance_size =sizeof (PCIESlot), + .parent =TYPE_PCIE_SLOT , .class_init = xio3130_downstream_class_init, };hw/pci-bridge/xio3130_upstream.c +2
-3@@ -53,8 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev)static int xio3130_upstream_initfn (PCIDevice *d) { -PCIBridge *br =PCI_BRIDGE (d); -PCIEPort *p =DO_UPCAST (PCIEPort, br, br); +PCIEPort *p =PCIE_PORT (d);int rc; rc =pci_bridge_initfn (d,TYPE_PCIE_BUS );@@ -125,7 +124,7 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,qdev_prop_set_uint8 (qdev,"port" , port);qdev_init_nofail (qdev); -return DO_UPCAST (PCIEPort, br, br); +return PCIE_PORT (d); }static const VMStateDescription vmstate_xio3130_upstream = {
hw/pci-bridge/xio3130_upstream.c static const VMStateDescription vmstate_xio3130_upstream = { · line 138
Quoted 8 lines
hw/pci-bridge/xio3130_upstream.c +2
-2@@ -134,21 +133,13 @@ static const VMStateDescription vmstate_xio3130_upstream = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { -VMSTATE_PCIE_DEVICE (br.parent_obj, PCIEPort), -VMSTATE_STRUCT (br.parent_obj.exp.aer_log, PCIEPort,0 , +VMSTATE_PCIE_DEVICE (parent_obj.parent_obj, PCIEPort), +VMSTATE_STRUCT (parent_obj.parent_obj.exp.aer_log, PCIEPort,0 , vmstate_pcie_aer_log, PCIEAERLog),
So this horror is due to insistance of calling the first structure in each struct "parent_obj". I never understood why it's a good idea.
Quoted 114 lines
hw/pci-bridge/xio3130_upstream.c +1
-11VMSTATE_END_OF_LIST() } }; -static Property xio3130_upstream_properties[] = { -DEFINE_PROP_UINT8 ("port" , PCIEPort, port,0 ), -DEFINE_PROP_UINT16 ("aer_log_max" , PCIEPort, - br.parent_obj.exp.aer_log.log_max, -PCIE_AER_LOG_MAX_DEFAULT ), -DEFINE_PROP_END_OF_LIST (), -}; -static void xio3130_upstream_class_init (ObjectClass *klass,void *data) {DeviceClass *dc =DEVICE_CLASS (klass);@@ -165,13 +156,11 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data) dc->desc ="TI X3130 Upstream Port of PCI Express Switch" ; dc->reset = xio3130_upstream_reset; dc->vmsd = &vmstate_xio3130_upstream; - dc->props = xio3130_upstream_properties; }static const TypeInfo xio3130_upstream_info = { .name ="x3130-upstream" , - .parent =TYPE_PCI_BRIDGE , - .instance_size =sizeof (PCIEPort), + .parent =TYPE_PCIE_PORT , .class_init = xio3130_upstream_class_init, };hw/pci/pcie_port.c +52
-0@@ -116,3 +116,55 @@ void pcie_chassis_del_slot(PCIESlot *s) {QLIST_REMOVE (s, next); } + +static Property pcie_port_props[] = { +DEFINE_PROP_UINT8 ("port" , PCIEPort, port,0 ), +DEFINE_PROP_UINT16 ("aer_log_max" , PCIEPort, + parent_obj.parent_obj.exp.aer_log.log_max, +PCIE_AER_LOG_MAX_DEFAULT ), +DEFINE_PROP_END_OF_LIST () +}; + +static void pcie_port_class_init (ObjectClass *oc,void *data) +{ +DeviceClass *dc =DEVICE_CLASS (oc); + + dc->props = pcie_port_props; +} + +static const TypeInfo pcie_port_type_info = { + .name =TYPE_PCIE_PORT , + .parent =TYPE_PCI_BRIDGE , + .instance_size =sizeof (PCIEPort), + .abstract = true, + .class_init = pcie_port_class_init, +}; + +static Property pcie_slot_props[] = { +DEFINE_PROP_UINT8 ("chassis" , PCIESlot, chassis,0 ), +DEFINE_PROP_UINT16 ("slot" , PCIESlot, slot,0 ), +DEFINE_PROP_END_OF_LIST () +}; + +static void pcie_slot_class_init (ObjectClass *oc,void *data) +{ +DeviceClass *dc =DEVICE_CLASS (oc); + + dc->props = pcie_slot_props; +} + +static const TypeInfo pcie_slot_type_info = { + .name =TYPE_PCIE_SLOT , + .parent =TYPE_PCIE_PORT , + .instance_size =sizeof (PCIESlot), + .abstract = true, + .class_init = pcie_slot_class_init, +}; + +static void pcie_port_register_types (void ) +{ +type_register_static (&pcie_port_type_info); +type_register_static (&pcie_slot_type_info); +} + +type_init (pcie_port_register_types)include/hw/pci/pcie_port.h +7
-1@@ -24,8 +24,13 @@#include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" +#define TYPE_PCIE_PORT "pcie-port" +#define PCIE_PORT (obj) OBJECT_CHECK(PCIEPort, (obj), TYPE_PCIE_PORT) +struct PCIEPort { -PCIBridge br; +/*< private >*/ +PCIBridge parent_obj; +/*< public >*/ /* pci express switch port */ uint8_t port;@@ -33,8 +38,13 @@ struct PCIEPort {void pcie_port_init_reg (PCIDevice *d); +#define TYPE_PCIE_SLOT "pcie-slot"
include/hw/pci/pcie_port.h struct PCIEPort { · line 50
Quoted 10 lines
include/hw/pci/pcie_port.h +5
-1+#define PCIE_SLOT (obj) OBJECT_CHECK(PCIESlot, (obj), TYPE_PCIE_SLOT) +struct PCIESlot { -PCIEPort port; +/*< private >*/ +PCIEPort parent_obj; +/*< public >*/ /* pci express switch port with slot */ uint8_t chassis;
I don't like how everthing is called parent_obj instead of what it really is, but since this appears to be in vogue at the moment
Quoted 2 lines
Signature · 1 line
1.8.1.4
Andreas Färber
AppliedAm 23.07.2013 00:36, schrieb Andreas Färber:
Quoted 5 lines
Andreas Färber (4):
pci-bridge: Turn PCIBridge into abstract QOM type
pci-bridge-dev: QOM parent field cleanup pci-bridge/i82801b11: Rename parent field
pcie_port: Turn PCIEPort and PCIESlot into abstract QOM types
Thanks, applied to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
The story behind parent_obj and the gtk-doc markup as far as I've inferred from Anthony's patches is
a) C++ for one does not have a field to access the parent class' fields, you access them directly, which TYPE_NAME() casts and using different-but-the-same pointers abstract and
b) it makes it easier for me to recognize which struct corresponds to a QOM object and which is just used inside some object's struct or elsewhere.
The practical use of renaming for me is to have the compiler check for parent field uses, to avoid concurrent merges such as Don's PCIBridge fix (which should go through the appropriate queues without delay, no criticism there) adding more uses and a 98% cleanup getting merged afterwards, requiring yet another round of cleanups. (Compare my SysBus cleanups, where I missed some ->qdev accesses, which I only noticed later when I did rename the parent field.)
I've sent out a series cleaning up the aer_log VMSTATE_STRUCT() and VMSTATE_MSIX() for you and Juan to review, which minimizes the use of parent_obj chains.
That leaves VMSTATE_PCIE_DEVICE() as user of parent_obj; I'm not sure about how to interpret Anthony's comment on v1, I'll inquire and hope we can get this cleaned up post-1.6, too. Ideally before more PCI parent fields get renamed and show up in such diffs.
One cool out-of-tree use case for PCI_DEVICE() that Peter C. has been explaining to me is reuse of PCI IP with SysBus by changing the .parent of TYPE_PCI_DEVICE and replacing the qdev field accordingly. Not applicable to upstream of course, we'd need QOM interfaces for that and I guess, a VMState solution for such "multi-inheritence" interfaces.
Regards,
Andreas
Signature · 2 lines
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