ARM: EXYNOS: add power domains support for EXYNOS5440
PATCH 1/1 ARM: EXYNOS: add power domains support for EXYNOS5440
On EXYNOS5440 power domains are handled in a different way than on the previous EXYNOS SoCs. Add support for them to EXYNOS pm_domains driver. Then add device tree nodes for PCIe (controlling power for PCIe host controller) and Conn2 (controlling power for Ethernet, SATA and USB controllers) power domains to exynos5440.dtsi.
Currently if runtime Power Management is enabled and the driver for devices under power domain is disabled then the power domain will be disabled by EXYNOS pm_domains driver. To make more active use of power domains (dynamically enable and disabled them as needed) it is required to add runtime PM support to pci-exynos, stmmac, ahci_platform, ohci-exynos and ehci-s5p drivers (to be done later).
--- Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 33 ++ arch/arm/boot/dts/exynos5440.dtsi | 23 + arch/arm/mach-exynos/Kconfig | 1 arch/arm/mach-exynos/common.c | 4 arch/arm/mach-exynos/pm_domains.c | 138 +++++++++- 5 files changed, 190 insertions(+), 9 deletions(-)
Documentation/devicetree/bindings/arm/exynos/power_domain.txt +30 -3
@@ -5,20 +5,47 @@ to gate power to one or more peripherals Required Properties: - compatible: should be one of the following. - * samsung,exynos4210-pd - for exynos4210 type power domain. + * samsung,exynos4210-pd - for Exynos4210 type power domain. + * samsung,exynos5440-pd - for Exynos5440 type power domain. - reg: physical base address of the controller and length of memory mapped - region. + region (Exynos4210 type power domain) or bit offset in the control + register (Exynos5440 type power domain). + +Additional parent node must be created for Exynos5440 power domains with +the following required properties: +- compatible: samsung,exynos5440-power-domains, simple-bus +- reg: physical base address of the XMU controller and length of memory + mapped region Node of a device using power domains must have a samsung,power-domain property defined with a phandle to respective power domain. -Example: +Example for Exynos4210 compatible power domain: lcd0: power-domain-lcd0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x10>; }; +Example for Exynos5440 compatible power domains: + + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + Example of the node using power domain: node {
arch/arm/boot/dts/exynos5440.dtsi +23 -0
@@ -29,6 +29,23 @@ #clock-cells = <1>; }; + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + gic:interrupt-controller at 2E0000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;
@@ -192,6 +209,7 @@ phy-mode = "sgmii"; clocks = <&clock 25>; clock-names = "stmmaceth"; + samsung,power-domain = <&pd_conn2>; }; amba {
@@ -240,6 +258,7 @@ interrupts = <0 30 0>; clocks = <&clock 23>; clock-names = "sata"; + samsung,power-domain = <&pd_conn2>; }; ohci at 220000 {
@@ -248,6 +267,7 @@ interrupts = <0 29 0>; clocks = <&clock 24>; clock-names = "usbhost"; + samsung,power-domain = <&pd_conn2>; }; ehci at 221000 {
@@ -256,6 +276,7 @@ interrupts = <0 29 0>; clocks = <&clock 24>; clock-names = "usbhost"; + samsung,power-domain = <&pd_conn2>; }; pcie at 290000 {
@@ -275,6 +296,7 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>; + samsung,power-domain = <&pd_pcie>; }; pcie at 2a0000 {
@@ -294,5 +316,6 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>; + samsung,power-domain = <&pd_pcie>; }; };
arch/arm/mach-exynos/Kconfig +1 -0
@@ -104,6 +104,7 @@ config SOC_EXYNOS5440 select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI select PINCTRL_EXYNOS5440 + select PM_GENERIC_DOMAINS if PM select PM_OPP help Enable EXYNOS5440 SoC support
arch/arm/mach-exynos/common.c +0 -4
@@ -296,10 +296,6 @@ void exynos5_restart(enum reboot_mode movoid __init exynos_init_late (void ) { -if (of_machine_is_compatible ("samsung,exynos5440" )) -/* to be supported later */ -return ; -exynos_pm_late_initcall (); }
arch/arm/mach-exynos/pm_domains.c +136 -2
168 lines not on this page · raw message
PATCH 1/1 ARM: EXYNOS: add power domains support for EXYNOS5440
(CCing the other DT maintainers, hence quoting binding in full)
Quoted 37 lines · Bartlomiej Zolnierkiewicz
On EXYNOS5440 power domains are handled in a different way than on the previous EXYNOS SoCs. Add support for them to EXYNOS
pm_domainsdriver. Then add device tree nodes for PCIe (controlling power for PCIe host controller) and Conn2 (controlling power for Ethernet, SATA and USB controllers) power domains toexynos5440.dtsi.Currently if runtime Power Management is enabled and the driver for devices under power domain is disabled then the power domain will be disabled by EXYNOS
pm_domainsdriver. To make more active use of power domains (dynamically enable and disabled them as needed) it is required to add runtime PM support to pci-exynos, stmmac,ahci_platform, ohci-exynos and ehci-s5p drivers (to be done later).Signed-off-by Bartlomiej Zolnierkiewicz <[email protected]>Signed-off-by Myungjoo Ham <[email protected]>Cc Tomasz Figa <[email protected]>Cc Stephen Warren <[email protected]>--- Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 33 ++ arch/arm/boot/dts/exynos5440.dtsi | 23 + arch/arm/mach-exynos/Kconfig | 1 arch/arm/mach-exynos/common.c | 4 arch/arm/mach-exynos/pm_domains.c | 138 +++++++++- 5 files changed, 190 insertions(+), 9 deletions(-)Index:
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
===================================================================Documentation/devicetree/bindings/arm/exynos/power_domain.txt +2
-1@@ -5,20 +5,47 @@ to gate power to one or more peripherals Required Properties: - compatible: should be one of the following. - * samsung,exynos4210-pd - for exynos4210 type power domain. + * samsung,exynos4210-pd - for Exynos4210 type power domain. + * samsung,exynos5440-pd - for Exynos5440 type power domain.
Documentation/devicetree/bindings/arm/exynos/power_domain.txt to gate power to one or more peripherals · line 18
Quoted 10 lines
Documentation/devicetree/bindings/arm/exynos/power_domain.txt +8
-1- reg: physical base address of the controller and length of memory mapped - region. + region (Exynos4210 type power domain) or bit offset in the control + register (Exynos5440 type power domain). + +Additional parent node must be created for Exynos5440 power domains with +the following required properties: +- compatible: samsung,exynos5440-power-domains, simple-bus +- reg: physical base address of the XMU controller and length of memory + mapped region
It's a little odd to describe the child nodes first. Given the 4210 and 5440 bindings work so differently, I'd suggest making separate binding files for the two; samsung,exynos4210-pd.txt and samsung,exynos5440-pd.txt.
The node being describe here clearly is not a simple-bus; the child nodes appear to have a specific need that their parent be compatible = "samsung,exynos5440-power-domains", hence they aren't the independent devices that simple-bus would usually contain.
Note that I only briefly reviewed the low-level structural aspects of the binding that I mentioned above; I haven't thought about the binding at a higher level of e.g. "does this binding conceptually make sense".
Quoted 108 lines
Documentation/devicetree/bindings/arm/exynos/power_domain.txt +20
-1Node of a device using power domains must have a samsung,power-domain property defined with a phandle to respective power domain. -Example: +Example for Exynos4210 compatible power domain: lcd0: power-domain-lcd0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x10>; }; +Example for Exynos5440 compatible power domains: + + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + Example of the node using power domain: node {Index:
b/arch/arm/boot/dts/exynos5440.dtsi
===================================================================arch/arm/boot/dts/exynos5440.dtsi +23
-0@@ -29,6 +29,23 @@ #clock-cells = <1>; }; + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + gic:interrupt-controller at 2E0000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;@@ -192,6 +209,7 @@ phy-mode = "sgmii"; clocks = <&clock 25>; clock-names = "stmmaceth"; + samsung,power-domain = <&pd_conn2>; }; amba {@@ -240,6 +258,7 @@ interrupts = <0 30 0>; clocks = <&clock 23>; clock-names = "sata"; + samsung,power-domain = <&pd_conn2>; }; ohci at 220000 {@@ -248,6 +267,7 @@ interrupts = <0 29 0>; clocks = <&clock 24>; clock-names = "usbhost"; + samsung,power-domain = <&pd_conn2>; }; ehci at 221000 {@@ -256,6 +276,7 @@ interrupts = <0 29 0>; clocks = <&clock 24>; clock-names = "usbhost"; + samsung,power-domain = <&pd_conn2>; }; pcie at 290000 {@@ -275,6 +296,7 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>; + samsung,power-domain = <&pd_pcie>; }; pcie at 2a0000 {@@ -294,5 +316,6 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>; + samsung,power-domain = <&pd_pcie>; }; };
PATCH 1/1 ARM: EXYNOS: add power domains support for EXYNOS5440
Quoted 55 lines · Stephen Warren
(CCing the other DT maintainers, hence quoting binding in full)
Quoted 37 lines · Bartlomiej Zolnierkiewicz
On EXYNOS5440 power domains are handled in a different way than on the previous EXYNOS SoCs. Add support for them to EXYNOS
pm_domainsdriver. Then add device tree nodes for PCIe (controlling power for PCIe host controller) and Conn2 (controlling power for Ethernet, SATA and USB controllers) power domains toexynos5440.dtsi.Currently if runtime Power Management is enabled and the driver for devices under power domain is disabled then the power domain will be disabled by EXYNOS
pm_domainsdriver. To make more active use of power domains (dynamically enable and disabled them as needed) it is required to add runtime PM support to pci-exynos, stmmac,ahci_platform, ohci-exynos and ehci-s5p drivers (to be done later).Signed-off-by Bartlomiej Zolnierkiewicz <[email protected]>Signed-off-by Myungjoo Ham <[email protected]>Cc Tomasz Figa <[email protected]>Cc Stephen Warren <[email protected]>--- Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 33 ++ arch/arm/boot/dts/exynos5440.dtsi | 23 + arch/arm/mach-exynos/Kconfig | 1 arch/arm/mach-exynos/common.c | 4 arch/arm/mach-exynos/pm_domains.c | 138 +++++++++- 5 files changed, 190 insertions(+), 9 deletions(-)Index:
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
===================================================================Documentation/devicetree/bindings/arm/exynos/power_domain.txt +2
-1@@ -5,20 +5,47 @@ to gate power to one or more peripherals Required Properties: - compatible: should be one of the following. - * samsung,exynos4210-pd - for exynos4210 type power domain. + * samsung,exynos4210-pd - for Exynos4210 type power domain. + * samsung,exynos5440-pd - for Exynos5440 type power domain.Documentation/devicetree/bindings/arm/exynos/power_domain.txt to gate power to one or more peripherals · line 18
Quoted 10 lines
Documentation/devicetree/bindings/arm/exynos/power_domain.txt +8
-1- reg: physical base address of the controller and length of memory mapped - region. + region (Exynos4210 type power domain) or bit offset in the control + register (Exynos5440 type power domain). + +Additional parent node must be created for Exynos5440 power domains with +the following required properties: +- compatible: samsung,exynos5440-power-domains, simple-bus +- reg: physical base address of the XMU controller and length of memory + mapped regionIt's a little odd to describe the child nodes first. Given the 4210 and 5440 bindings work so differently, I'd suggest making separate binding files for the two; samsung,exynos4210-pd.txt and samsung,exynos5440-pd.txt.
Quoted 4 lines
The node being describe here clearly is not a simple-bus; the child nodes appear to have a specific need that their parent be compatible = "samsung,exynos5440-power-domains", hence they aren't the independent devices that simple-bus would usually contain.
+1. This is most definitely not a simple-bus, the child nodes reg properties cdon't represent the same address space as the parent's reg property.
How much does the association of bit-offsets to power domains vary?
Quoted 4 lines
Note that I only briefly reviewed the low-level structural aspects of the binding that I mentioned above; I haven't thought about the binding at a higher level of e.g. "does this binding conceptually make sense".
This is unfortunately difficult to do :(
Quoted 60 lines
Quoted 60 lines
Documentation/devicetree/bindings/arm/exynos/power_domain.txt +20
-1Node of a device using power domains must have a samsung,power-domain property defined with a phandle to respective power domain. -Example: +Example for Exynos4210 compatible power domain: lcd0: power-domain-lcd0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x10>; }; +Example for Exynos5440 compatible power domains: + + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + Example of the node using power domain: node {Index:
b/arch/arm/boot/dts/exynos5440.dtsi
===================================================================arch/arm/boot/dts/exynos5440.dtsi +17
-0@@ -29,6 +29,23 @@ #clock-cells = <1>; }; + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + gic:interrupt-controller at 2E0000 {
Quoted 8 lines
arch/arm/boot/dts/exynos5440.dtsi line 213
Quoted 8 lines
arch/arm/boot/dts/exynos5440.dtsi +1
-0compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;@@ -192,6 +209,7 @@ phy-mode = "sgmii"; clocks = <&clock 25>; clock-names = "stmmaceth"; + samsung,power-domain = <&pd_conn2>; };
This feels like a clock style binding would fit better:
samsung,power-domain = <&pwr 7>;
But there may be a better, more general way of handling this. I'm not sure how this relates to regulators and so on, and how other vendors handle this stuff...
Thanks,
Mark.
Quoted 43 lines
Quoted 41 lines
arch/arm/boot/dts/exynos5440.dtsi +5
-0amba {@@ -240,6 +258,7 @@ interrupts = <0 30 0>; clocks = <&clock 23>; clock-names = "sata"; + samsung,power-domain = <&pd_conn2>; }; ohci at 220000 {@@ -248,6 +267,7 @@ interrupts = <0 29 0>; clocks = <&clock 24>; clock-names = "usbhost"; + samsung,power-domain = <&pd_conn2>; }; ehci at 221000 {@@ -256,6 +276,7 @@ interrupts = <0 29 0>; clocks = <&clock 24>; clock-names = "usbhost"; + samsung,power-domain = <&pd_conn2>; }; pcie at 290000 {@@ -275,6 +296,7 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>; + samsung,power-domain = <&pd_pcie>; }; pcie at 2a0000 {@@ -294,5 +316,6 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>; + samsung,power-domain = <&pd_pcie>; }; };
PATCH 1/1 ARM: EXYNOS: add power domains support for EXYNOS5440
Hi,
Quoted 47 lines · Mark Rutland
Quoted 46 lines · Stephen Warren
(CCing the other DT maintainers, hence quoting binding in full)
Quoted 43 lines · Bartlomiej Zolnierkiewicz
On EXYNOS5440 power domains are handled in a different way than on the previous EXYNOS SoCs. Add support for them to EXYNOS
pm_domainsdriver. Then add device tree nodes for PCIe (controlling power for PCIe host controller) and Conn2 (controlling power for Ethernet, SATA and USB controllers) power domains toexynos5440.dtsi.Currently if runtime Power Management is enabled and the driver for devices under power domain is disabled then the power domain will be disabled by EXYNOS
pm_domainsdriver. To make more active use of power domains (dynamically enable and disabled them as needed) it is required to add runtime PM support to pci-exynos, stmmac,ahci_platform, ohci-exynos and ehci-s5p drivers (to be done later).Signed-off-by Bartlomiej Zolnierkiewicz <[email protected]>Signed-off-by Myungjoo Ham <[email protected]>Cc Tomasz Figa <[email protected]>Cc Stephen Warren <[email protected]>--- Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 33 ++ arch/arm/boot/dts/exynos5440.dtsi | 23 + arch/arm/mach-exynos/Kconfig | 1 arch/arm/mach-exynos/common.c | 4 arch/arm/mach-exynos/pm_domains.c | 138 +++++++++- 5 files changed, 190 insertions(+), 9 deletions(-)Index:
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
===================================================================Documentation/devicetree/bindings/arm/exynos/power_domain.txt +6
-2@@ -5,20 +5,47 @@ to gate power to one or more peripherals Required Properties: - compatible: should be one of the following. - * samsung,exynos4210-pd - for exynos4210 type power domain. + * samsung,exynos4210-pd - for Exynos4210 type power domain. + * samsung,exynos5440-pd - for Exynos5440 type power domain. - reg: physical base address of the controller and length of memory mapped - region. + region (Exynos4210 type power domain) or bit offset in the control + register (Exynos5440 type power domain). + +Additional parent node must be created for Exynos5440 power domains with
Quoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/arm/exynos/power_domain.txt to gate power to one or more peripherals · line 18
Quoted 4 lines
Documentation/devicetree/bindings/arm/exynos/power_domain.txt +4
-0+the following required properties: +- compatible: samsung,exynos5440-power-domains, simple-bus +- reg: physical base address of the XMU controller and length of memory + mapped regionIt's a little odd to describe the child nodes first. Given the 4210 and 5440 bindings work so differently, I'd suggest making separate binding files for the two; samsung,exynos4210-pd.txt and samsung,exynos5440-pd.txt.
OK, I'll fix it.
Quoted 8 lines
Quoted 4 lines
The node being describe here clearly is not a simple-bus; the child nodes appear to have a specific need that their parent be compatible = "samsung,exynos5440-power-domains", hence they aren't the independent devices that simple-bus would usually contain.
+1. This is most definitely not a simple-bus, the child nodes reg properties cdon't represent the same address space as the parent's reg property.
What does in mean in the practice? What should I do instead?
Quoted 1 line
How much does the association of bit-offsets to power domains vary?
On EXYNOS5440 power domains are controlled by control and status registers which are shared among all power domains. On other EXYNOS SoCs there are separate control/status registers for each power domain.
Quoted 78 lines
Quoted 3 lines
Note that I only briefly reviewed the low-level structural aspects of the binding that I mentioned above; I haven't thought about the binding at a higher level of e.g. "does this binding conceptually make sense".
This is unfortunately difficult to do :(
Quoted 60 lines
Quoted 60 lines
Documentation/devicetree/bindings/arm/exynos/power_domain.txt +20
-1Node of a device using power domains must have a samsung,power-domain property defined with a phandle to respective power domain. -Example: +Example for Exynos4210 compatible power domain: lcd0: power-domain-lcd0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x10>; }; +Example for Exynos5440 compatible power domains: + + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + Example of the node using power domain: node {Index:
b/arch/arm/boot/dts/exynos5440.dtsi
===================================================================arch/arm/boot/dts/exynos5440.dtsi +17
-0@@ -29,6 +29,23 @@ #clock-cells = <1>; }; + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + gic:interrupt-controller at 2E0000 {Quoted 8 lines
arch/arm/boot/dts/exynos5440.dtsi line 213
Quoted 8 lines
arch/arm/boot/dts/exynos5440.dtsi +1
-0compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;@@ -192,6 +209,7 @@ phy-mode = "sgmii"; clocks = <&clock 25>; clock-names = "stmmaceth"; + samsung,power-domain = <&pd_conn2>; };This feels like a clock style binding would fit better:
samsung,power-domain = <&pwr 7>;
Quoted 3 lines
But there may be a better, more general way of handling this. I'm not sure how this relates to regulators and so on, and how other vendors handle this stuff...
Other vendors don't implement device tree for their power domains yet.
Also there is not much power domain users in the tree currently:
$ git grep pm_genpd_init arch/arm/mach-exynos/pm_domains.c: pm_genpd_init(&pd->pd, NULL, !on); arch/arm/mach-s3c64xx/pm.c: pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd, arch/arm/mach-s3c64xx/pm.c: pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false); arch/arm/mach-shmobile/pm-r8a7779.c: pm_genpd_init(genpd, NULL, false); arch/arm/mach-shmobile/pm-rmobile.c: pm_genpd_init(genpd, gov ? : &simple_qos_governor, false); drivers/base/power/domain.c: * pm_genpd_init - Initialize a generic I/O PM domain object. drivers/base/power/domain.c:void pm_genpd_init(struct generic_pm_domain *genpd, include/linux/pm_domain.h:extern void pm_genpd_init(struct generic_pm_domain *genpd, include/linux/pm_domain.h:static inline void pm_genpd_init(struct generic_pm_domain *genpd,
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
Quoted 44 lines
Thanks,
Mark.Quoted 41 lines
Quoted 41 lines
arch/arm/boot/dts/exynos5440.dtsi +5
-0amba {@@ -240,6 +258,7 @@ interrupts = <0 30 0>; clocks = <&clock 23>; clock-names = "sata"; + samsung,power-domain = <&pd_conn2>; }; ohci at 220000 {@@ -248,6 +267,7 @@ interrupts = <0 29 0>; clocks = <&clock 24>; clock-names = "usbhost"; + samsung,power-domain = <&pd_conn2>; }; ehci at 221000 {@@ -256,6 +276,7 @@ interrupts = <0 29 0>; clocks = <&clock 24>; clock-names = "usbhost"; + samsung,power-domain = <&pd_conn2>; }; pcie at 290000 {@@ -275,6 +296,7 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>; + samsung,power-domain = <&pd_pcie>; }; pcie at 2a0000 {@@ -294,5 +316,6 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>; + samsung,power-domain = <&pd_pcie>; }; };
PATCH 1/1 ARM: EXYNOS: add power domains support for EXYNOS5440
Quoted 67 lines · Bartlomiej Zolnierkiewicz
Hi,
Quoted 47 lines · Mark Rutland
Quoted 46 lines · Stephen Warren
(CCing the other DT maintainers, hence quoting binding in full)
Quoted 43 lines · Bartlomiej Zolnierkiewicz
On EXYNOS5440 power domains are handled in a different way than on the previous EXYNOS SoCs. Add support for them to EXYNOS
pm_domainsdriver. Then add device tree nodes for PCIe (controlling power for PCIe host controller) and Conn2 (controlling power for Ethernet, SATA and USB controllers) power domains toexynos5440.dtsi.Currently if runtime Power Management is enabled and the driver for devices under power domain is disabled then the power domain will be disabled by EXYNOS
pm_domainsdriver. To make more active use of power domains (dynamically enable and disabled them as needed) it is required to add runtime PM support to pci-exynos, stmmac,ahci_platform, ohci-exynos and ehci-s5p drivers (to be done later).Signed-off-by Bartlomiej Zolnierkiewicz <[email protected]>Signed-off-by Myungjoo Ham <[email protected]>Cc Tomasz Figa <[email protected]>Cc Stephen Warren <[email protected]>--- Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 33 ++ arch/arm/boot/dts/exynos5440.dtsi | 23 + arch/arm/mach-exynos/Kconfig | 1 arch/arm/mach-exynos/common.c | 4 arch/arm/mach-exynos/pm_domains.c | 138 +++++++++- 5 files changed, 190 insertions(+), 9 deletions(-)Index:
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
===================================================================Documentation/devicetree/bindings/arm/exynos/power_domain.txt +6
-2@@ -5,20 +5,47 @@ to gate power to one or more peripherals Required Properties: - compatible: should be one of the following. - * samsung,exynos4210-pd - for exynos4210 type power domain. + * samsung,exynos4210-pd - for Exynos4210 type power domain. + * samsung,exynos5440-pd - for Exynos5440 type power domain. - reg: physical base address of the controller and length of memory mapped - region. + region (Exynos4210 type power domain) or bit offset in the control + register (Exynos5440 type power domain). + +Additional parent node must be created for Exynos5440 power domains withQuoted 8 lines
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Documentation/devicetree/bindings/arm/exynos/power_domain.txt to gate power to one or more peripherals · line 18
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Documentation/devicetree/bindings/arm/exynos/power_domain.txt +4
-0+the following required properties: +- compatible: samsung,exynos5440-power-domains, simple-bus +- reg: physical base address of the XMU controller and length of memory + mapped regionIt's a little odd to describe the child nodes first. Given the 4210 and 5440 bindings work so differently, I'd suggest making separate binding files for the two; samsung,exynos4210-pd.txt and samsung,exynos5440-pd.txt.
OK, I'll fix it.
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The node being describe here clearly is not a simple-bus; the child nodes appear to have a specific need that their parent be compatible = "samsung,exynos5440-power-domains", hence they aren't the independent devices that simple-bus would usually contain.
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+1. This is most definitely not a simple-bus, the child nodes reg properties cdon't represent the same address space as the parent's reg property.
What does in mean in the practice? What should I do instead?
The driver for the parent nodes should probe for the child nodes via some mechanism. The "simple-bus" compatible property should be removed from the parent node as it's simply not true.
Simple-bus should only be used where the child nodes make sense and are useable on their own, regardless of the parent node.
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How much does the association of bit-offsets to power domains vary?
On EXYNOS5440 power domains are controlled by control and status registers which are shared among all power domains. On other EXYNOS SoCs there are separate control/status registers for each power domain.
Ok.
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Note that I only briefly reviewed the low-level structural aspects of the binding that I mentioned above; I haven't thought about the binding at a higher level of e.g. "does this binding conceptually make sense".
This is unfortunately difficult to do :(
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Documentation/devicetree/bindings/arm/exynos/power_domain.txt +20
-1Node of a device using power domains must have a samsung,power-domain property defined with a phandle to respective power domain. -Example: +Example for Exynos4210 compatible power domain: lcd0: power-domain-lcd0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x10>; }; +Example for Exynos5440 compatible power domains: + + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + Example of the node using power domain: node {Index:
b/arch/arm/boot/dts/exynos5440.dtsi
===================================================================arch/arm/boot/dts/exynos5440.dtsi +17
-0@@ -29,6 +29,23 @@ #clock-cells = <1>; }; + power-domains at 00160000 { + compatible = "samsung,exynos5440-power-domains", "simple-bus"; + reg = <0x00160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: pcie-power-domain at 6 { + compatible = "samsung,exynos5440-pd"; + reg = <6>; + }; + + pd_conn2: conn2-power-domain at 7 { + compatible = "samsung,exynos5440-pd"; + reg = <7>; + }; + }; + gic:interrupt-controller at 2E0000 {Quoted 8 lines
arch/arm/boot/dts/exynos5440.dtsi line 213
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arch/arm/boot/dts/exynos5440.dtsi +1
-0compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;@@ -192,6 +209,7 @@ phy-mode = "sgmii"; clocks = <&clock 25>; clock-names = "stmmaceth"; + samsung,power-domain = <&pd_conn2>; };This feels like a clock style binding would fit better:
samsung,power-domain = <&pwr 7>;Quoted 3 lines
But there may be a better, more general way of handling this. I'm not sure how this relates to regulators and so on, and how other vendors handle this stuff...
Other vendors don't implement device tree for their power domains yet.
Also there is not much power domain users in the tree currently:
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$ git grep pm_genpd_init arch/arm/mach-exynos/pm_domains.c: pm_genpd_init(&pd->pd, NULL, !on); arch/arm/mach-s3c64xx/pm.c: pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd, arch/arm/mach-s3c64xx/pm.c: pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false); arch/arm/mach-shmobile/pm-r8a7779.c: pm_genpd_init(genpd, NULL, false); arch/arm/mach-shmobile/pm-rmobile.c: pm_genpd_init(genpd, gov ? : &simple_qos_governor, false); drivers/base/power/domain.c: * pm_genpd_init - Initialize a generic I/O PM domain object. drivers/base/power/domain.c:void pm_genpd_init(struct generic_pm_domain *genpd, include/linux/pm_domain.h:extern void pm_genpd_init(struct generic_pm_domain *genpd, include/linux/pm_domain.h:static inline void pm_genpd_init(struct generic_pm_domain *genpd,
Ok. How do you feel about for clock style binding I suggested above? Is there any information you might need to membed in teh child *-pd nodes in future?
Thanks,
Mark.