ARM: OMAP4: Add OMAP4470 support

PATCH New Taras Kondratiuk 3 participants 9 messages Aug 6, 2013 – Aug 28, 2013 Arm (32-bit)

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Taras Kondratiuk

author

2013-08-06 12:18 UTC #0 lore raw

cover ARM: OMAP4: Add OMAP4470 support

This series adds OMAP4470 support. It initializes clocks, voltages and EMIF. This is enough to boot SLP, but U-Boot will try to start battery charging on TWL6032 and will crash, because registers GPADC registers are different.

To get fully functional system Oleg's TWL6032 series [1] is needed on top of this one.

Tested on TI Blaze Tablet2 board.

Based on v2013.07+ commit f53932a "dts/Makefile: pass -undef -D__DTS__ to cpp"

[1] http://www.mail-archive.com/u-boot at lists.denx.de/msg118364.html

Lubomir Popov (1):
ARM: OMAP4470: Add Elpida EDB8164B3PF memory configuration

Taras Kondratiuk (3):
ARM: OMAP4470: Add OMAP4470 identification
ARM: OMAP4470: Add voltage and dpll data
ARM: OMAP4460: sdp: Limit TPS mux config to 4460

 arch/arm/cpu/armv7/omap4/hw_data.c      |   36 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/hwinit.c       |    3 +++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c |   41 +++++++++++++++++++++++++------
 arch/arm/include/asm/arch-omap4/clock.h |    7 +++++-
 arch/arm/include/asm/arch-omap4/omap.h  |    1 +
 arch/arm/include/asm/omap_common.h      |    1 +
 board/ti/sdp4430/sdp.c                  |    3 ++-
 7 files changed, 83 insertions(+), 9 deletions(-)

Signature · 1 line

1.7.9.5

Taras Kondratiuk

author

2013-08-06 12:18 UTC #1 lore raw

PATCH 1/4 ARM: OMAP4470: Add OMAP4470 identification

Signed-off-by Taras Kondratiuk <[email protected]>

---
 arch/arm/cpu/armv7/omap4/hwinit.c      |    3 +++
 arch/arm/include/asm/arch-omap4/omap.h |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 3 files changed, 5 insertions(+)

arch/arm/cpu/armv7/omap4/hwinit.c +3 -0

index 4da0fc0..b0598a0 100644
@@ -138,6 +138,9 @@ void init_omap_revision(void)
 		break;
 	case MIDR_CORTEX_A9_R2P10:
 		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP4470_CONTROL_ID_CODE_ES1_0:
+			*omap_si_rev = OMAP4470_ES1_0;
+			break;
 		case OMAP4460_CONTROL_ID_CODE_ES1_1:
 			*omap_si_rev = OMAP4460_ES1_1;
 			break;

arch/arm/include/asm/arch-omap4/omap.h +1 -0

index 3823a37..9129c0d 100644
@@ -41,6 +41,7 @@
 #define OMAP4_CONTROL_ID_CODE_ES2_3	0x6B95C02F
 #define OMAP4460_CONTROL_ID_CODE_ES1_0	0x0B94E02F
 #define OMAP4460_CONTROL_ID_CODE_ES1_1	0x2B94E02F
+#define OMAP4470_CONTROL_ID_CODE_ES1_0	0x0B97502F
 
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)

arch/arm/include/asm/omap_common.h +1 -0

index b56e949..d6ff030 100644
@@ -612,6 +612,7 @@ static inline u8 is_omap54xx(void)
 #define OMAP4430_ES2_3	0x44300230
 #define OMAP4460_ES1_0	0x44600100
 #define OMAP4460_ES1_1	0x44600110
+#define OMAP4470_ES1_0	0x44700100
 
 /* omap5 */
 #define OMAP5430_SILICON_ID_INVALID	0

Signature · 1 line

1.7.9.5

Taras Kondratiuk

author

2013-08-06 12:18 UTC #2 lore raw

PATCH 2/4 ARM: OMAP4470: Add voltage and dpll data

In reply to Taras Kondratiuk

OMAP4470 reference design uses TWL6032 PMIC
with a following connection scheme:
VDD_CORE = TWL6032 SMPS2
VDD_MPU = TWL6032 SMPS1
VDD_IVA = TWL6032 SMPS5

Set voltage and frequency values according to OMAP4470 Data Manual Operating Condition Addendum v0.7

Signed-off-by Taras Kondratiuk <[email protected]>

---
 arch/arm/cpu/armv7/omap4/hw_data.c      |   36 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/clock.h |    7 +++++-
 2 files changed, 42 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/omap4/hw_data.c +36 -0

index 310df5a..6a225c8 100644
@@ -50,6 +50,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
 /*
  * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
  * OMAP4430 OPP_TURBO frequency
+ * OMAP4470 OPP_NOM frequency
  */
 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
 	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */

@@ -76,6 +77,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
 };
 
 /* OMAP4460 OPP_NOM frequency */
+/* OMAP4470 OPP_NOM (Low Power) frequency */
 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
 	{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
 	{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */

@@ -198,6 +200,20 @@ struct dplls omap4460_dplls = {
 	.ddr = NULL
 };
 
+struct dplls omap4470_dplls = {
+	.mpu = mpu_dpll_params_1600mhz,
+	.core = core_dpll_params_1600mhz,
+	.per = per_dpll_params_1536mhz,
+	.iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
 struct pmic_data twl6030_4430es1 = {
 	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
 	.step = 12660, /* 12.66 mV represented in uV */

@@ -208,6 +224,7 @@ struct pmic_data twl6030_4430es1 = {
 	.pmic_write	= omap_vc_bypass_send_value,
 };
 
+/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
 struct pmic_data twl6030 = {
 	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
 	.step = 12660, /* 12.66 mV represented in uV */

@@ -271,6 +288,20 @@ struct vcores_data omap4460_volts = {
 	.mm.pmic = &twl6030,
 };
 
+struct vcores_data omap4470_volts = {
+	.mpu.value = 1200,
+	.mpu.addr = SMPS_REG_ADDR_SMPS1,
+	.mpu.pmic = &twl6030,
+
+	.core.value = 1126,
+	.core.addr = SMPS_REG_ADDR_SMPS1,
+	.core.pmic = &twl6030,
+
+	.mm.value = 1137,
+	.mm.addr = SMPS_REG_ADDR_SMPS1,
+	.mm.pmic = &twl6030,
+};
+
 /*
  * Enable essential clock domains, modules and
  * do some additional special settings needed

@@ -476,6 +507,11 @@ void hw_data_init(void)
 	*omap_vcores = &omap4460_volts;
 	break;
 
+	case OMAP4470_ES1_0:
+	*dplls_data = &omap4470_dplls;
+	*omap_vcores = &omap4470_volts;
+	break;
+
 	default:
 		printf("\n INVALID OMAP REVISION ");
 	}

arch/arm/include/asm/arch-omap4/clock.h +6 -1

index b2e03d6..f3a682a 100644
@@ -149,11 +149,16 @@
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
 
-/* SMPS */
+/* PMIC */
 #define SMPS_I2C_SLAVE_ADDR	0x12
+/* TWL6030 SMPS */
 #define SMPS_REG_ADDR_VCORE1	0x55
 #define SMPS_REG_ADDR_VCORE2	0x5B
 #define SMPS_REG_ADDR_VCORE3	0x61
+/* TWL6032 SMPS */
+#define SMPS_REG_ADDR_SMPS1	0x55
+#define SMPS_REG_ADDR_SMPS2	0x5B
+#define SMPS_REG_ADDR_SMPS5	0x49
 
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000

Signature · 1 line

1.7.9.5

Taras Kondratiuk

author

2013-08-06 12:18 UTC #3 lore raw

PATCH 3/4 ARM: OMAP4470: Add Elpida EDB8164B3PF memory configuration

In reply to Taras Kondratiuk

From: Lubomir Popov <[email protected]>

OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. This memory has 4Gb x 2CS = 8Gb configuration.
Add configuration for runtime calculation and precalculated cases.

Patch is based on a draft Lubomir's patch [1].

[1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html

Signed-off-by Lubomir Popov <[email protected]>

[taras at ti.com: cleaned up patch and fixed precalculated values]

Signed-off-by Taras Kondratiuk <[email protected]>

---
 arch/arm/cpu/armv7/omap4/sdram_elpida.c |   41 +++++++++++++++++++++++++------
 1 file changed, 34 insertions(+), 7 deletions(-)

arch/arm/cpu/armv7/omap4/sdram_elpida.c +34 -7

index d76dde7..67a7926 100644
@@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
 	.emif_ddr_phy_ctlr_1		= 0x049ff418
 };
 
+const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
+	.sdram_config_init		= 0x80800eb2,
+	.sdram_config			= 0x80801ab2,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3215,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
 	.sdram_config_init		= 0x80000eb9,
 	.sdram_config			= 0x80001ab9,

@@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 		*regs = &emif_regs_elpida_380_mhz_1cs;
 	else if (omap4_rev == OMAP4430_ES2_0)
 		*regs = &emif_regs_elpida_200_mhz_2cs;
-	else
+	else if (omap4_rev < OMAP4470_ES1_0)
 		*regs = &emif_regs_elpida_400_mhz_2cs;
+	else
+		*regs = &emif_regs_elpida_400_mhz_1cs;
 }
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 	__attribute__((weak, alias("emif_get_reg_dump_sdp")));

@@ -138,20 +154,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = {
 	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
 };
 
+static const struct lpddr2_device_details elpida_4G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_4Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
 			struct lpddr2_device_details *lpddr2_dev_details)
 {
 	u32 omap_rev = omap_revision();
 
 	/* EMIF1 & EMIF2 have identical configuration */
-	if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
-		/* Nothing connected on CS1 for ES1.0 */
+	if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
+		&& (cs == CS1)) {
+		/* Nothing connected on CS1 for 4430/4470 ES1.0 */
 		return NULL;
-	} else {
-		/* In all other cases Elpida 2G device */
+	} else if (omap_rev < OMAP4470_ES1_0) {
+		/* In all other 4430/4460 cases Elpida 2G device */
 		*lpddr2_dev_details = elpida_2G_S4_details;
-		return lpddr2_dev_details;
+	} else {
+		/* 4470: 4G device */
+		*lpddr2_dev_details = elpida_4G_S4_details;
 	}
+	return lpddr2_dev_details;
 }
 
 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,

@@ -265,7 +292,7 @@ void emif_get_device_timings_sdp(u32 emif_nr,
 	/* Identical devices on EMIF1 & EMIF2 */
 	*cs0_device_timings = &elpida_2G_S4_timings;
 
-	if (omap_rev == OMAP4430_ES1_0)
+	if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
 		*cs1_device_timings = NULL;
 	else
 		*cs1_device_timings = &elpida_2G_S4_timings;

Signature · 1 line

1.7.9.5

Lokesh Vutla

2013-08-06 14:21 UTC #4 lore raw

PATCH 3/4 ARM: OMAP4470: Add Elpida EDB8164B3PF memory configuration

Hi Taras,

Quoted 9 lines · Taras Kondratiuk

From: Lubomir Popov <[email protected]>
OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. This memory has 4Gb x 2CS = 8Gb configuration.
Add configuration for runtime calculation and precalculated cases.
Patch is based on a draft Lubomir's patch [1].
[1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html

Just curious to know, Have you tried SDRAM_AUTO_DETECTION ? Rest looks fine to me.

Thanks and regards,
Lokesh

Quoted 4 lines

Signed-off-by Lubomir Popov <[email protected]>
[taras at ti.com: cleaned up patch and fixed precalculated values]
Signed-off-by Taras Kondratiuk <[email protected]>

@@ -138,6 +138,9 @@ void init_omap_revision(void)
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4470_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP4470_ES1_0;
+ break;
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = OMAP4460_ES1_1; break;
@@ -138,6 +138,9 @@ void init_omap_revision(void)
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4470_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP4470_ES1_0;
+ break;
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = OMAP4460_ES1_1; break;

Quoted 42 lines

---
 arch/arm/cpu/armv7/omap4/sdram_elpida.c |   41 +++++++++++++++++++++++++------
 1 file changed, 34 insertions(+), 7 deletions(-)

arch/arm/cpu/armv7/omap4/sdram_elpida.c +17 -1

index d76dde7..67a7926 100644
@@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
 	.emif_ddr_phy_ctlr_1		= 0x049ff418
 };
 
+const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
+	.sdram_config_init		= 0x80800eb2,
+	.sdram_config			= 0x80801ab2,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3215,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
 	.sdram_config_init		= 0x80000eb9,
 	.sdram_config			= 0x80001ab9,

@@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 		*regs = &emif_regs_elpida_380_mhz_1cs;
 	else if (omap4_rev == OMAP4430_ES2_0)
 		*regs = &emif_regs_elpida_200_mhz_2cs;
-	else
+	else if (omap4_rev < OMAP4470_ES1_0)
 		*regs = &emif_regs_elpida_400_mhz_2cs;
+	else
+		*regs = &emif_regs_elpida_400_mhz_1cs;
 }
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 	__attribute__((weak, alias("emif_get_reg_dump_sdp")));

arch/arm/cpu/armv7/omap4/sdram_elpida.c static const struct lpddr2_device_details elpida_2G_S4_details = { · line 159

Quoted 6 lines

arch/arm/cpu/armv7/omap4/sdram_elpida.c +3 -0

@@ -138,20 +154,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = {
 	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
 };
 
+static const struct lpddr2_device_details elpida_4G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_4Gb,

Quoted 40 lines

arch/arm/cpu/armv7/omap4/sdram_elpida.c +14 -6

+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
 			struct lpddr2_device_details *lpddr2_dev_details)
 {
 	u32 omap_rev = omap_revision();
 
 	/* EMIF1 & EMIF2 have identical configuration */
-	if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
-		/* Nothing connected on CS1 for ES1.0 */
+	if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
+		&& (cs == CS1)) {
+		/* Nothing connected on CS1 for 4430/4470 ES1.0 */
 		return NULL;
-	} else {
-		/* In all other cases Elpida 2G device */
+	} else if (omap_rev < OMAP4470_ES1_0) {
+		/* In all other 4430/4460 cases Elpida 2G device */
 		*lpddr2_dev_details = elpida_2G_S4_details;
-		return lpddr2_dev_details;
+	} else {
+		/* 4470: 4G device */
+		*lpddr2_dev_details = elpida_4G_S4_details;
 	}
+	return lpddr2_dev_details;
 }
 
 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,

@@ -265,7 +292,7 @@ void emif_get_device_timings_sdp(u32 emif_nr,
 	/* Identical devices on EMIF1 & EMIF2 */
 	*cs0_device_timings = &elpida_2G_S4_timings;
 
-	if (omap_rev == OMAP4430_ES1_0)
+	if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
 		*cs1_device_timings = NULL;
 	else
 		*cs1_device_timings = &elpida_2G_S4_timings;

Taras Kondratiuk

author

2013-08-06 15:57 UTC #5 lore raw

PATCH 3/4 ARM: OMAP4470: Add Elpida EDB8164B3PF memory configuration

Quoted 8 lines · Lokesh Vutla

Hi Taras,
Quoted 6 lines · Taras Kondratiuk
From: Lubomir Popov <[email protected]>
OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. This memory has 4Gb x 2CS = 8Gb configuration.
Add configuration for runtime calculation and precalculated cases.

Quoted 5 lines

Quoted 3 lines
Patch is based on a draft Lubomir's patch [1].
[1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html
Just curious to know, Have you tried SDRAM_AUTO_DETECTION ? Rest looks fine to me.

If you mean SYS_AUTOMATIC_SDRAM_DETECTION then yes I've tried it and it works.
The only minor issue is that detection is called twice during boot:
for dmm_init() and for do_sdram_init().

In case you need additional details I've put boot log with debug enabled below.

U-Boot SPL 2013.07-00116-gd7325e5-dirty (Aug 06 2013 - 18:20:56) OMAP4470 ES1.0

Quoted 1 line

Quoted 1 line
sdram_init()

in_sdram = 0
get_mr: EMIF1 cs 0 mr 00000000 val 0x0
get_mr: EMIF1 cs 0 mr 00000004 val 0x3
get_mr: EMIF1 cs 0 mr 00000005 val 0x3
get_mr: EMIF1 cs 0 mr 00000006 val 0x0
get_mr: EMIF1 cs 0 mr 00000007 val 0x0
get_mr: EMIF1 cs 0 mr 00000008 val 0x18
EMIF1 CS0 Elpida LPDDR2-S4 512 MB
get_mr: EMIF1 cs 1 mr 80000000 val 0x3
get_mr: EMIF2 cs 0 mr 00000000 val 0x0
get_mr: EMIF2 cs 0 mr 00000004 val 0x3
get_mr: EMIF2 cs 0 mr 00000005 val 0x3
get_mr: EMIF2 cs 0 mr 00000006 val 0x0
get_mr: EMIF2 cs 0 mr 00000007 val 0x0
get_mr: EMIF2 cs 0 mr 00000008 val 0x18
EMIF2 CS0 Elpida LPDDR2-S4 512 MB
get_mr: EMIF2 cs 1 mr 80000000 val 0x3 emif1_size 0x20000000 emif2_size 0x20000000

Quoted 1 line

Quoted 1 line
do_sdram_init() 4c000000

get_mr: EMIF1 cs 0 mr 00000000 val 0x0
get_mr: EMIF1 cs 0 mr 00000004 val 0x3
get_mr: EMIF1 cs 0 mr 00000005 val 0x3
get_mr: EMIF1 cs 0 mr 00000006 val 0x0
get_mr: EMIF1 cs 0 mr 00000007 val 0x0
get_mr: EMIF1 cs 0 mr 00000008 val 0x18
EMIF1 CS0 Elpida LPDDR2-S4 512 MB
get_mr: EMIF1 cs 1 mr 80000000 val 0x3
emif: timings table: 400000000
emif: addressing table index 6 regs->sdram_config_init - 0x80000eb2 regs->sdram_config - 0x80001ab2 regs->ref_ctrl - 0x00000618 regs->sdram_tim1 - 0x10eb0662 regs->sdram_tim2 - 0x20370dd2 regs->sdram_tim3 - 0x00b1c33f regs->read_idle_ctrl - 0x000501ff regs->temp_alert_config - 0x58016893 regs->zq_config - 0x500b3214 regs->emif_ddr_phy_ctlr_1 - 0x049ff418 regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5
get_mr: EMIF1 cs 0 mr 00000000 val 0x0 <<do_sdram_init() 4c000000

Quoted 1 line

Quoted 1 line
do_sdram_init() 4d000000

get_mr: EMIF2 cs 0 mr 00000000 val 0x0
get_mr: EMIF2 cs 0 mr 00000004 val 0x3
get_mr: EMIF2 cs 0 mr 00000005 val 0x3
get_mr: EMIF2 cs 0 mr 00000006 val 0x0
get_mr: EMIF2 cs 0 mr 00000007 val 0x0
get_mr: EMIF2 cs 0 mr 00000008 val 0x18
EMIF2 CS0 Elpida LPDDR2-S4 512 MB
get_mr: EMIF2 cs 1 mr 80000000 val 0x3
emif: timings table: 400000000
emif: addressing table index 6 regs->sdram_config_init - 0x80000eb2 regs->sdram_config - 0x80001ab2 regs->ref_ctrl - 0x00000618 regs->sdram_tim1 - 0x10eb0662 regs->sdram_tim2 - 0x20370dd2 regs->sdram_tim3 - 0x00b1c33f regs->read_idle_ctrl - 0x000501ff regs->temp_alert_config - 0x58016893 regs->zq_config - 0x500b3214 regs->emif_ddr_phy_ctlr_1 - 0x049ff418 regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5
get_mr: EMIF2 cs 0 mr 00000000 val 0x0 <<do_sdram_init() 4d000000 get_ram_size() successful<<sdram_init() OMAP SD/MMC: 0
reading u-boot.img
reading u-boot.img

Signature · 2 lines

BR
Taras Kondratiuk | GlobalLogic

Lokesh Vutla

2013-08-06 16:31 UTC #6 lore raw

PATCH 3/4 ARM: OMAP4470: Add Elpida EDB8164B3PF memory configuration

Hi,

Quoted 9 lines · Taras Kondratiuk

Quoted 8 lines · Lokesh Vutla
Hi Taras,
Quoted 6 lines · Taras Kondratiuk
From: Lubomir Popov <[email protected]>
OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. This memory has 4Gb x 2CS = 8Gb configuration.
Add configuration for runtime calculation and precalculated cases.

Quoted 7 lines

Quoted 5 lines
Quoted 3 lines
Patch is based on a draft Lubomir's patch [1].
[1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html
Just curious to know, Have you tried SDRAM_AUTO_DETECTION ? Rest looks fine to me.
If you mean SYS_AUTOMATIC_SDRAM_DETECTION then yes I've tried it and it works.

Cool, thats fine...!!

Thanks and regards,
Lokesh

Quoted 79 lines

The only minor issue is that detection is called twice during boot:
for dmm_init() and for do_sdram_init().
In case you need additional details I've put boot log with debug enabled below.
U-Boot SPL 2013.07-00116-gd7325e5-dirty (Aug 06 2013 - 18:20:56) OMAP4470 ES1.0
Quoted 1 line
Quoted 1 line
sdram_init()
in_sdram = 0
get_mr: EMIF1 cs 0 mr 00000000 val 0x0
get_mr: EMIF1 cs 0 mr 00000004 val 0x3
get_mr: EMIF1 cs 0 mr 00000005 val 0x3
get_mr: EMIF1 cs 0 mr 00000006 val 0x0
get_mr: EMIF1 cs 0 mr 00000007 val 0x0
get_mr: EMIF1 cs 0 mr 00000008 val 0x18
EMIF1 CS0 Elpida LPDDR2-S4 512 MB
get_mr: EMIF1 cs 1 mr 80000000 val 0x3
get_mr: EMIF2 cs 0 mr 00000000 val 0x0
get_mr: EMIF2 cs 0 mr 00000004 val 0x3
get_mr: EMIF2 cs 0 mr 00000005 val 0x3
get_mr: EMIF2 cs 0 mr 00000006 val 0x0
get_mr: EMIF2 cs 0 mr 00000007 val 0x0
get_mr: EMIF2 cs 0 mr 00000008 val 0x18
EMIF2 CS0 Elpida LPDDR2-S4 512 MB
get_mr: EMIF2 cs 1 mr 80000000 val 0x3 emif1_size 0x20000000 emif2_size 0x20000000
Quoted 1 line
Quoted 1 line
do_sdram_init() 4c000000
get_mr: EMIF1 cs 0 mr 00000000 val 0x0
get_mr: EMIF1 cs 0 mr 00000004 val 0x3
get_mr: EMIF1 cs 0 mr 00000005 val 0x3
get_mr: EMIF1 cs 0 mr 00000006 val 0x0
get_mr: EMIF1 cs 0 mr 00000007 val 0x0
get_mr: EMIF1 cs 0 mr 00000008 val 0x18
EMIF1 CS0 Elpida LPDDR2-S4 512 MB
get_mr: EMIF1 cs 1 mr 80000000 val 0x3
emif: timings table: 400000000
emif: addressing table index 6 regs->sdram_config_init - 0x80000eb2 regs->sdram_config - 0x80001ab2 regs->ref_ctrl - 0x00000618 regs->sdram_tim1 - 0x10eb0662 regs->sdram_tim2 - 0x20370dd2 regs->sdram_tim3 - 0x00b1c33f regs->read_idle_ctrl - 0x000501ff regs->temp_alert_config - 0x58016893 regs->zq_config - 0x500b3214 regs->emif_ddr_phy_ctlr_1 - 0x049ff418 regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5
get_mr: EMIF1 cs 0 mr 00000000 val 0x0 <<do_sdram_init() 4c000000
Quoted 1 line
Quoted 1 line
do_sdram_init() 4d000000
get_mr: EMIF2 cs 0 mr 00000000 val 0x0
get_mr: EMIF2 cs 0 mr 00000004 val 0x3
get_mr: EMIF2 cs 0 mr 00000005 val 0x3
get_mr: EMIF2 cs 0 mr 00000006 val 0x0
get_mr: EMIF2 cs 0 mr 00000007 val 0x0
get_mr: EMIF2 cs 0 mr 00000008 val 0x18
EMIF2 CS0 Elpida LPDDR2-S4 512 MB
get_mr: EMIF2 cs 1 mr 80000000 val 0x3
emif: timings table: 400000000
emif: addressing table index 6 regs->sdram_config_init - 0x80000eb2 regs->sdram_config - 0x80001ab2 regs->ref_ctrl - 0x00000618 regs->sdram_tim1 - 0x10eb0662 regs->sdram_tim2 - 0x20370dd2 regs->sdram_tim3 - 0x00b1c33f regs->read_idle_ctrl - 0x000501ff regs->temp_alert_config - 0x58016893 regs->zq_config - 0x500b3214 regs->emif_ddr_phy_ctlr_1 - 0x049ff418 regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5
get_mr: EMIF2 cs 0 mr 00000000 val 0x0 <<do_sdram_init() 4d000000 get_ram_size() successful<<sdram_init() OMAP SD/MMC: 0
reading u-boot.img
reading u-boot.img

Taras Kondratiuk

author

2013-08-06 12:18 UTC #7 lore raw

PATCH 4/4 ARM: OMAP4460: sdp: Limit TPS mux config to 4460

In reply to Taras Kondratiuk

TPS mux config is 4460 specific, so it should be limited to 4460 only.

Signed-off-by Taras Kondratiuk <[email protected]>

---
 board/ti/sdp4430/sdp.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

board/ti/sdp4430/sdp.c +2 -1

index 25daaa9..0479a56 100644
@@ -66,7 +66,8 @@ void set_muxconf_regs_essential(void)
 		   sizeof(wkup_padconf_array_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	if (omap_revision() >= OMAP4460_ES1_0)
+	if ((omap_revision() >= OMAP4460_ES1_0) &&
+			(omap_revision() < OMAP4470_ES1_0))
 		do_set_mux((*ctrl)->control_padconf_wkup_base,
 				 wkup_padconf_array_essential_4460,
 				 sizeof(wkup_padconf_array_essential_4460) /

Signature · 1 line

1.7.9.5

Tom Rini

2013-08-28 18:25 UTC #8 lore raw

cover ARM: OMAP4: Add OMAP4470 support

In reply to Taras Kondratiuk

Quoted 21 lines · Taras Kondratiuk

This series adds OMAP4470 support. It initializes clocks, voltages and EMIF. This is enough to boot SLP, but U-Boot will try to start battery charging on TWL6032 and will crash, because registers GPADC registers are different.
To get fully functional system Oleg's TWL6032 series [1] is needed on top of this one.
Tested on TI Blaze Tablet2 board.
Based on v2013.07+ commit f53932a "dts/Makefile: pass -undef -D__DTS__ to cpp"
[1] http://www.mail-archive.com/u-boot at lists.denx.de/msg118364.html
Lubomir Popov (1):
ARM: OMAP4470: Add Elpida EDB8164B3PF memory configuration
Taras Kondratiuk (3):
ARM: OMAP4470: Add OMAP4470 identification
ARM: OMAP4470: Add voltage and dpll data
ARM: OMAP4460: sdp: Limit TPS mux config to 4460

Quoted 8 lines

 arch/arm/cpu/armv7/omap4/hw_data.c      |   36 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/hwinit.c       |    3 +++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c |   41 +++++++++++++++++++++++++------
 arch/arm/include/asm/arch-omap4/clock.h |    7 +++++-
 arch/arm/include/asm/arch-omap4/omap.h  |    1 +
 arch/arm/include/asm/omap_common.h      |    1 +
 board/ti/sdp4430/sdp.c                  |    3 ++-
 7 files changed, 83 insertions(+), 9 deletions(-)

Applied to u-boot-ti/master, thanks!

Signature · 8 lines

Tom
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