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ppc4xx: Remove support for PPC405CR CPUs

PATCH New Matthias Fuchs 2 participants 2 messages Aug 7, 2013 – Aug 20, 2013

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PowerPC Generic include/asm header files
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Matthias Fuchs

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PATCH 1/1 ppc4xx: Remove support for PPC405CR CPUs

This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.

Signed-off-by Matthias Fuchs <[email protected]>
---
 arch/powerpc/cpu/ppc4xx/4xx_uart.c    |   10 ++--
 arch/powerpc/cpu/ppc4xx/cpu.c         |   18 +------
 arch/powerpc/cpu/ppc4xx/cpu_init.c    |    2 +-
 arch/powerpc/cpu/ppc4xx/speed.c       |    4 +-
 arch/powerpc/cpu/ppc4xx/start.S       |    4 +-
 arch/powerpc/include/asm/ppc405cr.h   |   92 ---------------------------------
 arch/powerpc/include/asm/ppc4xx-ebc.h |    6 +--
 arch/powerpc/include/asm/ppc4xx.h     |    4 --
 arch/powerpc/include/asm/processor.h  |    3 --
 arch/powerpc/include/asm/u-boot.h     |    1 -
 common/cmd_bdinfo.c                   |    6 +--
 include/asm-generic/u-boot.h          |    1 -
 include/serial.h                      |    2 +-
 13 files changed, 18 insertions(+), 135 deletions(-)
 delete mode 100644 arch/powerpc/include/asm/ppc405cr.h
arch/powerpc/cpu/ppc4xx/4xx_uart.c +5 -5
index 1ad19ab..da5bda8 100644
@@ -40,7 +40,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if defined(CONFIG_405GP) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || defined(CONFIG_440)
 

@@ -91,7 +91,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UDIV_SUBTRACT	0
 #define UART0_SDR	SDR0_UART0
 #define UART1_SDR	SDR0_UART1
-#else /* CONFIG_405GP || CONFIG_405CR */
+#else /* CONFIG_405GP */
 #define CR0_MASK        0x00001fff
 #define CR0_EXTCLK_ENA  0x000000c0
 #define CR0_UDIV_POS    1

@@ -196,7 +196,7 @@ int get_serial_clock(void)
 	 * Let's handle this in some #ifdef's for the SoC's.
 	 */
 
-#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
+#if defined(CONFIG_405GP)
 	reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	clk = CONFIG_SYS_EXT_SERIAL_CLOCK;

@@ -223,7 +223,7 @@ int get_serial_clock(void)
 #else
 	clk = CONFIG_SYS_BASE_BAUD * 16;
 #endif
-#endif /* CONFIG_405CR */
+#endif
 
 #if defined(CONFIG_405EP)
 	{

@@ -288,4 +288,4 @@ int get_serial_clock(void)
 
 	return clk;
 }
-#endif	/* CONFIG_405GP || CONFIG_405CR */
+#endif	/* CONFIG_405GP */
arch/powerpc/cpu/ppc4xx/cpu.c +1 -17
index fe05098..5cebafd 100644
@@ -320,25 +320,9 @@ int checkcpu (void)
 		puts("405GP Rev. D");
 		break;
 
-#ifdef CONFIG_405GP
-	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
+	case PVR_405GP_RE:
 		puts("405GP Rev. E");
 		break;
-#endif
-
-	case PVR_405CR_RA:
-		puts("405CR Rev. A");
-		break;
-
-	case PVR_405CR_RB:
-		puts("405CR Rev. B");
-		break;
-
-#ifdef CONFIG_405CR
-	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
-		puts("405CR Rev. C");
-		break;
-#endif
 
 	case PVR_405GPR_RB:
 		puts("405GPr Rev. B");
arch/powerpc/cpu/ppc4xx/cpu_init.c +1 -1
index d53d882..d465dcd 100644
@@ -326,7 +326,7 @@ cpu_init_f (void)
 	 * External Bus Controller (EBC) Setup
 	 */
 #if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
-#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if (defined(CONFIG_405GP) || \
      defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
      defined(CONFIG_405EX) || defined(CONFIG_405))
 	/*
arch/powerpc/cpu/ppc4xx/speed.c +2 -2
index 3345e73..7e077d5 100644
@@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
+#if defined(CONFIG_405GP)
 
 void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
 {

@@ -1184,7 +1184,7 @@ ulong get_bus_freq (ulong dummy)
 {
 	ulong val;
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if defined(CONFIG_405GP) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || defined(CONFIG_405) || \
     defined(CONFIG_440)
arch/powerpc/cpu/ppc4xx/start.S +2 -2
index 57ae1d3..1f1ddde 100644
@@ -833,7 +833,7 @@ _start:
 #endif /* CONFIG_440 */
 
 /*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if defined(CONFIG_405GP) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || defined(CONFIG_405)
 	/*----------------------------------------------------------------------- */

@@ -1103,7 +1103,7 @@ _start:
 
 #endif /* CONFIG_NAND_SPL */
 
-#endif	/* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
+#endif	/* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
 	/*----------------------------------------------------------------------- */
arch/powerpc/include/asm/ppc405cr.h deleted +0 -92

92 lines not on this page · raw message

arch/powerpc/include/asm/ppc4xx-ebc.h +3 -3
index 9eb50ee..32062fd 100644
@@ -14,12 +14,12 @@
  * Within this group there is a slight variation concerning the bit field
  * position of the EMPL and EMPH fields:
  */
-#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+#if defined(CONFIG_405GP) || \
     defined(CONFIG_405EP) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define CONFIG_EBC_PPC4xx_IBM_VER1
-#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+#if defined(CONFIG_405GP) || \
     defined(CONFIG_405EP)
 #define EBC_CFG_EMPH_POS	8
 #define EBC_CFG_EMPL_POS	6

@@ -32,7 +32,7 @@
 /*
  * Define the max number of EBC banks (chip selects)
  */
-#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+#if defined(CONFIG_405GP) || \
     defined(CONFIG_405EZ) || \
     defined(CONFIG_440GP) || defined(CONFIG_440GX)
 #define EBC_NUM_BANKS	8
arch/powerpc/include/asm/ppc4xx.h +0 -4
index 9f2a08b..bbbaa41 100644
@@ -27,10 +27,6 @@
 /*
  * Include SoC specific headers
  */
-#if defined(CONFIG_405CR)
-#include <asm/ppc405cr.h>
-#endif
-
 #if defined(CONFIG_405EP)
 #include <asm/ppc405ep.h>
 #endif
arch/powerpc/include/asm/processor.h +0 -3
index 56b22d8..0d3499c 100644
@@ -894,9 +894,6 @@
 #define PVR_405GP_RC	0x40110082
 #define PVR_405GP_RD	0x401100C4
 #define PVR_405GP_RE	0x40110145  /* same as pc405cr rev c */
-#define PVR_405CR_RA	0x40110041
-#define PVR_405CR_RB	0x401100C5
-#define PVR_405CR_RC	0x40110145  /* same as pc405gp rev e */
 #define PVR_405EP_RA	0x51210950
 #define PVR_405GPR_RB	0x50910951
 #define PVR_405EZ_RA	0x41511460
arch/powerpc/include/asm/u-boot.h +0 -1
index f17b146..5916f7c 100644
@@ -67,7 +67,6 @@ typedef struct bd_info {
 	unsigned int	bi_baudrate;	/* Console Baudrate */
 #if defined(CONFIG_405)   || \
     defined(CONFIG_405GP) || \
-    defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || \
     defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || \
common/cmd_bdinfo.c +3 -3
index af884b8..713de14 100644
@@ -92,7 +92,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_num("immr_base",		bd->bi_immr_base);
 #endif
 	print_num("bootflags",		bd->bi_bootflags);
-#if	defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
+#if	defined(CONFIG_405EP) || \
 	defined(CONFIG_405GP) || \
 	defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
 	defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \

@@ -106,7 +106,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
 	print_mhz("pci_busfreq",	bd->bi_pci_busfreq);
 #endif
-#else	/* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
+#else	/* ! CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
 #if defined(CONFIG_CPM2)
 	print_mhz("vco",		bd->bi_vco);
 	print_mhz("sccfreq",		bd->bi_sccfreq);

@@ -117,7 +117,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_mhz("cpmfreq",		bd->bi_cpmfreq);
 #endif
 	print_mhz("busfreq",		bd->bi_busfreq);
-#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
+#endif /* CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
 
 #ifdef CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
include/asm-generic/u-boot.h +0 -1
index 29e0438..4387201 100644
@@ -69,7 +69,6 @@ typedef struct bd_info {
 	unsigned int	bi_baudrate;	/* Console Baudrate */
 #if defined(CONFIG_405)   || \
 		defined(CONFIG_405GP) || \
-		defined(CONFIG_405CR) || \
 		defined(CONFIG_405EP) || \
 		defined(CONFIG_405EZ) || \
 		defined(CONFIG_405EX) || \
include/serial.h +1 -1
index f6bb2b9..d232d47 100644
@@ -26,7 +26,7 @@ extern struct serial_device serial_smc_device;
 extern struct serial_device serial_scc_device;
 extern struct serial_device *default_serial_console(void);
 
-#if	defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if	defined(CONFIG_405GP) || \
 	defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 	defined(CONFIG_405EX) || defined(CONFIG_440) || \
 	defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH 1/1 ppc4xx: Remove support for PPC405CR CPUs

Quoted 4 lines · Matthias Fuchs

This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.

Signed-off-by Matthias Fuchs <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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