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FSL SECURE BOOT: Add support for next level image validation

PATCH New Ruchika Gupta 6 participants 13 messages Mar 28, 2013 – Aug 19, 2013

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Ruchika Gupta

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#0 lore raw

cover FSL SECURE BOOT: Add support for next level image validation

The patch set adds support for next level image validation (linux, rootfs, dtb) in secure boot scenarios.

The patch set adds the following functaionality :
1. In secure boot, PAMU is not in bypassed mode. For validating next level images, CAAM block needs to be accessed. In order to access the CAAM block, first PAMU needs to be configured to allow access to CAAM block from core. This patch set adds the basic driver for PAMU.

2. Support has been added for using job ring interface of SEC block to do cryptographic operations. Descriptors for the following crypto operations have been added
a) RSA modular exponentiation
b) SHA-256
c) cryptographic blob encryption/decryption

3. esbc_validate command added which uses the SEC block and verifies the images. esbc_validate command is meant for validating header and
signature of images (Boot Script and ESBC uboot client).
SHA-256 and RSA operations are performed using SEC block in HW. This command works on both high-end (P4080) and low-end (P1010) platforms.

Ruchika Gupta (5):
arch/powerpc/cpu/mpc8xxx: PAMU driver support powerpc/pamu : PAMU configuration for accessing SEC block drivers/sec : Freescale SEC driver
FSL SEC Driver : Add support for descriptor creation Added command for validation of images in case of secure boot

 Makefile                                     |    1 +
 arch/powerpc/cpu/mpc85xx/Makefile            |    2 +
 arch/powerpc/cpu/mpc85xx/cmd_esbc_validate.c |   54 +
 arch/powerpc/cpu/mpc85xx/cpu_init.c          |   17 +
 arch/powerpc/cpu/mpc85xx/fsl_sfp_snvs.c      |  163 +++
 arch/powerpc/cpu/mpc85xx/fsl_validate.c      |  543 +++++++++
 arch/powerpc/cpu/mpc8xxx/Makefile            |    3 +-
 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c          |  488 ++++++++
 arch/powerpc/cpu/mpc8xxx/fsl_pamu_table.c    |   68 ++
 arch/powerpc/include/asm/fsl_pamu.h          |  194 ++++
 arch/powerpc/include/asm/fsl_secure_boot.h   |   68 ++-
 arch/powerpc/include/asm/fsl_sfp_snvs.h      |   42 +
 arch/powerpc/include/asm/immap_85xx.h        |  121 ++-
 arch/powerpc/include/asm/types.h             |    5 +-
 drivers/sec/Makefile                         |   46 +
 drivers/sec/error.c                          |  259 +++++
 drivers/sec/jobdesc.c                        |  157 +++
 drivers/sec/jr.c                             |  319 +++++
 drivers/sec/rsa_sec.c                        |   95 ++
 drivers/sec/sha.c                            |  111 ++
 include/desc.h                               | 1605 ++++++++++++++++++++++++++
 include/desc_constr.h                        |  200 ++++
 include/jobdesc.h                            |   55 +
 include/jr.h                                 |  129 ++
 include/rsa_sec.h                            |   59 +
 include/sha.h                                |  100 ++
 26 files changed, 4900 insertions(+), 4 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/cmd_esbc_validate.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_sfp_snvs.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_validate.c
 create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
 create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu_table.c
 create mode 100644 arch/powerpc/include/asm/fsl_pamu.h
 create mode 100644 arch/powerpc/include/asm/fsl_sfp_snvs.h
 create mode 100644 drivers/sec/Makefile
 create mode 100644 drivers/sec/error.c
 create mode 100644 drivers/sec/jobdesc.c
 create mode 100644 drivers/sec/jr.c
 create mode 100644 drivers/sec/rsa_sec.c
 create mode 100644 drivers/sec/sha.c
 create mode 100644 include/desc.h
 create mode 100644 include/desc_constr.h
 create mode 100644 include/jobdesc.h
 create mode 100644 include/jr.h
 create mode 100644 include/rsa_sec.h
 create mode 100644 include/sha.h
Signature · 1 line
1.7.7.6
author
#1 lore raw

PATCH 1/5 arch/powerpc/cpu/mpc8xxx: PAMU driver support

PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured.

The Header file fsl_pamu.h and few functions in driver have been derived from Freescale Libos.

Signed-off-by Kuldip Giroh <[email protected]>
Signed-off-by Ruchika Gupta <[email protected]>

---
Based upon git://git.denx.de/u-boot.git branch master

 arch/powerpc/cpu/mpc8xxx/Makefile     |    3 +-
 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c   |  488 +++++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/fsl_pamu.h   |  193 +++++++++++++
 arch/powerpc/include/asm/immap_85xx.h |   18 ++
 4 files changed, 701 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
 create mode 100644 arch/powerpc/include/asm/fsl_pamu.h
arch/powerpc/cpu/mpc8xxx/Makefile +2 -1
index 3dc8e05..097599e 100644
@@ -1,5 +1,5 @@
 #
-# Copyright 2009-2010 Freescale Semiconductor, Inc.
+# Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License

@@ -33,6 +33,7 @@ COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 COBJS-$(CONFIG_SYS_SRIO) += srio.o
 COBJS-$(CONFIG_FSL_LAW) += law.o
+COBJS-$(CONFIG_FSL_CORENET) += fsl_pamu.o
 
 endif
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c new file +488 -0

488 lines not on this page · raw message

arch/powerpc/include/asm/fsl_pamu.h new file +193 -0

193 lines not on this page · raw message

arch/powerpc/include/asm/immap_85xx.h +18 -0
index 4eb3f79..17e0f39 100644
@@ -2829,6 +2829,21 @@ typedef struct ccsr_pme {
 	u8	res4[0x400];
 } ccsr_pme_t;
 
+typedef struct ccsr_pamu {
+	u32 ppbah;
+	u32 ppbal;
+	u32 pplah;
+	u32 pplal;
+	u32 spbah;
+	u32 spbal;
+	u32 splah;
+	u32 splal;
+	u32 obah;
+	u32 obal;
+	u32 olah;
+	u32 olal;
+} ccsr_pamu_t;
+
 typedef struct ccsr_usb_phy {
 	u8	res0[0x18];
 	u32	usb_enable_override;

@@ -2905,6 +2920,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
+#define CONFIG_SYS_FSL_PAMU_OFFSET		0x20000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		CONFIG_SYS_MPC85xx_DMA1_OFFSET

@@ -3085,6 +3101,8 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
 #define CONFIG_SYS_FSL_SRIO_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CONFIG_SYS_PAMU_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
Signature · 1 line
1.7.7.6
#2 lore raw

PATCH 1/5 arch/powerpc/cpu/mpc8xxx: PAMU driver support

Quoted 5 lines · Ruchika Gupta

PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured.

Quoted 8 lines

The Header file fsl_pamu.h and few functions in driver have been derived from Freescale Libos.

Signed-off-by Kuldip Giroh <[email protected]>
Signed-off-by Ruchika Gupta <[email protected]>

---
Based upon git://git.denx.de/u-boot.git branch master

You don't really have to say this as a) It's assumed, b) It becomes quickly obsolete (as it is now). You probably only need to mention it if you're based on an unusual git repo.

(quoted diff) +0 -0

b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
new file mode 100644
index 0000000..bdbec07
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c

[...]

+
+static inline int __ilog2_roundup_64(uint64_t val) +{
+
+ if ((val & (val - 1)) == 0)
+ return __ilog2_u64(val);
+ else
+ return __ilog2_u64(val) + 1;
+}

These sorts of functions seem like they belong
in arch/powerpc/include/asm/bitops.h

Quoted 8 lines
(quoted diff) +7 -0
+
+
+static inline int count_lsb_zeroes(unsigned long val)
+{
+       return ffs(val) - 1;
+}
+

[...]

Quoted 9 lines
(quoted diff) +8 -0
+static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr,
+       uint64_t win_size, uint32_t omi,
+       uint32_t snoopid, uint32_t stashid,
+       uint32_t subwin_cnt)
+{
+       unsigned long fspi;
+       paace_t *ppaace;
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+       if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE)
+               return -1;
+
+       if (win_addr & (win_size - 1))
+               return -2;
+
+       if (liodn > NUM_PPAACT_ENTRIES) {
+               printf("Entries in PPACT not sufficient\n");
+               return -3;
+       }

These return values should really have names to define, up-front, what they mean.

Quoted 14 lines
(quoted diff) +13 -0
+
+       ppaace = &ppaact[liodn];
+
+       /* window size is 2^(WSE+1) bytes */
+       set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE,
+               map_addrspace_size_to_wse(win_size));
+
+       pamu_setup_default_xfer_to_host_ppaace(ppaace);
+
+       if (sizeof(phys_addr_t) > 4)
+               ppaace->wbah = (u64)win_addr >> (PAMU_PAGE_SHIFT + 20);
+       else
+               ppaace->wbah = 0;

Review

Quoted 10 lines
(quoted diff) +10 -0
+
+       set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL,
+              (win_addr >> PAMU_PAGE_SHIFT));
+
+       /* set up operation mapping if it's configured */
+       if (omi < OME_NUMBER_ENTRIES) {
+               set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
+               ppaace->op_encode.index_ot.omi = omi;
+       } else if (~omi != 0)
+               return -3;

ditto here

Quoted 9 lines
(quoted diff) +8 -0
+static int pamu_config_spaace(uint32_t liodn,
+       uint64_t subwin_size, uint64_t subwin_addr, uint64_t size,
+       uint32_t omi, uint32_t snoopid, uint32_t stashid)
+{
+       paace_t *paace;
+       unsigned long fspi;
+       /* Align start addr of subwin to subwindoe size */
+       uint64_t sec_addr = subwin_addr & ~(subwin_size - 1);

Review

Quoted 10 lines
(quoted diff) +10 -0
+       uint64_t end_addr = subwin_addr + size;
+       int size_shift = __ilog2_u64(subwin_size);
+       uint64_t win_size = 0;
+       uint32_t index, swse;
+
+       /* Recalculate the size */
+       size = end_addr - sec_addr;
+
+       if (!subwin_size)
+               return -1;

Also need a named constant here

Review

Quoted 8 lines
(quoted diff) +7 -0
+
+       if (liodn > NUM_PPAACT_ENTRIES) {
+               printf("LIODN Number to be programmed %d"
+                       "greater than number of PPAACT entries %d\n",
+                               liodn, NUM_PPAACT_ENTRIES);
+               return -1;
+       }

And here

Review

Quoted 10 lines
(quoted diff) +9 -0
+
+       while (sec_addr < end_addr) {
+#ifdef DEBUG
+               printf("sec_addr < end_addr is %llx < %llx\n", sec_addr,
+                       end_addr);
+#endif
+               paace = &ppaact[liodn];
+               if (!paace)
+                       return -1;

And here

+
+int pamu_init(void)
+{
+ u32 base_addr = CONFIG_SYS_PAMU_ADDR;

void *base_addr = (void *)CONFIG_SYS_PAMU_ADDR;

+       ccsr_pamu_t *regs;
+       u32 i = 0;
+       u64 ppaact_phys, ppaact_lim, ppaact_size;
+       u64 spaact_phys, spaact_lim, spaact_size;

+
+ ppaact_size = sizeof(paace_t) * NUM_PPAACT_ENTRIES;
+ spaact_size = sizeof(paace_t) * NUM_SPAACT_ENTRIES;
+

+       /* Allocate space for Primary PAACT Table */
+       ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size);
+       if (!ppaact)

+ return -1;

Named constant.

Review

Quoted 7 lines
(quoted diff) +6 -0
+       memset(ppaact, 0, ppaact_size);
+
+       /* Allocate space for Secondary PAACT Table */
+       sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size);
+       if (!sec)
+               return -1;

And here

Review

Quoted 12 lines
(quoted diff) +11 -0
+       memset(sec, 0, spaact_size);
+
+       ppaact_phys = virt_to_phys((void *)ppaact);
+       ppaact_lim = ppaact_phys + ppaact_size;
+
+       spaact_phys = (uint64_t)virt_to_phys((void *)sec);
+       spaact_lim = spaact_phys + spaact_size;
+
+       /* Configure all PAMU's */
+       for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+               regs = (ccsr_pamu_t *)base_addr;

No need for cast once base_addr is more sane.

Quoted 16 lines
(quoted diff) +15 -0
+
+               out_be32(&regs->ppbah, ppaact_phys >> 32);
+               out_be32(&regs->ppbal, (uint32_t)ppaact_phys);
+
+               out_be32(&regs->pplah, (ppaact_lim) >> 32);
+               out_be32(&regs->pplal, (uint32_t)ppaact_lim);
+
+               if (sec != NULL) {
+                       out_be32(&regs->spbah, spaact_phys >> 32);
+                       out_be32(&regs->spbal, (uint32_t)spaact_phys);
+                       out_be32(&regs->splah, spaact_lim >> 32);
+                       out_be32(&regs->splal, (uint32_t)spaact_lim);
+               }
+               asm volatile("sync" : : : "memory");
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+               base_addr += PAMU_OFFSET;
+       }
+
+       return 0;
+}
+
+void pamu_enable(void)
+{
+       u32 i = 0;
+       u32 base_addr = CONFIG_SYS_PAMU_ADDR;

void *base_addr = (void *)CONFIG_SYS_PAMU_ADDR;

Review

Quoted 4 lines
(quoted diff) +3 -0
+       for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+               setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
+                       PAMU_PCR_PE);

And then eliminate the "(void *)" here

Review

Quoted 10 lines
(quoted diff) +9 -0
+               asm volatile("sync" : : : "memory");
+               base_addr += PAMU_OFFSET;
+       }
+}
+
+void pamu_reset(void)
+{
+       u32 i  = 0;
+       u32 base_addr = CONFIG_SYS_PAMU_ADDR;

void *base_addr = (void *)CONFIG_SYS_PAMU_ADDR;

In general, why would you declare an address as u32? We have 32 and 64-bit processors that use PAMU. Does this work at all on e5500 or e6500?

+ ccsr_pamu_t *regs;

Review

Quoted 4 lines
(quoted diff) +3 -0
+
+       for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+               regs = (ccsr_pamu_t *)base_addr;

Get rid of cast by following above recommendation.

Quoted 11 lines
(quoted diff) +10 -0
+       /* Clear PPAACT Base register */
+               out_be32(&regs->ppbah, 0);
+               out_be32(&regs->ppbal, 0);
+               out_be32(&regs->pplah, 0);
+               out_be32(&regs->pplal, 0);
+               out_be32(&regs->spbah, 0);
+               out_be32(&regs->spbal, 0);
+               out_be32(&regs->splah, 0);
+               out_be32(&regs->splal, 0);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+               clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE);
+               asm volatile("sync" : : : "memory");
+               base_addr += PAMU_OFFSET;
+       }
+}
+
+void pamu_disable(void)
+{
+       u32 i  = 0;
+       u32 base_addr = CONFIG_SYS_PAMU_ADDR;

ditto here.

Quoted 6 lines
(quoted diff) +4 -0
+
+
+       for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+               clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET,

PAMU_PCR_PE);

And this cast

Quoted 7 lines
(quoted diff) +6 -0
+               asm volatile("sync" : : : "memory");
+               base_addr += PAMU_OFFSET;
+       }
+}
+
+

[...]

Quoted 9 lines

+int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn)

(quoted diff) +6 -0
+{
+       int i = 0;
+       int ret = 0;
+       uint32_t num_sec_windows = 0;
+       uint32_t num_windows = 0;
+       uint64_t min_addr, max_addr;

Review

Quoted 10 lines
(quoted diff) +10 -0
+       uint64_t size;
+       uint64_t subwin_size;
+       int sizebit;
+
+       min_addr = find_min(tbl->start_addr, num_entries);
+       max_addr = find_max(tbl->end_addr, num_entries);
+       size = max_addr - min_addr + 1;
+
+       if (!size)
+               return -1;

Named constant

Quoted 10 lines
(quoted diff) +9 -0
+
+       sizebit = __ilog2_roundup_64(size);
+       size = 1 << sizebit;
+#ifdef DEBUG
+       printf("min start_addr is %llx\n", min_addr);
+       printf("max end_addr is %llx\n", max_addr);
+       printf("size found is  %llx\n", size);
+#endif
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+       if (size < PAMU_PAGE_SIZE)
+               size = PAMU_PAGE_SIZE;
+
+       while (1) {
+               min_addr = min_addr & ~(size - 1);
+               if (min_addr + size > max_addr)
+                       break;
+               size <<= 1;
+               if (!size)
+                       return -1;

Named constant

(quoted diff) +0 -0

b/arch/powerpc/include/asm/fsl_pamu.h
new file mode 100644
index 0000000..e2cfe97

arch/powerpc/include/asm/fsl_pamu.h new file +0 -0
@@ -0,0 +1,193 @@

Review

Quoted 5 lines
(quoted diff) +4 -0
+
+#define CONFIG_NUM_PAMU                16
+#define NUM_PPAACT_ENTRIES     512
+#define NUM_SPAACT_ENTRIES     128

Aren't these values variable, depending on the platform?

Quoted 24 lines
(quoted diff) +24 -0
+
+/* PAMU_OFFSET to the next pamu space in ccsr */
+#define PAMU_OFFSET 0x1000
+
+#define PAMU_TABLE_ALIGNMENT 0x00001000
+
+#define PAMU_PAGE_SHIFT 12
+#define PAMU_PAGE_SIZE  4096U
+
+#define PAACE_M_COHERENCE_REQ   0x01
+
+#define PAACE_DA_HOST_CR                0x80
+#define PAACE_DA_HOST_CR_SHIFT          7
+
+#define PAACE_AF_PT                     0x00000002
+#define PAACE_AF_PT_SHIFT               1
+
+#define PAACE_PT_PRIMARY       0x0
+#define PAACE_PT_SECONDARY     0x1
+
+#define PPAACE_AF_WBAL                 0xfffff000
+#define PPAACE_AF_WBAL_SHIFT           12
+
+#define        OME_NUMBER_ENTRIES      16   /* based on P4080 2.0 silicon
Quoted 2 lines

plan */

...Is this P4080-specific?

Andy

#3 lore raw

PATCH 1/5 arch/powerpc/cpu/mpc8xxx: PAMU driver support

In reply to Ruchika Gupta
Quoted 5 lines · Ruchika Gupta

PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured.

Quoted 7 lines

The Header file fsl_pamu.h and few functions in driver have been derived from Freescale Libos.

Signed-off-by Kuldip Giroh <[email protected]>
Signed-off-by Ruchika Gupta <[email protected]>

Ruchika and Kuldip,

Please update your patches for this series. They were first sent on March 28, 2013.

York

author
#4 lore raw

PATCH 2/5 powerpc/pamu : PAMU configuration for accessing SEC block

In reply to Ruchika Gupta
Signed-off-by Kuldip Giroh <[email protected]>
Signed-off-by Ruchika Gupta <[email protected]>

---
Based upon git://git.denx.de/u-boot.git branch master

 arch/powerpc/cpu/mpc8xxx/Makefile         |    2 +-
 arch/powerpc/cpu/mpc8xxx/fsl_pamu_table.c |   68 +++++++++++++++++++++++++++++
 arch/powerpc/include/asm/fsl_pamu.h       |    1 +
 3 files changed, 70 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu_table.c
arch/powerpc/cpu/mpc8xxx/Makefile +1 -1
index 097599e..7099136 100644
@@ -33,7 +33,7 @@ COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 COBJS-$(CONFIG_SYS_SRIO) += srio.o
 COBJS-$(CONFIG_FSL_LAW) += law.o
-COBJS-$(CONFIG_FSL_CORENET) += fsl_pamu.o
+COBJS-$(CONFIG_FSL_CORENET) += fsl_pamu.o fsl_pamu_table.o
 
 endif
arch/powerpc/cpu/mpc8xxx/fsl_pamu_table.c new file +68 -0

68 lines not on this page · raw message

arch/powerpc/include/asm/fsl_pamu.h +1 -0
index e2cfe97..85ef9bf 100644
@@ -189,5 +189,6 @@ int pamu_init(void);
 void pamu_enable(void);
 void pamu_disable(void);
 int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
+int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
 
 #endif
Signature · 1 line
1.7.7.6
author
#5 lore raw

PATCH 3/5 drivers/sec : Freescale SEC driver

In reply to Ruchika Gupta

SEC driver support is required in secure boot

Following files have been picked up from caam driver in Linux :
include/desc.h

The file drivers/sec/jr.c has some functions derived from caam driver in Linux.

Signed-off-by Kuldip Giroh <[email protected]>
Signed-off-by Ruchika Gupta <[email protected]>

---
Based upon git://git.denx.de/u-boot.git branch master

 Makefile                              |    1 +
 arch/powerpc/include/asm/immap_85xx.h |   50 +-
 arch/powerpc/include/asm/types.h      |    5 +-
 drivers/sec/Makefile                  |   46 +
 drivers/sec/jr.c                      |  319 +++++++
 include/desc.h                        | 1605 +++++++++++++++++++++++++++++++++
 include/jr.h                          |  129 +++
 7 files changed, 2152 insertions(+), 3 deletions(-)
 create mode 100644 drivers/sec/Makefile
 create mode 100644 drivers/sec/jr.c
 create mode 100644 include/desc.h
 create mode 100644 include/jr.h
Makefile +1 -0
index 12763ce..2b63585 100644
@@ -329,6 +329,7 @@ LIBS-y += common/libcommon.o
 LIBS-y += lib/libfdt/libfdt.o
 LIBS-y += api/libapi.o
 LIBS-y += post/libpost.o
+LIBS-y += drivers/sec/libsec.o
 LIBS-y += test/libtest.o
 
 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
arch/powerpc/include/asm/immap_85xx.h +48 -2

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arch/powerpc/include/asm/types.h +4 -1
index b27a6b7..ec9a4c3 100644
@@ -41,8 +41,11 @@ typedef unsigned long long u64;
 
 #define BITS_PER_LONG 32
 
-/* DMA addresses are 32-bits wide */
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+#else
 typedef u32 dma_addr_t;
+#endif
 
 #ifdef CONFIG_PHYS_64BIT
 typedef unsigned long long phys_addr_t;
drivers/sec/Makefile new file +46 -0

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drivers/sec/jr.c new file +319 -0

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include/desc.h new file +1605 -0

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include/jr.h new file +129 -0

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Signature · 1 line
1.7.7.6
author
#6 lore raw

PATCH 4/5 FSL SEC Driver : Add support for descriptor creation

In reply to Ruchika Gupta

The patch add supports for descriptor creation for doing 1.SHA256 and RSA Modular exponentiation.
2. Cryptographic blob encryption/decryption

Following files have been picked up from caam driver in Linux :
drivers/sec/error.c
include/desc_constr.h

Signed-off-by Kuldip Giroh <[email protected]>
Signed-off-by Ruchika Gupta <[email protected]>

---
Based upon git://git.denx.de/u-boot.git branch master

 drivers/sec/Makefile  |    2 +-
 drivers/sec/error.c   |  259 +++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/sec/jobdesc.c |  157 ++++++++++++++++++++++++++++++
 drivers/sec/rsa_sec.c |   95 ++++++++++++++++++
 drivers/sec/sha.c     |  111 +++++++++++++++++++++
 include/desc_constr.h |  200 ++++++++++++++++++++++++++++++++++++++
 include/jobdesc.h     |   55 +++++++++++
 include/rsa_sec.h     |   59 +++++++++++
 include/sha.h         |  100 +++++++++++++++++++
 9 files changed, 1037 insertions(+), 1 deletions(-)
 create mode 100644 drivers/sec/error.c
 create mode 100644 drivers/sec/jobdesc.c
 create mode 100644 drivers/sec/rsa_sec.c
 create mode 100644 drivers/sec/sha.c
 create mode 100644 include/desc_constr.h
 create mode 100644 include/jobdesc.h
 create mode 100644 include/rsa_sec.h
 create mode 100644 include/sha.h
drivers/sec/Makefile +1 -1
index 33c707e..01eafba 100644
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)libsec.o
 
-COBJS-$(CONFIG_SECURE_BOOT) += jr.o
+COBJS-$(CONFIG_SECURE_BOOT) += jr.o jobdesc.o sha.o rsa_sec.o error.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
drivers/sec/error.c new file +259 -0

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drivers/sec/jobdesc.c new file +157 -0

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drivers/sec/rsa_sec.c new file +95 -0

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drivers/sec/sha.c new file +111 -0

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include/desc_constr.h new file +200 -0

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include/jobdesc.h new file +55 -0

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include/rsa_sec.h new file +59 -0

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include/sha.h new file +100 -0

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Signature · 1 line
1.7.7.6
author
#7 lore raw

PATCH 5/5 Added command for validation of images in case of secure boot

In reply to Ruchika Gupta

1. Default environment will be used for secure boot flow which can't be edited or saved.
2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this:
#define CONFIG_SECBOOT \
"setenv bs_hdraddr 0xe8e00000;" \
"esbc_validate $bs_hdraddr;" \
"source $img_addr;" \
"esbc_halt;"
#endif
3. esbc_validate command is meant for validating header and signature of images (Boot Script and ESBC uboot client). SHA-256 and RSA operations are performed using SEC block in HW. This command works on both high-end (P4080) and low-end (P1010) platforms.
Command usage:
esbc_validate img_hdr_addr [pub_key_hash]
4. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript.
5. ESBC uboot client can be linux. Additionally, rootfs and device tree blob can also be signed.
6. In the event of header or signature failure in validation, ITS and ITF bits determine further course of action.
7. In case of soft failure, appropriate error is dumped on console and next esbc_validate command is executed.
8. In case of hard failure, SoC is issued RESET REQUEST after dumping error on the console.
9. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin.

Signed-off-by Kuldip Giroh <[email protected]>
Signed-off-by Ruchika Gupta <[email protected]>

---
Based upon git://git.denx.de/u-boot.git branch master

 arch/powerpc/cpu/mpc85xx/Makefile            |    2 +
 arch/powerpc/cpu/mpc85xx/cmd_esbc_validate.c |   54 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c          |   17 +
 arch/powerpc/cpu/mpc85xx/fsl_sfp_snvs.c      |  163 ++++++++
 arch/powerpc/cpu/mpc85xx/fsl_validate.c      |  543 ++++++++++++++++++++++++++
 arch/powerpc/include/asm/fsl_secure_boot.h   |   68 ++++-
 arch/powerpc/include/asm/fsl_sfp_snvs.h      |   42 ++
 arch/powerpc/include/asm/immap_85xx.h        |   55 +++
 8 files changed, 943 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/cmd_esbc_validate.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_sfp_snvs.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_validate.c
 create mode 100644 arch/powerpc/include/asm/fsl_sfp_snvs.h
arch/powerpc/cpu/mpc85xx/Makefile +2 -0
index 6776c85..66b7b67 100644
@@ -109,6 +109,8 @@ COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o
 COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
 COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
+COBJS-$(CONFIG_SECURE_BOOT) += fsl_sfp_snvs.o
+COBJS-$(CONFIG_CMD_ESBC_VALIDATE) += cmd_esbc_validate.o fsl_validate.o
 
 # SoC specific SERDES support
 COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
arch/powerpc/cpu/mpc85xx/cmd_esbc_validate.c new file +54 -0

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arch/powerpc/cpu/mpc85xx/cpu_init.c +17 -0
index de9d916..41d7bf8 100644
@@ -46,6 +46,14 @@
 #include <errno.h>
 #endif
 
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#include <asm/fsl_pamu.h>
+#endif
+#ifdef CONFIG_SECURE_BOOT
+#include <jr.h>
+#include <asm/fsl_secboot_err.h>
+#endif
+
 #include "../../../../drivers/block/fsl_sata.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -650,6 +658,15 @@ skip_l2:
 	}
 #endif
 
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+	if (pamu_init() < 0)
+		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
+#ifdef CONFIG_SECURE_BOOT
+	if (sec_init() < 0)
+		fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT);
+#endif
 
 	return 0;
 }
arch/powerpc/cpu/mpc85xx/fsl_sfp_snvs.c new file +163 -0

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arch/powerpc/cpu/mpc85xx/fsl_validate.c new file +543 -0

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arch/powerpc/include/asm/fsl_secure_boot.h +67 -1

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arch/powerpc/include/asm/fsl_sfp_snvs.h new file +42 -0

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arch/powerpc/include/asm/immap_85xx.h +55 -0

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Signature · 1 line
1.7.7.6
#8 lore raw

cover FSL SECURE BOOT: Add support for next level image validation

In reply to Ruchika Gupta
Quoted 2 lines · Ruchika Gupta

The patch set adds support for next level image validation (linux, rootfs, dtb) in secure boot scenarios.

It seems to focus in PowerPC, do you know if same code could be ported to ARM?

--
Otavio Salvador O.S. Systems
E-mail: otavio at ossystems.com.br http://www.ossystems.com.br
Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br

#9 lore raw

cover FSL SECURE BOOT: Add support for next level image validation

Quoted 11 lines

-----Original Message-----
From: otavio.salvador at gmail.com [mailto:otavio.salvador at gmail.com] On Behalf Of Otavio Salvador
Sent: Thursday, March 28, 2013 8:23 PM
To: Gupta Ruchika-R66431
Cc: U-Boot Mailing List; Fleming Andy-AFLEMING
Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next level image validation

Quoted 7 lines
Quoted 2 lines · Ruchika Gupta

The patch set adds support for next level image validation (linux, rootfs, dtb) in secure boot scenarios.

It seems to focus in PowerPC, do you know if same code could be ported to ARM?

For the code to be ported to ARM platform, corresponding hardware blocks like cryptographic accelerator/SW support for crypto operations, IOMMU and a security monitor block will be required.

Ruchika

Quoted 5 lines

--
Otavio Salvador O.S. Systems
E-mail: otavio at ossystems.com.br http://www.ossystems.com.br
Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br

#10 lore raw

cover FSL SECURE BOOT: Add support for next level image validation

Quoted 8 lines · On Fri, 29 Mar 2013 04:43:23 +0000 Gupta Ruchika-R66431 <[email protected]>…
Quoted 8 lines

From: otavio.salvador at gmail.com [mailto:otavio.salvador at gmail.com] On Behalf Of Otavio Salvador
Sent: Thursday, March 28, 2013 8:23 PM
To: Gupta Ruchika-R66431
Cc: U-Boot Mailing List; Fleming Andy-AFLEMING
Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next level image validation

Quoted 8 lines
Quoted 7 lines
Quoted 2 lines · Ruchika Gupta

The patch set adds support for next level image validation (linux, rootfs, dtb) in secure boot scenarios.

It seems to focus in PowerPC, do you know if same code could be ported to ARM?

For the code to be ported to ARM platform, corresponding hardware blocks like cryptographic accelerator/SW support for crypto operations, IOMMU and a security monitor block will be required.

i.mx6 has, and other future ARM-based devices will have, a CAAM, so I see no reason why any of this code should be restricted to power arch at all.

How does this patchseries integrate with this SHA offload patchseries:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156321

and this "verified boot" implementation:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156422

?

Kim

#11 lore raw

cover FSL SECURE BOOT: Add support for next level image validation

Quoted 41 lines

-----Original Message-----
From: Phillips Kim-R1AAHA
Sent: Saturday, March 30, 2013 4:08 AM
To: Gupta Ruchika-R66431
Cc: Otavio Salvador; U-Boot Mailing List; Fleming Andy-AFLEMING
Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next level image validation

Quoted 11 lines · On Fri, 29 Mar 2013 04:43:23 +0000 Gupta Ruchika-R66431 <[email protected]>…
Quoted 11 lines

From: otavio.salvador at gmail.com [mailto:otavio.salvador at gmail.com] On Behalf Of Otavio Salvador
Sent: Thursday, March 28, 2013 8:23 PM
To: Gupta Ruchika-R66431
Cc: U-Boot Mailing List; Fleming Andy-AFLEMING
Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next level image validation

On Thu, Mar 28, 2013 at 7:46 AM, Ruchika Gupta
<[email protected]>
wrote:

Quoted 6 lines
Quoted 5 lines
Quoted 2 lines

The patch set adds support for next level image validation (linux, rootfs, dtb) in secure boot scenarios.

It seems to focus in PowerPC, do you know if same code could be ported to ARM?

For the code to be ported to ARM platform, corresponding hardware blocks

like cryptographic accelerator/SW support for crypto operations, IOMMU and a security monitor block will be required.

i.mx6 has, and other future ARM-based devices will have, a CAAM, so I see no reason why any of this code should be restricted to power arch at all.

How does this patchseries integrate with this SHA offload patchseries:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156321

Quoted 7 lines

and this "verified boot" implementation:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156422

?

Kim

Thanks for the suggestion Kim. I will have a look at the links you mentioned and see how my patches can fit in. Since I am on leave this week so my response on this will be a little delayed.

Ruchika

#12 lore raw

cover FSL SECURE BOOT: Add support for next level image validation

In reply to Kim Phillips
Quoted 33 lines

-----Original Message-----
From: Phillips Kim-R1AAHA
Sent: Saturday, March 30, 2013 4:08 AM
To: Gupta Ruchika-R66431
Cc: Otavio Salvador; U-Boot Mailing List; Fleming Andy-AFLEMING
Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next level image validation

Quoted 11 lines · On Fri, 29 Mar 2013 04:43:23 +0000 Gupta Ruchika-R66431 <[email protected]>…
Quoted 11 lines

From: otavio.salvador at gmail.com [mailto:otavio.salvador at gmail.com] On Behalf Of Otavio Salvador
Sent: Thursday, March 28, 2013 8:23 PM
To: Gupta Ruchika-R66431
Cc: U-Boot Mailing List; Fleming Andy-AFLEMING
Subject: Re: [U-Boot] [PATCH 0/5] FSL SECURE BOOT: Add support for next level image validation

On Thu, Mar 28, 2013 at 7:46 AM, Ruchika Gupta
<[email protected]>
wrote:

Quoted 6 lines
Quoted 5 lines
Quoted 2 lines

The patch set adds support for next level image validation (linux, rootfs, dtb) in secure boot scenarios.

It seems to focus in PowerPC, do you know if same code could be ported to ARM?

For the code to be ported to ARM platform, corresponding hardware blocks

like cryptographic accelerator/SW support for crypto operations, IOMMU and a security monitor block will be required.

Quoted 7 lines

i.mx6 has, and other future ARM-based devices will have, a CAAM, so I see no reason why any of this code should be restricted to power arch at all.

How does this patchseries integrate with this SHA offload patchseries:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156321

Once this patch series is applied on the main branch I will rebase my patch, align to this and re-send.

Quoted 6 lines

and this "verified boot" implementation:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/156422

?

Thanks for pointing this link out. We have been using bootscript approach for validating next level images, which works on validation of each of the Linux, rootfs and dtb image separately. The location of this bootscript is hardcoded in the board bootcmd file. However the approach pointed by this link is more generic, since it validates a single FIT image. I will work towards integrating our SoC's approach into this framework.

Ruchika