arm: dts: Add clock entries for timers in SOCFPGA
PATCH v4 1/4 arm: dts: Add clock entries for timers in SOCFPGA
From: Dinh Nguyen <[email protected]>
Set the correct clock entries for the the timers, and also clean up the timer entries for SOCFPGA by removing timer<n> in the timer entry.
--- arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++-------- arch/arm/boot/dts/socfpga_cyclone5.dts | 8 ++++---- arch/arm/boot/dts/socfpga_vt.dts | 8 ++++---- 3 files changed, 16 insertions(+), 16 deletions(-)
arch/arm/boot/dts/socfpga.dtsi +8 -8
@@ -26,10 +26,6 @@ ethernet1 = &gmac1; serial0 = &uart0; serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; }; cpus {
@@ -475,28 +471,32 @@ interrupts = <1 13 0xf04>; }; - timer0: timer0 at ffc08000 { + timer at ffc08000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 167 4>; reg = <0xffc08000 0x1000>; + clocks = <&osc>; }; - timer1: timer1 at ffc09000 { + timer at ffc09000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 168 4>; reg = <0xffc09000 0x1000>; + clocks = <&osc>; }; - timer2: timer2 at ffd00000 { + timer at ffd00000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 169 4>; reg = <0xffd00000 0x1000>; + clocks = <&l4_sp_clk>; }; - timer3: timer3 at ffd01000 { + timer at ffd01000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 170 4>; reg = <0xffd01000 0x1000>; + clocks = <&l4_sp_clk>; }; uart0: serial0 at ffc02000 {
arch/arm/boot/dts/socfpga_cyclone5.dts +4 -4
@@ -54,19 +54,19 @@ status = "okay"; }; - timer0 at ffc08000 { + timer at ffc08000 { clock-frequency = <100000000>; }; - timer1 at ffc09000 { + timer at ffc09000 { clock-frequency = <100000000>; }; - timer2 at ffd00000 { + timer at ffd00000 { clock-frequency = <25000000>; }; - timer3 at ffd01000 { + timer at ffd01000 { clock-frequency = <25000000>; };
arch/arm/boot/dts/socfpga_vt.dts +4 -4
@@ -46,19 +46,19 @@ status = "okay"; }; - timer0 at ffc08000 { + timer at ffc08000 { clock-frequency = <7000000>; }; - timer1 at ffc09000 { + timer at ffc09000 { clock-frequency = <7000000>; }; - timer2 at ffd00000 { + timer at ffd00000 { clock-frequency = <7000000>; }; - timer3 at ffd01000 { + timer at ffd01000 { clock-frequency = <7000000>; };
Signature · 1 line
1.7.9.5
PATCH v4 1/4 arm: dts: Add clock entries for timers in SOCFPGA
Hi Stephen,
Quoted 124 lines · Dinh Nguyen
From: Dinh Nguyen <[email protected]>
Set the correct clock entries for the the timers, and also clean up the timer entries for SOCFPGA by removing timer<n> in the timer entry.
Signed-off-by Dinh Nguyen <[email protected]>Reviewed-by Pavel Machek <[email protected]>CC Rob Herring <[email protected]>Cc Pawel Moll <[email protected]>Cc Mark Rutland <[email protected]>Cc Stephen Warren <[email protected]>Cc Ian Campbell <[email protected]>CC Arnd Bergmann <[email protected]>Cc Olof Johansson <[email protected]>CC Jamie Iles <[email protected]>Cc John Stultz <[email protected]>Cc Heiko Stuebner <[email protected]>Cc Pavel Machek <[email protected]>Cc devicetree at vger.kernel.orgCc linux-arm-kernel at lists.infradead.org--- arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++-------- arch/arm/boot/dts/socfpga_cyclone5.dts | 8 ++++---- arch/arm/boot/dts/socfpga_vt.dts | 8 ++++---- 3 files changed, 16 insertions(+), 16 deletions(-)arch/arm/boot/dts/socfpga.dtsi +8
-8@@ -26,10 +26,6 @@ ethernet1 = &gmac1; serial0 = &uart0; serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; }; cpus {@@ -475,28 +471,32 @@ interrupts = <1 13 0xf04>; }; - timer0: timer0 at ffc08000 { + timer at ffc08000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 167 4>; reg = <0xffc08000 0x1000>; + clocks = <&osc>; }; - timer1: timer1 at ffc09000 { + timer at ffc09000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 168 4>; reg = <0xffc09000 0x1000>; + clocks = <&osc>; }; - timer2: timer2 at ffd00000 { + timer at ffd00000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 169 4>; reg = <0xffd00000 0x1000>; + clocks = <&l4_sp_clk>; }; - timer3: timer3 at ffd01000 { + timer at ffd01000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 170 4>; reg = <0xffd01000 0x1000>; + clocks = <&l4_sp_clk>; }; uart0: serial0 at ffc02000 {arch/arm/boot/dts/socfpga_cyclone5.dts +4
-4@@ -54,19 +54,19 @@ status = "okay"; }; - timer0 at ffc08000 { + timer at ffc08000 { clock-frequency = <100000000>; }; - timer1 at ffc09000 { + timer at ffc09000 { clock-frequency = <100000000>; }; - timer2 at ffd00000 { + timer at ffd00000 { clock-frequency = <25000000>; }; - timer3 at ffd01000 { + timer at ffd01000 { clock-frequency = <25000000>; };arch/arm/boot/dts/socfpga_vt.dts +2
-2@@ -46,19 +46,19 @@ status = "okay"; }; - timer0 at ffc08000 { + timer at ffc08000 { clock-frequency = <7000000>; }; - timer1 at ffc09000 { + timer at ffc09000 { clock-frequency = <7000000>; };
arch/arm/boot/dts/socfpga_vt.dts line 64
Quoted 10 lines
arch/arm/boot/dts/socfpga_vt.dts +2
-2- timer2 at ffd00000 { + timer at ffd00000 { clock-frequency = <7000000>; }; - timer3 at ffd01000 { + timer at ffd01000 { clock-frequency = <7000000>; };
Not sure if you our Ack for:
[
PATCHv4 2/4] arm: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timer
applies to this one too. But just in case, can I get your Ack for this one too?
Thanks,
Dinh
PATCH v4 1/4 arm: dts: Add clock entries for timers in SOCFPGA
Quoted 7 lines · Dinh Nguyen
Hi Stephen,
Quoted 4 lines · Dinh Nguyen
From: Dinh Nguyen <[email protected]>
Set the correct clock entries for the the timers, and also clean up the timer entries for SOCFPGA by removing timer<n> in the timer entry.
...
Quoted 7 lines
Not sure if you our Ack for:
[
PATCHv4 2/4] arm: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timerapplies to this one too. But just in case, can I get your Ack for this one too?
I only reviewed the binding changes, not the DT file changes themselves; I don't really want to set a precedent for that, or it'll increase the review volume too much.
PATCH v4 2/4 arm: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timer
In reply to dinguyen at altera.comFrom: Dinh Nguyen <[email protected]>
"dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the DW APB timer, just fed by different clocks. Thus, deprecate both "dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer".
v3:
- Split out a separate that cleans up the timer entries and clock information.
- Clearly states which binding is deprecated in the bindingd doc.
v2:
- Deprecate the "dw-apb-timer-osc" and "dw-apb-timer-sp" but maintain backwards compatibility in the driver.
--- Documentation/devicetree/bindings/rtc/dw-apb.txt | 34 +++++++--------------- arch/arm/boot/dts/socfpga.dtsi | 8 ++--- 2 files changed, 15 insertions(+), 27 deletions(-)
Documentation/devicetree/bindings/rtc/dw-apb.txt +11 -23
@@ -1,7 +1,10 @@ * Designware APB timer Required properties: -- compatible: "snps,dw-apb-timer-sp" or "snps,dw-apb-timer-osc" +- compatible: One of: + "snps,dw-apb-timer" + "snps,dw-apb-timer-sp" <DEPRECATED> + "snps,dw-apb-timer-osc" <DEPRECATED> - reg: physical base address of the controller and length of memory mapped region. - interrupts: IRQ line for the timer.
@@ -20,25 +23,10 @@ systems may use one. Example: - - timer1: timer at ffc09000 { - compatible = "snps,dw-apb-timer-sp"; - interrupts = <0 168 4>; - clock-frequency = <200000000>; - reg = <0xffc09000 0x1000>; - }; - - timer2: timer at ffd00000 { - compatible = "snps,dw-apb-timer-osc"; - interrupts = <0 169 4>; - clock-frequency = <200000000>; - reg = <0xffd00000 0x1000>; - }; - - timer3: timer at ffe00000 { - compatible = "snps,dw-apb-timer-osc"; - interrupts = <0 170 4>; - reg = <0xffe00000 0x1000>; - clocks = <&timer_clk>, <&timer_pclk>; - clock-names = "timer", "pclk"; - }; + timer at ffe00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clocks = <&timer_clk>, <&timer_pclk>; + clock-names = "timer", "pclk"; + };
arch/arm/boot/dts/socfpga.dtsi +4 -4
@@ -472,28 +472,28 @@ }; timer at ffc08000 { - compatible = "snps,dw-apb-timer-sp"; + compatible = "snps,dw-apb-timer"; interrupts = <0 167 4>; reg = <0xffc08000 0x1000>; clocks = <&osc>; }; timer at ffc09000 { - compatible = "snps,dw-apb-timer-sp"; + compatible = "snps,dw-apb-timer"; interrupts = <0 168 4>; reg = <0xffc09000 0x1000>; clocks = <&osc>; }; timer at ffd00000 { - compatible = "snps,dw-apb-timer-osc"; + compatible = "snps,dw-apb-timer"; interrupts = <0 169 4>; reg = <0xffd00000 0x1000>; clocks = <&l4_sp_clk>; }; timer at ffd01000 { - compatible = "snps,dw-apb-timer-osc"; + compatible = "snps,dw-apb-timer"; interrupts = <0 170 4>; reg = <0xffd01000 0x1000>; clocks = <&l4_sp_clk>;
Signature · 1 line
1.7.9.5
PATCH v4 2/4 arm: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timer
Quoted 5 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
"dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the DW APB timer, just fed by different clocks. Thus, deprecate both "dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer".
The binding change looks reasonable to me.
The *.dtsi change will cause the new DT not to work with older kernels that don't support the new compatible values. Perhaps you're fine with that?
I assume that the driver has already been updated to support the new values, and that the driver change is guaranteed to be merged before this change? Otherwise, git bisect will be broken for a while.
PATCH v4 2/4 arm: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timer
Quoted 11 lines · Stephen Warren
Quoted 5 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
"dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the DW APB timer, just fed by different clocks. Thus, deprecate both "dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer".
The binding change looks reasonable to me.
The *.dtsi change will cause the new DT not to work with older kernels that don't support the new compatible values. Perhaps you're fine with that?
I am okay with the older kernels not working as SOCFPGA is pretty new and older kernel don't really have too much support for it.
Quoted 4 lines
I assume that the driver has already been updated to support the new values, and that the driver change is guaranteed to be merged before this change? Otherwise, git bisect will be broken for a while.
Yes, the patch to update the driver was part of this series, but not merged yet. The driver's V1 patch was Acked-By: Jamie Iles who is the maintainer for Picoxcell and is the only other platform using this timer driver at the moment. The only changes since V1 is to maintain compatibility for the new binding values.
Thanks,
Dinh
Quoted 1 line
PATCH v4 2/4 arm: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timer
In reply to Stephen WarrenQuoted 7 lines · Stephen Warren
Quoted 5 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
"dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the DW APB timer, just fed by different clocks. Thus, deprecate both "dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer".
Quoted 9 lines
The binding change looks reasonable to me.
The *.dtsi change will cause the new DT not to work with older kernels that don't support the new compatible values. Perhaps you're fine with that?
I assume that the driver has already been updated to support the new values, and that the driver change is guaranteed to be merged before this change? Otherwise, git bisect will be broken for a while.
Can I have your Acked-by: for these bindings? I just received an Ack from Linus Walleij for the driver portion.
Thanks,
Dinh
PATCH v4 2/4 arm: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timer
Quoted 13 lines · Dinh Nguyen
Quoted 12 lines · Stephen Warren
Quoted 5 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
"dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the DW APB timer, just fed by different clocks. Thus, deprecate both "dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer".
The binding change looks reasonable to me.
The *.dtsi change will cause the new DT not to work with older kernels that don't support the new compatible values. Perhaps you're fine with that?
Quoted 7 lines
Quoted 4 lines
I assume that the driver has already been updated to support the new values, and that the driver change is guaranteed to be merged before this change? Otherwise, git bisect will be broken for a while.
Can I have your Acked-by: for these bindings? I just received an Ack from Linus Walleij for the driver portion.
Yes, the binding change,
PATCH v4 3/4 clocksource: dw_apb_timer: Move timer defines to header file.
In reply to dinguyen at altera.comFrom: Dinh Nguyen <[email protected]>
Move all dw_apb_timer defines to include/linux/dw_apb_timer.h.
v2:
- Remove the defines in dw_apb_timer.c
--- drivers/clocksource/dw_apb_timer.c | 19 ------------------- include/linux/dw_apb_timer.h | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 19 deletions(-)
drivers/clocksource/dw_apb_timer.c +0 -19
@@ -18,25 +18,6 @@#include <linux/io.h> #include <linux/slab.h> -#define APBT_MIN_PERIOD 4 -#define APBT_MIN_DELTA_USEC 200 - -#define APBTMR_N_LOAD_COUNT 0x00 -#define APBTMR_N_CURRENT_VALUE 0x04 -#define APBTMR_N_CONTROL 0x08 -#define APBTMR_N_EOI 0x0c -#define APBTMR_N_INT_STATUS 0x10 - -#define APBTMRS_INT_STATUS 0xa0 -#define APBTMRS_EOI 0xa4 -#define APBTMRS_RAW_INT_STATUS 0xa8 -#define APBTMRS_COMP_VERSION 0xac - -#define APBTMR_CONTROL_ENABLE (1 << 0) -/* 1: periodic, 0:free running. */ -#define APBTMR_CONTROL_MODE_PERIODIC (1 << 1) -#define APBTMR_CONTROL_INT (1 << 2) -static inline struct dw_apb_clock_event_device *ced_to_dw_apb_ced (struct clock_event_device *evt) {
include/linux/dw_apb_timer.h +19 -0
@@ -19,6 +19,25 @@#define APBTMRS_REG_SIZE 0x14 +#define APBT_MIN_PERIOD 4 +#define APBT_MIN_DELTA_USEC 200 + +#define APBTMR_N_LOAD_COUNT 0x00 +#define APBTMR_N_CURRENT_VALUE 0x04 +#define APBTMR_N_CONTROL 0x08 +#define APBTMR_N_EOI 0x0c +#define APBTMR_N_INT_STATUS 0x10 + +#define APBTMRS_INT_STATUS 0xa0 +#define APBTMRS_EOI 0xa4 +#define APBTMRS_RAW_INT_STATUS 0xa8 +#define APBTMRS_COMP_VERSION 0xac + +#define APBTMR_CONTROL_ENABLE (1 << 0) +/* 1: periodic, 0:free running. */ +#define APBTMR_CONTROL_MODE_PERIODIC (1 << 1) +#define APBTMR_CONTROL_INT (1 << 2) +struct dw_apb_timer {void __iomem *base;unsigned long freq;
Signature · 1 line
1.7.9.5
PATCH v4 3/4 clocksource: dw_apb_timer: Move timer defines to header file.
Quoted 4 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Move all
dw_apb_timerdefines toinclude/linux/dw_apb_timer.h.
Quoted 10 lines
Signed-off-by Dinh Nguyen <[email protected]>CC Rob Herring <[email protected]>CC Arnd Bergmann <[email protected]>Cc Olof Johansson <[email protected]>CC Jamie Iles <[email protected]>Cc John Stultz <[email protected]>Cc Daniel Lezcano <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Linus Walleij <[email protected]>Cc Pavel Machek <[email protected]>
Thanks!
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH v4 4/4 clocksource: dw_apb_timer_of: Fix read_sched_clock
In reply to dinguyen at altera.comFrom: Dinh Nguyen <[email protected]>
The read_sched_clock should return the ~value because the clock is a countdown implementation. read_sched_clock() should be the same as __apbt_read_clocksource().
If a separate timer for the sched_clock exist, then read_sched_clock() will return an incorrect value. The (sched_io_base + 0x4) needs to be in the function for both cases.
Maintain backwards compatibility for "dw-apb-timer-sp" and "dw-apb-timer-osc".
v3:
- Use APBTMR_N_CURRENT_VALUE define in read_sched_clock()
v2:
- Maintain backwards compatibility for "dw-apb-timer-sp" and "dw-apb-timer-osc".
--- drivers/clocksource/dw_apb_timer_of.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
drivers/clocksource/dw_apb_timer_of.c +5 -4
@@ -102,18 +102,17 @@ static void add_clocksource(struct device_node *source_timer)* timer is found. sched_io_base then points to the current_value * register of the clocksource timer. */ - sched_io_base = iobase +0x04 ; + sched_io_base = iobase; sched_rate = rate; }static u32 read_sched_clock (void ) { -return __raw_readl (sched_io_base); +return ~__raw_readl (sched_io_base +APBTMR_N_CURRENT_VALUE ); }static const struct of_device_id sptimer_ids[]__initconst = { { .compatible ="picochip,pc3x2-rtc" }, - { .compatible ="snps,dw-apb-timer-sp" }, {/* Sentinel */ }, };
@@ -153,4 +152,6 @@ static void __init dw_apb_timer_init(struct device_node *timer) num_called++; }CLOCKSOURCE_OF_DECLARE (pc3x2_timer,"picochip,pc3x2-timer" , dw_apb_timer_init); -CLOCKSOURCE_OF_DECLARE (apb_timer,"snps,dw-apb-timer-osc" , dw_apb_timer_init); +CLOCKSOURCE_OF_DECLARE (apb_timer_osc,"snps,dw-apb-timer-osc" , dw_apb_timer_init); +CLOCKSOURCE_OF_DECLARE (apb_timer_sp,"snps,dw-apb-timer-sp" , dw_apb_timer_init); +CLOCKSOURCE_OF_DECLARE (apb_timer,"snps,dw-apb-timer" , dw_apb_timer_init);
Signature · 1 line
1.7.9.5
PATCH v4 4/4 clocksource: dw_apb_timer_of: Fix read_sched_clock
Quoted 27 lines · On Thu, Aug 22, 2013 at 6:30 PM, <[email protected]> wrote:
From: Dinh Nguyen <[email protected]>
The
read_sched_clockshould return the ~value because the clock is a countdown implementation.read_sched_clock()should be the same as__apbt_read_clocksource().If a separate timer for the
sched_clockexist, thenread_sched_clock()will return an incorrect value. The (sched_io_base+0x4) needs to be in the function for both cases.Maintain backwards compatibility for "dw-apb-timer-sp" and "dw-apb-timer-osc".
Signed-off-by Dinh Nguyen <[email protected]>Acked-by Jamie Iles <[email protected]>CC Rob Herring <[email protected]>CC Arnd Bergmann <[email protected]>Cc Olof Johansson <[email protected]>CC Jamie Iles <[email protected]>Cc John Stultz <[email protected]>Cc Daniel Lezcano <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Linus Walleij <[email protected]>Cc Pavel Machek <[email protected]>Cc Heiko Stuebner <[email protected]>Cc linux-arm-kernel at lists.infradead.org
Quoted 2 lines
v3:
- UseAPBTMR_N_CURRENT_VALUEdefine inread_sched_clock()
Yours,
Linus Walleij