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EXYNOS: I2S: Enable I2S0 channel

PATCH Superseded Dani Krishna Mohan 3 participants 12 messages Aug 4, 2013 – Aug 28, 2013

Subsystems (2)
Arm (32-bit) Arm Samsung Exynos

v2 of 3 Superseded Latest is v3 →

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Dani Krishna Mohan

author
#0 lore raw

v2 cover EXYNOS: I2S: Enable I2S0 channel

This patch set replaces I2S1 channel with I2S0 channel. Corresponding changes have been done in audio codec to
support I2S0 channel.

Changes in V2:
- Added cover letter.
- Configured GPIO chipselect to enable MAX98095 codec.

Dani Krishna Mohan (6):
Sound: WM8994: Support I2S0 channel
DTS: Addition of I2S0 channel and replacing I2S1
ARM: Change from I2S1 to I2S0 for audio on SMDK5250
Sound: I2S: Replacing I2S1 with I2S0 channel.
DTS: Addition of GPIO chipselect for MAX98095
Sound: MAX98095: Support I2S0 channel

 arch/arm/cpu/armv7/exynos/clock.c           |   13 ++--
 arch/arm/cpu/armv7/exynos/pinmux.c          |   15 ++++-
 arch/arm/dts/exynos5250.dtsi                |   10 ++-
 arch/arm/include/asm/arch-exynos/clock.h    |    8 ++-
 arch/arm/include/asm/arch-exynos/cpu.h      |    2 +
 arch/arm/include/asm/arch-exynos/i2s-regs.h |    6 ++
 arch/arm/include/asm/arch-exynos/periph.h   |    1 +
 board/samsung/dts/exynos5250-smdk5250.dts   |    8 +--
 board/samsung/dts/exynos5250-snow.dts       |    9 +--
 drivers/sound/max98095.c                    |   29 ++++----
 drivers/sound/samsung-i2s.c                 |   16 +++--
 drivers/sound/sound.c                       |    2 +-
 drivers/sound/wm8994.c                      |   95 +++++++++++----------------
 drivers/sound/wm8994_registers.h            |   77 ++++++++++++----------
 14 files changed, 149 insertions(+), 142 deletions(-)
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH v2 1/6 Sound: WM8994: Support I2S0 channel

This patch modifies the WM8994 codec to support I2S0 channel in codec slave mode

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- None

 drivers/sound/sound.c            |    2 +-
 drivers/sound/wm8994.c           |   95 +++++++++++++++-----------------------
 drivers/sound/wm8994_registers.h |   77 ++++++++++++++++--------------
 3 files changed, 81 insertions(+), 93 deletions(-)
drivers/sound/sound.c +1 -1
index 6fcc75d..47879a4 100644
@@ -130,7 +130,7 @@ static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
 #endif
 	if (!strcmp(codectype, "wm8994")) {
 		/* Check the codec type and initialise the same */
-		ret = wm8994_init(blob, WM8994_AIF2,
+		ret = wm8994_init(blob, WM8994_AIF1,
 			pi2s_tx->samplingrate,
 			(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
 			pi2s_tx->bitspersample, pi2s_tx->channels);
drivers/sound/wm8994.c +38 -57

140 lines not on this page · raw message

drivers/sound/wm8994_registers.h +42 -35

145 lines not on this page · raw message

Signature · 1 line
1.7.9.5
#2 lore raw

PATCH v2 1/6 Sound: WM8994: Support I2S0 channel

Dear Dani Krishna Mohan,

Quoted 12 lines · Dani Krishna Mohan

This patch modifies the WM8994 codec to support I2S0 channel in codec slave mode

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- None

 drivers/sound/sound.c            |    2 +-
 drivers/sound/wm8994.c           |   95 +++++++++++++++-----------------------
 drivers/sound/wm8994_registers.h |   77 ++++++++++++++++--------------
 3 files changed, 81 insertions(+), 93 deletions(-)

I think, we can support both of AIF1 and AIF2. Why don't you add AIF1 features instead of replacing.

Quoted 151 lines
drivers/sound/sound.c +1 -1
index 6fcc75d..47879a4 100644
@@ -130,7 +130,7 @@ static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
 #endif
 	if (!strcmp(codectype, "wm8994")) {
 		/* Check the codec type and initialise the same */
-		ret = wm8994_init(blob, WM8994_AIF2,
+		ret = wm8994_init(blob, WM8994_AIF1,
 			pi2s_tx->samplingrate,
 			(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
 			pi2s_tx->bitspersample, pi2s_tx->channels);
drivers/sound/wm8994.c +35 -54
index 37e354c..57c8f8d 100644
@@ -477,9 +477,9 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
 				reg1);
 
 	ret |= wm8994_update_bits(WM8994_CLOCKING_1,
-			WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
+			WM8994_SYSCLK_SRC | WM8994_AIF1DSPCLK_ENA_MASK |
 			WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
-			WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
+			WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
 
 	if (ret < 0) {
 		debug("%s: codec register access error\n", __func__);

@@ -536,7 +536,7 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
 					break;
 			if (i == ARRAY_SIZE(opclk_divs)) {
 				debug("%s frequency divisor not found\n",
-					__func__);
+				      __func__);
 				return -1;
 			}
 			ret = wm8994_update_bits(WM8994_CLOCKING_2,

@@ -565,28 +565,17 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
 }
 
 /*
- * Initializes Volume for AIF2 to HP path
+ * Initializes Volume for AIF1 to HP path
  *
  * @returns -1 for error  and 0 Success.
  *
  */
-static int wm8994_init_volume_aif2_dac1(void)
+static int wm8994_init_volume_aif1_dac1(void)
 {
-	int ret;
-
-	/* Unmute AIF2DAC */
-	ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1,
-			WM8994_AIF2DAC_MUTE_MASK, 0);
-
-
-	ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME,
-			WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
-			WM8994_AIF2DAC_VU | 0xff);
-
-	ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME,
-			WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
-			WM8994_AIF2DAC_VU | 0xff);
+	int ret = 0;
 
+	/* unmute AIF1DAC1 */
+	ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000);
 
 	ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
 			WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |

@@ -661,12 +650,19 @@ static int wm8994_device_init(struct wm8994_priv *wm8994)
 	ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
 				WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
 
-	/* Power enable for AIF2 and DAC1 */
-	ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
-		WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
-		WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
-		WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA |
-		WM8994_DAC1R_ENA);
+
+	ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2, WM8994_TSHUT_ENA
+			| WM8994_MIXINL_ENA | WM8994_MIXINR_ENA
+			| WM8994_IN2L_ENA | WM8994_IN2R_ENA);
+
+	ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4, WM8994_ADCL_ENA
+				| WM8994_ADCR_ENA | WM8994_AIF1ADC1R_ENA
+				| WM8994_AIF1ADC1L_ENA);
+
+	/* Power enable for AIF1 and DAC1 */
+	ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5, WM8994_AIF1DACL_ENA
+			| WM8994_AIF1DACR_ENA | WM8994_DAC1L_ENA
+			| WM8994_DAC1R_ENA);
 
 	/* Head Phone Initialisation */
 	ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,

@@ -695,35 +691,20 @@ static int wm8994_device_init(struct wm8994_priv *wm8994)
 	ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
 			WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
 
-	/* Routing AIF2 to DAC1 */
-	ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
-			WM8994_AIF2DACL_TO_DAC1L_MASK,
-			WM8994_AIF2DACL_TO_DAC1L);
-
-	ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
-			WM8994_AIF2DACR_TO_DAC1R_MASK,
-			WM8994_AIF2DACR_TO_DAC1R);
-
-	 /* GPIO Settings for AIF2 */
-	 /* B CLK */
-	ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
-				WM8994_GPIO_FUNCTION_MASK ,
-				WM8994_GPIO_DIR_OUTPUT |
-				WM8994_GPIO_FUNCTION_I2S_CLK);
-
-	/* LR CLK */
-	ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
-				WM8994_GPIO_FUNCTION_MASK,
-				WM8994_GPIO_DIR_OUTPUT |
-				WM8994_GPIO_FUNCTION_I2S_CLK);
-
-	/* DATA */
-	ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
-				WM8994_GPIO_FUNCTION_MASK,
-				WM8994_GPIO_DIR_OUTPUT |
-				WM8994_GPIO_FUNCTION_I2S_CLK);
-
-	ret |= wm8994_init_volume_aif2_dac1();
+	/* Routing AIF1 to DAC1 */
+	ret |= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING,
+			WM8994_AIF1DAC1L_TO_DAC1L);
+
+	ret |= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING,
+			WM8994_AIF1DAC1R_TO_DAC1R);
+
+	 /* GPIO Settings for AIF1 */
+
+	ret |=  wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT
+				| WM8994_GPIO_FUNCTION_I2S_CLK
+				| WM8994_GPIO_INPUT_DEBOUNCE);
+
+	ret |= wm8994_init_volume_aif1_dac1();
 	if (ret < 0)
 		goto err;
 

@@ -813,11 +794,11 @@ int wm8994_init(const void *blob, enum en_audio_interface aif_id,
 	g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
 	wm8994_i2c_init(pcodec_info->i2c_bus);

drivers/sound/wm8994.c int wm8994_init(const void *blob, enum en_audio_interface aif_id, · line 802

Quoted 10 lines
drivers/sound/wm8994.c +3 -3
 
-	if (pcodec_info->codec_type == CODEC_WM_8994)
+	if (pcodec_info->codec_type == CODEC_WM_8994) {
 		g_wm8994_info.type = WM8994;
-	else {
+	} else {
 		debug("%s: Codec id [%d] not defined\n", __func__,
-				pcodec_info->codec_type);
+		      pcodec_info->codec_type);
 		return -1;

unrelated change.

Quoted 25 lines
drivers/sound/wm8994.c +0 -0
 	}
drivers/sound/wm8994_registers.h +4 -0
index 1e987c2..debb658 100644
@@ -13,6 +13,7 @@
 #define WM8994_SOFTWARE_RESET                   0x00
 #define WM8994_POWER_MANAGEMENT_1               0x01
 #define WM8994_POWER_MANAGEMENT_2               0x02
+#define WM8994_POWER_MANAGEMENT_4		0x04
 #define WM8994_POWER_MANAGEMENT_5               0x05
 #define WM8994_LEFT_OUTPUT_VOLUME               0x1C
 #define WM8994_RIGHT_OUTPUT_VOLUME              0x1D

@@ -38,6 +39,9 @@
 #define WM8994_AIF2_CONTROL_2                   0x311
 #define WM8994_AIF2_MASTER_SLAVE                0x312
 #define WM8994_AIF2_BCLK                        0x313
+#define WM8994_AIF1_DAC_LEFT_VOLUME             0x402
+#define WM8994_AIF1_DAC_RIGHT_VOLUME            0x403
+#define WM8994_AIF1_DAC_FILTERS_1               0x420
 #define WM8994_AIF2_DAC_LEFT_VOLUME             0x502
 #define WM8994_AIF2_DAC_RIGHT_VOLUME            0x503
 #define WM8994_AIF2_DAC_FILTERS_1               0x520

drivers/sound/wm8994_registers.h line 53

Quoted 5 lines
drivers/sound/wm8994_registers.h +2 -0
@@ -45,6 +49,8 @@
 #define WM8994_DAC1_RIGHT_MIXER_ROUTING         0x602
 #define WM8994_DAC1_LEFT_VOLUME                 0x610
 #define WM8994_DAC1_RIGHT_VOLUME                0x611
+#define WM8994_OVERSAMPLING	                0x620
+#define WM8994_GPIO_1                           0x700

please use tab.

Quoted 13 lines
drivers/sound/wm8994_registers.h +2 -0
 #define WM8994_GPIO_3                           0x702
 #define WM8994_GPIO_4                           0x703
 #define WM8994_GPIO_5                           0x704

@@ -75,6 +81,8 @@
 #define WM8994_BIAS_ENA                         0x0001
 /* BIAS_ENA */
 #define WM8994_BIAS_ENA_MASK                    0x0001
+#define WM8994_BIAS_ENA_SHIFT                        0
+#define WM8994_BIAS_ENA_WIDTH                        1
 
 /*
  * R2 (0x02) - Power Management (2)

drivers/sound/wm8994_registers.h line 97

Quoted 8 lines
drivers/sound/wm8994_registers.h +5 -0
@@ -82,21 +90,35 @@
 /* OPCLK_ENA */
 #define WM8994_OPCLK_ENA                        0x0800
 
+#define WM8994_TSHUT_ENA                        0x4000
+#define WM8994_MIXINL_ENA                       0x0200
+#define WM8994_MIXINR_ENA                       0x0100
+#define WM8994_IN2L_ENA                         0x0080
+#define WM8994_IN2R_ENA                         0x0020

please use tab.

Quoted 34 lines
drivers/sound/wm8994_registers.h +15 -6
+
+/*
+ * R5 (0x04) - Power Management (4)
+ */
+#define WM8994_ADCL_ENA				0x0001
+#define WM8994_ADCR_ENA				0x0002
+#define WM8994_AIF1ADC1R_ENA			0x0100
+#define WM8994_AIF1ADC1L_ENA			0x0200
+
 /*
  * R5 (0x05) - Power Management (5)
  */
-/* AIF2DACL_ENA */
-#define WM8994_AIF2DACL_ENA                     0x2000
-#define WM8994_AIF2DACL_ENA_MASK                0x2000
-/* AIF2DACR_ENA */
-#define WM8994_AIF2DACR_ENA                     0x1000
-#define WM8994_AIF2DACR_ENA_MASK                0x1000
 /* DAC1L_ENA */
 #define WM8994_DAC1L_ENA                        0x0002
 #define WM8994_DAC1L_ENA_MASK                   0x0002
 /* DAC1R_ENA */
 #define WM8994_DAC1R_ENA                        0x0001
 #define WM8994_DAC1R_ENA_MASK                   0x0001
+/* AIF1DACL_ENA */
+#define WM8994_AIF1DACL_ENA                     0x0200
+#define WM8994_AIF1DACL_ENA_MASK                0x0200
+/* AIF1DACR_ENA */
+#define WM8994_AIF1DACR_ENA                     0x0100
+#define WM8994_AIF1DACR_ENA_MASK                0x0100
 
 /*
  * R45 (0x2D) - Output Mixer (1)

drivers/sound/wm8994_registers.h line 197

Quoted 9 lines
drivers/sound/wm8994_registers.h +3 -3
@@ -170,14 +192,14 @@
 /*
  * R520 (0x208) - Clocking (1)
  */
-/* AIF2DSPCLK_ENA */
-#define WM8994_AIF2DSPCLK_ENA                   0x0004
-#define WM8994_AIF2DSPCLK_ENA_MASK              0x0004
+/* AIF1DSPCLK_ENA */
+#define WM8994_AIF1DSPCLK_ENA                   0x0008
+#define WM8994_AIF1DSPCLK_ENA_MASK              0x0008

please use tab.

Quoted 38 lines
drivers/sound/wm8994_registers.h +1 -22
 /* SYSDSPCLK_ENA */
 #define WM8994_SYSDSPCLK_ENA                    0x0002
 #define WM8994_SYSDSPCLK_ENA_MASK               0x0002
 /* SYSCLK_SRC */
-#define WM8994_SYSCLK_SRC                       0x0001
+#define WM8994_SYSCLK_SRC                       0x0000
 
 /*
  * R521 (0x209) - Clocking (2)

@@ -228,27 +250,6 @@
 #define WM8994_AIF1_BCLK_DIV_SHIFT                   4
 
 /*
- * R1282 (0x502) - AIF2 DAC Left Volume
- */
-/* AIF2DAC_VU */
-#define WM8994_AIF2DAC_VU                       0x0100
-#define WM8994_AIF2DAC_VU_MASK                  0x0100
-/* AIF2DACL_VOL - [7:0] */
-#define WM8994_AIF2DACL_VOL_MASK                0x00FF
-
-/*
- * R1283 (0x503) - AIF2 DAC Right Volume
- */
-/* AIF2DACR_VOL - [7:0] */
-#define WM8994_AIF2DACR_VOL_MASK                0x00FF
-
-/*
- * R1312 (0x520) - AIF2 DAC Filters (1)
- */
-/* AIF2DAC_MUTE */
-#define WM8994_AIF2DAC_MUTE_MASK                0x0200
-
-/*
  * R1537 (0x601) - DAC1 Left Mixer Routing
  */
 /* AIF2DACL_TO_DAC1L */

drivers/sound/wm8994_registers.h line 267

Quoted 5 lines
drivers/sound/wm8994_registers.h +2 -0
@@ -262,6 +263,11 @@
 #define WM8994_AIF2DACR_TO_DAC1R                0x0004
 #define WM8994_AIF2DACR_TO_DAC1R_MASK           0x0004
 
+/* AIF1DAC1L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L               0x0001

please use tab.

drivers/sound/wm8994_registers.h line 270

Quoted 3 lines
drivers/sound/wm8994_registers.h +3 -0
+
+/* AIF1DAC1R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R               0x0001

please use tab.

drivers/sound/wm8994_registers.h line 294

Quoted 9 lines
drivers/sound/wm8994_registers.h +1 -1
 /*
  * R1552 (0x610) - DAC1 Left Volume
  */

@@ -285,11 +291,12 @@
  *  GPIO
  */
 /* OUTPUT PIN */
-#define WM8994_GPIO_DIR_OUTPUT                   0x8000
+#define WM8994_GPIO_DIR_OUTPUT                  0x8000

please use tab.

drivers/sound/wm8994_registers.h line 301

Quoted 10 lines
drivers/sound/wm8994_registers.h +4 -3
 /* GPIO PIN MASK */
-#define WM8994_GPIO_DIR_MASK                     0xFFE0
+#define WM8994_GPIO_DIR_MASK			0xFFE0
 /* I2S CLK */
-#define WM8994_GPIO_FUNCTION_I2S_CLK             0x0000
+#define WM8994_GPIO_FUNCTION_I2S_CLK		0x0001
+#define WM8994_GPIO_INPUT_DEBOUNCE		0x0100
 /* GPn FN */
-#define WM8994_GPIO_FUNCTION_MASK                0x001F
+#define WM8994_GPIO_FUNCTION_MASK               0x001F

please use tab.

drivers/sound/wm8994_registers.h line 302

Quoted 2 lines
drivers/sound/wm8994_registers.h +0 -0
 #endif

Thanks,
Minkyu Kang.

author
#3 lore raw

PATCH v2 2/6 DTS: Addition of I2S0 channel and replacing I2S1

In reply to Dani Krishna Mohan

This patch enables default I2S0 channel and replaces I2S1. I2S platform parameter has been moved to a common file viz exynos5.dtsi.

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- None

 arch/arm/dts/exynos5250.dtsi              |   10 ++++++++--
 board/samsung/dts/exynos5250-smdk5250.dts |    8 +-------
 board/samsung/dts/exynos5250-snow.dts     |    8 +-------
 3 files changed, 10 insertions(+), 16 deletions(-)
arch/arm/dts/exynos5250.dtsi +8 -2
index 4fff5e3..da7ce24 100644
@@ -93,9 +93,15 @@
 		interrupts = <0 63 0>;
 	};
 
-	sound at 12d60000 {
+	sound at 3830000 {
 		compatible = "samsung,exynos-sound";
-		reg = <0x12d60000 0x20>;
+		reg = <0x3830000 0x50>;
+		samsung,i2s-epll-clock-frequency = <192000000>;
+		samsung,i2s-sampling-rate = <48000>;
+		samsung,i2s-bits-per-sample = <16>;
+		samsung,i2s-channels = <2>;
+		samsung,i2s-lr-clk-framesize = <256>;
+		samsung,i2s-bit-clk-framesize = <32>;
 	};
 
 	spi at 12d20000 {
board/samsung/dts/exynos5250-smdk5250.dts +1 -7
index 80ffe30..0067130 100644
@@ -49,13 +49,7 @@
 		};
 	};
 
-	sound at 12d60000 {
-		samsung,i2s-epll-clock-frequency = <192000000>;
-		samsung,i2s-sampling-rate = <48000>;
-		samsung,i2s-bits-per-sample = <16>;
-		samsung,i2s-channels = <2>;
-		samsung,i2s-lr-clk-framesize = <256>;
-		samsung,i2s-bit-clk-framesize = <32>;
+	sound at 3830000 {
 		samsung,codec-type = "wm8994";
 	};
board/samsung/dts/exynos5250-snow.dts +1 -7
index dca3386..9e258fd 100644
@@ -65,13 +65,7 @@
 		};
 	};
 
-	sound at 12d60000 {
-		samsung,i2s-epll-clock-frequency = <192000000>;
-		samsung,i2s-sampling-rate = <48000>;
-		samsung,i2s-bits-per-sample = <16>;
-		samsung,i2s-channels = <2>;
-		samsung,i2s-lr-clk-framesize = <256>;
-		samsung,i2s-bit-clk-framesize = <32>;
+	sound at 3830000 {
 		samsung,codec-type = "max98095";
 	};
Signature · 1 line
1.7.9.5
author
#4 lore raw

PATCH v2 3/6 ARM: Change from I2S1 to I2S0 for audio on SMDK5250

In reply to Dani Krishna Mohan

This patch makes the necessary changes for making use of I2S0 channel instead of I2S1 channel on smdk board. This changes are done to maintain the uniformity to use I2S0 channel.

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- None

 arch/arm/cpu/armv7/exynos/clock.c         |   13 +++++++++----
 arch/arm/cpu/armv7/exynos/pinmux.c        |   15 +++++++++++++--
 arch/arm/include/asm/arch-exynos/clock.h  |    8 +++++---
 arch/arm/include/asm/arch-exynos/cpu.h    |    2 ++
 arch/arm/include/asm/arch-exynos/periph.h |    1 +
 5 files changed, 30 insertions(+), 9 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +9 -4
index 0cb1a61..2a1b681 100644
@@ -282,6 +282,9 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 		src = readl(&clk->src_peric0);
 		div = readl(&clk->div_peric3);
 		break;
+	case PERIPH_ID_I2S0:
+		src = readl(&clk->src_mau);
+		div = readl(&clk->div_mau);
 	case PERIPH_ID_SPI0:
 	case PERIPH_ID_SPI1:
 		src = readl(&clk->src_peric1);

@@ -1151,8 +1154,10 @@ void exynos5_set_i2s_clk_source(void)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 
-	clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+	setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
+	clrsetbits_le32(&clk->src_mau, AUDIO_SEL_MASK,
 			(CLK_SRC_SCLK_EPLL));
+	setbits_le32(EXYNOS_AUDSS, CLKMUX_ASS);
 }
 
 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,

@@ -1169,13 +1174,13 @@ int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
 	}
 
 	div = (src_frq / dst_frq);
-	if (div > AUDIO_1_RATIO_MASK) {
+	if (div > AUDIO_RATIO_MASK) {
 		debug("%s: Frequency ratio is out of range\n", __func__);
 		debug("src frq = %d des frq = %d ", src_frq, dst_frq);
 		return -1;
 	}
-	clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
-				(div & AUDIO_1_RATIO_MASK));
+	clrsetbits_le32(&clk->div_mau, AUDIO_RATIO_MASK,
+			(div & AUDIO_RATIO_MASK));
 	return 0;
 }
arch/arm/cpu/armv7/exynos/pinmux.c +13 -2
index 1b05ebf..59f445a 100644
@@ -221,9 +221,19 @@ static void exynos5_i2s_config(int peripheral)
 	int i;
 	struct exynos5_gpio_part1 *gpio1 =
 		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	struct exynos5_gpio_part4 *gpio4 =
+		(struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
 
-	for (i = 0; i < 5; i++)
-		s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+	switch (peripheral) {
+	case PERIPH_ID_I2S0:
+		for (i = 0; i < 5; i++)
+			s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
+		break;
+	case PERIPH_ID_I2S1:
+		for (i = 0; i < 5; i++)
+			s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+		break;
+	}
 }
 
 void exynos5_spi_config(int peripheral)

@@ -296,6 +306,7 @@ static int exynos5_pinmux_config(int peripheral, int flags)
 	case PERIPH_ID_I2C7:
 		exynos5_i2c_config(peripheral, flags);
 		break;
+	case PERIPH_ID_I2S0:
 	case PERIPH_ID_I2S1:
 		exynos5_i2s_config(peripheral);
 		break;
arch/arm/include/asm/arch-exynos/clock.h +5 -3
index 2b97b9a..d55424e 100644
@@ -873,11 +873,13 @@ struct set_epll_con_val {
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT	29  /* EPLL Locked bit position*/
 #define TIMEOUT_EPLL_LOCK		1000
 
-#define AUDIO_0_RATIO_MASK		0x0f
-#define AUDIO_1_RATIO_MASK		0x0f
+#define AUDIO_RATIO_MASK		0x0f
+
+#define AUDIO_SEL_MASK			0xf
 
-#define AUDIO1_SEL_MASK			0xf
 #define CLK_SRC_SCLK_EPLL		0x7
+#define CLK_SRC_MOUT_EPLL		(1<<12)
+#define CLKMUX_ASS			(1<<0)
 
 /* CON0 bit-fields */
 #define EPLL_CON0_MDIV_MASK		0x1ff
arch/arm/include/asm/arch-exynos/cpu.h +2 -0
index cb924fb..552b64f 100644
@@ -89,6 +89,8 @@
 /* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING		0x10000
 
+#define EXYNOS_AUDSS			0x03810000
+
 #define EXYNOS5_GPIO_PART4_BASE		0x03860000
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
arch/arm/include/asm/arch-exynos/periph.h +1 -0
index 9952155..64bd8b7 100644
@@ -34,6 +34,7 @@ enum periph_id {
 	PERIPH_ID_SDMMC1,
 	PERIPH_ID_SDMMC2,
 	PERIPH_ID_SDMMC3,
+	PERIPH_ID_I2S0 = 98,
 	PERIPH_ID_I2S1 = 99,
 
 	/* Since following peripherals do
Signature · 1 line
1.7.9.5
#5 lore raw

PATCH v2 3/6 ARM: Change from I2S1 to I2S0 for audio on SMDK5250

Quoted 30 lines · Dani Krishna Mohan

This patch makes the necessary changes for making use of I2S0 channel instead of I2S1 channel on smdk board. This changes are done to maintain the uniformity to use I2S0 channel.

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- None

 arch/arm/cpu/armv7/exynos/clock.c         |   13 +++++++++----
 arch/arm/cpu/armv7/exynos/pinmux.c        |   15 +++++++++++++--
 arch/arm/include/asm/arch-exynos/clock.h  |    8 +++++---
 arch/arm/include/asm/arch-exynos/cpu.h    |    2 ++
 arch/arm/include/asm/arch-exynos/periph.h |    1 +
 5 files changed, 30 insertions(+), 9 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +3 -0
index 0cb1a61..2a1b681 100644
@@ -282,6 +282,9 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 		src = readl(&clk->src_peric0);
 		div = readl(&clk->div_peric3);
 		break;
+	case PERIPH_ID_I2S0:
+		src = readl(&clk->src_mau);
+		div = readl(&clk->div_mau);
 	case PERIPH_ID_SPI0:
 	case PERIPH_ID_SPI1:
 		src = readl(&clk->src_peric1);

arch/arm/cpu/armv7/exynos/clock.c void exynos5_set_i2s_clk_source(void) · line 1154

Quoted 4 lines
arch/arm/cpu/armv7/exynos/clock.c +0 -1
@@ -1151,8 +1154,10 @@ void exynos5_set_i2s_clk_source(void)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 
-	clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,

you should support audio1 also.
please do not replace, support both of them.

arch/arm/cpu/armv7/exynos/clock.c void exynos5_set_i2s_clk_source(void) · line 1160

Quoted 4 lines
arch/arm/cpu/armv7/exynos/clock.c +3 -0
+	setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
+	clrsetbits_le32(&clk->src_mau, AUDIO_SEL_MASK,
 			(CLK_SRC_SCLK_EPLL));
+	setbits_le32(EXYNOS_AUDSS, CLKMUX_ASS);

Don't access base address directly.

Quoted 7 lines
arch/arm/cpu/armv7/exynos/clock.c +0 -0
 }
 
 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,

@@ -1169,13 +1174,13 @@ int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
 	}
 
 	div = (src_frq / dst_frq);

arch/arm/cpu/armv7/exynos/clock.c int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, · line 1183

Quoted 10 lines
arch/arm/cpu/armv7/exynos/clock.c +3 -3
-	if (div > AUDIO_1_RATIO_MASK) {
+	if (div > AUDIO_RATIO_MASK) {
 		debug("%s: Frequency ratio is out of range\n", __func__);
 		debug("src frq = %d des frq = %d ", src_frq, dst_frq);
 		return -1;
 	}
-	clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
-				(div & AUDIO_1_RATIO_MASK));
+	clrsetbits_le32(&clk->div_mau, AUDIO_RATIO_MASK,
+			(div & AUDIO_RATIO_MASK));

ditto.
please support both of them.

Quoted 45 lines
arch/arm/cpu/armv7/exynos/clock.c +0 -0
 	return 0;
 }
arch/arm/cpu/armv7/exynos/pinmux.c +13 -2
index 1b05ebf..59f445a 100644
@@ -221,9 +221,19 @@ static void exynos5_i2s_config(int peripheral)
 	int i;
 	struct exynos5_gpio_part1 *gpio1 =
 		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	struct exynos5_gpio_part4 *gpio4 =
+		(struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
 
-	for (i = 0; i < 5; i++)
-		s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+	switch (peripheral) {
+	case PERIPH_ID_I2S0:
+		for (i = 0; i < 5; i++)
+			s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
+		break;
+	case PERIPH_ID_I2S1:
+		for (i = 0; i < 5; i++)
+			s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+		break;
+	}
 }
 
 void exynos5_spi_config(int peripheral)

@@ -296,6 +306,7 @@ static int exynos5_pinmux_config(int peripheral, int flags)
 	case PERIPH_ID_I2C7:
 		exynos5_i2c_config(peripheral, flags);
 		break;
+	case PERIPH_ID_I2S0:
 	case PERIPH_ID_I2S1:
 		exynos5_i2s_config(peripheral);
 		break;
arch/arm/include/asm/arch-exynos/clock.h +0 -0
index 2b97b9a..d55424e 100644
@@ -873,11 +873,13 @@ struct set_epll_con_val {
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT	29  /* EPLL Locked bit position*/
 #define TIMEOUT_EPLL_LOCK		1000

arch/arm/include/asm/arch-exynos/clock.h struct set_epll_con_val { · line 882

Quoted 10 lines
arch/arm/include/asm/arch-exynos/clock.h +5 -3
-#define AUDIO_0_RATIO_MASK		0x0f
-#define AUDIO_1_RATIO_MASK		0x0f
+#define AUDIO_RATIO_MASK		0x0f
+
+#define AUDIO_SEL_MASK			0xf
 
-#define AUDIO1_SEL_MASK			0xf
 #define CLK_SRC_SCLK_EPLL		0x7
+#define CLK_SRC_MOUT_EPLL		(1<<12)
+#define CLKMUX_ASS			(1<<0)

Please add prefix AUDIO.

arch/arm/include/asm/arch-exynos/cpu.h line 92

Quoted 12 lines
arch/arm/include/asm/arch-exynos/clock.h +0 -0
 /* CON0 bit-fields */
 #define EPLL_CON0_MDIV_MASK		0x1ff
arch/arm/include/asm/arch-exynos/cpu.h +1 -0
index cb924fb..552b64f 100644
@@ -89,6 +89,8 @@
 /* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING		0x10000
 
+#define EXYNOS_AUDSS			0x03810000

please fix naming. It's a exynos5 section.
AUD is far too vague. AUDIO please.

arch/arm/include/asm/arch-exynos/cpu.h line 93

Quoted 1 line
arch/arm/include/asm/arch-exynos/cpu.h +1 -0
+

please remove blank line.

Quoted 9 lines
arch/arm/include/asm/arch-exynos/cpu.h +0 -0
 #define EXYNOS5_GPIO_PART4_BASE		0x03860000
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
arch/arm/include/asm/arch-exynos/periph.h +0 -0
index 9952155..64bd8b7 100644

arch/arm/include/asm/arch-exynos/periph.h enum periph_id { · line 40

Quoted 7 lines
arch/arm/include/asm/arch-exynos/periph.h +1 -0
@@ -34,6 +34,7 @@ enum periph_id {
 	PERIPH_ID_SDMMC1,
 	PERIPH_ID_SDMMC2,
 	PERIPH_ID_SDMMC3,
+	PERIPH_ID_I2S0 = 98,
 	PERIPH_ID_I2S1 = 99,
 
 	/* Since following peripherals do

Thanks,
Minkyu Kang.

author
#6 lore raw

PATCH v2 4/6 Sound: I2S: Replacing I2S1 with I2S0 channel.

In reply to Dani Krishna Mohan

This patch makes required changes to make use of I2S0 channel instead of I2S1 channel on exynos5250.

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- None

 arch/arm/include/asm/arch-exynos/i2s-regs.h |    6 ++++++
 drivers/sound/samsung-i2s.c                 |   16 ++++++++++------
 2 files changed, 16 insertions(+), 6 deletions(-)
arch/arm/include/asm/arch-exynos/i2s-regs.h +6 -0
index 613b9b7..4a4a7a0 100644
@@ -8,10 +8,12 @@
 #ifndef __I2S_REGS_H__
 #define __I2S_REGS_H__
 
+#define CON_RESET		(1 << 31)
 #define CON_TXFIFO_FULL		(1 << 8)
 #define CON_TXCH_PAUSE		(1 << 4)
 #define CON_ACTIVE		(1 << 0)
 
+#define MOD_OP_CLK		(3 << 30)
 #define MOD_BLCP_SHIFT		24
 #define MOD_BLCP_16BIT		(0 << MOD_BLCP_SHIFT)
 #define MOD_BLCP_8BIT		(1 << MOD_BLCP_SHIFT)

@@ -24,6 +26,7 @@
 #define MOD_BLC_MASK		(3 << 13)
 
 #define MOD_SLAVE		(1 << 11)
+#define MOD_RCLKSRC		(0 << 10)
 #define MOD_MASK		(3 << 8)
 #define MOD_LR_LLOW		(0 << 7)
 #define MOD_LR_RLOW		(1 << 7)

@@ -47,4 +50,7 @@
 #define FIC_TXFLUSH		(1 << 15)
 #define FIC_RXFLUSH		(1 << 7)
 
+#define PSREN			(1 << 15)
+#define PSVAL			(3 << 8)
+
 #endif /* __I2S_REGS_H__ */
drivers/sound/samsung-i2s.c +10 -6
index 49921e5..8e8a2bc 100644
@@ -303,21 +303,25 @@ int i2s_tx_init(struct i2stx_info *pi2s_tx)
 				(struct i2s_reg *)pi2s_tx->base_address;
 
 	/* Initialize GPIO for I2s */
-	exynos_pinmux_config(PERIPH_ID_I2S1, 0);
+	exynos_pinmux_config(PERIPH_ID_I2S0, 0);
 
 	/* Set EPLL Clock */
-	ret = set_epll_clk(pi2s_tx->audio_pll_clk);
+	ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4);
 	if (ret != 0) {
 		debug("%s: epll clock set rate falied\n", __func__);
 		return -1;
 	}
 
-	/* Select Clk Source for Audio1 */
+	/* Select Clk Source for Audio0 */
 	set_i2s_clk_source();
 
-	/* Set Prescaler to get MCLK */
-	set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
-				(pi2s_tx->samplingrate * (pi2s_tx->rfs)));
+	/*Reset the i2s module */
+	writel(CON_RESET, &i2s_reg->con);
+
+	writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod);
+
+	/* set i2s prescaler */
+	writel(PSREN | PSVAL, &i2s_reg->psr);
 
 	/* Configure I2s format */
 	ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
Signature · 1 line
1.7.9.5
#7 lore raw

PATCH v2 4/6 Sound: I2S: Replacing I2S1 with I2S0 channel.

Quoted 49 lines · Dani Krishna Mohan

This patch makes required changes to make use of I2S0 channel instead of I2S1 channel on exynos5250.

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- None

 arch/arm/include/asm/arch-exynos/i2s-regs.h |    6 ++++++
 drivers/sound/samsung-i2s.c                 |   16 ++++++++++------
 2 files changed, 16 insertions(+), 6 deletions(-)
arch/arm/include/asm/arch-exynos/i2s-regs.h +6 -0
index 613b9b7..4a4a7a0 100644
@@ -8,10 +8,12 @@
 #ifndef __I2S_REGS_H__
 #define __I2S_REGS_H__
 
+#define CON_RESET		(1 << 31)
 #define CON_TXFIFO_FULL		(1 << 8)
 #define CON_TXCH_PAUSE		(1 << 4)
 #define CON_ACTIVE		(1 << 0)
 
+#define MOD_OP_CLK		(3 << 30)
 #define MOD_BLCP_SHIFT		24
 #define MOD_BLCP_16BIT		(0 << MOD_BLCP_SHIFT)
 #define MOD_BLCP_8BIT		(1 << MOD_BLCP_SHIFT)

@@ -24,6 +26,7 @@
 #define MOD_BLC_MASK		(3 << 13)
 
 #define MOD_SLAVE		(1 << 11)
+#define MOD_RCLKSRC		(0 << 10)
 #define MOD_MASK		(3 << 8)
 #define MOD_LR_LLOW		(0 << 7)
 #define MOD_LR_RLOW		(1 << 7)

@@ -47,4 +50,7 @@
 #define FIC_TXFLUSH		(1 << 15)
 #define FIC_RXFLUSH		(1 << 7)
 
+#define PSREN			(1 << 15)
+#define PSVAL			(3 << 8)
+
 #endif /* __I2S_REGS_H__ */
drivers/sound/samsung-i2s.c +0 -0
index 49921e5..8e8a2bc 100644

drivers/sound/samsung-i2s.c int i2s_tx_init(struct i2stx_info *pi2s_tx) · line 306

Quoted 5 lines
drivers/sound/samsung-i2s.c +1 -1
@@ -303,21 +303,25 @@ int i2s_tx_init(struct i2stx_info *pi2s_tx)
 				(struct i2s_reg *)pi2s_tx->base_address;
 
 	/* Initialize GPIO for I2s */
-	exynos_pinmux_config(PERIPH_ID_I2S1, 0);
+	exynos_pinmux_config(PERIPH_ID_I2S0, 0);

please don't replacing.
please adds support i2c0.

Quoted 17 lines
drivers/sound/samsung-i2s.c +3 -5
 	/* Set EPLL Clock */
-	ret = set_epll_clk(pi2s_tx->audio_pll_clk);
+	ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4);
 	if (ret != 0) {
 		debug("%s: epll clock set rate falied\n", __func__);
 		return -1;
 	}
 
-	/* Select Clk Source for Audio1 */
+	/* Select Clk Source for Audio0 */
 	set_i2s_clk_source();
 
-	/* Set Prescaler to get MCLK */
-	set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
-				(pi2s_tx->samplingrate * (pi2s_tx->rfs)));
+	/*Reset the i2s module */

drivers/sound/samsung-i2s.c int i2s_tx_init(struct i2stx_info *pi2s_tx)

Quoted 10 lines
drivers/sound/samsung-i2s.c +6 -0
+	writel(CON_RESET, &i2s_reg->con);
+
+	writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod);
+
+	/* set i2s prescaler */
+	writel(PSREN | PSVAL, &i2s_reg->psr);
 
 	/* Configure I2s format */
 	ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |

Thanks,
Minkyu Kang.

author
#8 lore raw

PATCH v2 5/6 DTS: Addition of GPIO chipselect for MAX98095

In reply to Dani Krishna Mohan

This patch enables the chipselect for MAX98095 audio codec in snow.

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- New patch added to V2

 board/samsung/dts/exynos5250-snow.dts |    1 +
 1 file changed, 1 insertion(+)
board/samsung/dts/exynos5250-snow.dts +1 -0
index 9e258fd..5a39044 100644
@@ -67,6 +67,7 @@
 
 	sound at 3830000 {
 		samsung,codec-type = "max98095";
+		codec-enable-gpio = <&gpio 0xb7 0>;
 	};
 
 	i2c at 12cd0000 {
Signature · 1 line
1.7.9.5
author
#9 lore raw

PATCH v2 6/6 Sound: MAX98095: Support I2S0 channel

In reply to Dani Krishna Mohan

This patch modifies the MAX98095 audio codec to support
I2S0 channel in codec slave mode.

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- New patch added to V2

 drivers/sound/max98095.c |   29 +++++++++++------------------
 1 file changed, 11 insertions(+), 18 deletions(-)
drivers/sound/max98095.c +11 -18
index d69db58..a8b0319 100644
@@ -145,11 +145,11 @@ static int max98095_hw_params(struct max98095_priv *max98095,
 
 	switch (bits_per_sample) {
 	case 16:
-		error = max98095_update_bits(M98095_034_DAI2_FORMAT,
+		error = max98095_update_bits(M98095_02A_DAI1_FORMAT,
 			M98095_DAI_WS, 0);
 		break;
 	case 24:
-		error = max98095_update_bits(M98095_034_DAI2_FORMAT,
+		error = max98095_update_bits(M98095_02A_DAI1_FORMAT,
 			M98095_DAI_WS, M98095_DAI_WS);
 		break;
 	default:

@@ -165,15 +165,15 @@ static int max98095_hw_params(struct max98095_priv *max98095,
 	}
 	max98095->rate = rate;
 
-	error |= max98095_update_bits(M98095_031_DAI2_CLKMODE,
+	error |= max98095_update_bits(M98095_027_DAI1_CLKMODE,
 		M98095_CLKMODE_MASK, regval);
 
 	/* Update sample rate mode */
 	if (rate < 50000)
-		error |= max98095_update_bits(M98095_038_DAI2_FILTERS,
+		error |= max98095_update_bits(M98095_02E_DAI1_FILTERS,
 			M98095_DAI_DHF, 0);
 	else
-		error |= max98095_update_bits(M98095_038_DAI2_FILTERS,
+		error |= max98095_update_bits(M98095_02E_DAI1_FILTERS,
 			M98095_DAI_DHF, M98095_DAI_DHF);
 
 	if (error < 0) {

@@ -248,9 +248,9 @@ static int max98095_set_fmt(struct max98095_priv *max98095, int fmt)
 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 	case SND_SOC_DAIFMT_CBS_CFS:
 		/* Slave mode PLL */
-		error |= max98095_i2c_write(M98095_032_DAI2_CLKCFG_HI,
+		error |= max98095_i2c_write(M98095_028_DAI1_CLKCFG_HI,
 					0x80);
-		error |= max98095_i2c_write(M98095_033_DAI2_CLKCFG_LO,
+		error |= max98095_i2c_write(M98095_029_DAI1_CLKCFG_LO,
 					0x00);
 		break;
 	case SND_SOC_DAIFMT_CBM_CFM:

@@ -292,11 +292,11 @@ static int max98095_set_fmt(struct max98095_priv *max98095, int fmt)
 		return -1;
 	}
 
-	error |= max98095_update_bits(M98095_034_DAI2_FORMAT,
+	error |= max98095_update_bits(M98095_02A_DAI1_FORMAT,
 		M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
 		M98095_DAI_WCI, regval);
 
-	error |= max98095_i2c_write(M98095_035_DAI2_CLOCK,
+	error |= max98095_i2c_write(M98095_02B_DAI1_CLOCK,
 		M98095_DAI_BSEL64);
 
 	if (error < 0) {

@@ -386,22 +386,15 @@ static int max98095_device_init(struct max98095_priv *max98095)
 	 * interface2 to DAC
 	 */
 	error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
-		M98095_DAI2M_TO_DACL|M98095_DAI2M_TO_DACR);
+		M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
 
 	error |= max98095_i2c_write(M98095_092_PWR_EN_OUT,
 			M98095_SPK_SPREADSPECTRUM);
-	error |= max98095_i2c_write(M98095_045_CFG_DSP, M98095_DSPNORMAL);
 	error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL);
 
 	error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG,
 			M98095_S1NORMAL|M98095_SDATA);
 
-	error |= max98095_i2c_write(M98095_036_DAI2_IOCFG,
-			M98095_S2NORMAL|M98095_SDATA);
-
-	error |= max98095_i2c_write(M98095_040_DAI3_IOCFG,
-			M98095_S3NORMAL|M98095_SDATA);
-
 	/* take the codec out of the shut down */
 	error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN,
 			M98095_SHDNRUN);

@@ -422,7 +415,7 @@ static int max98095_device_init(struct max98095_priv *max98095)
 
 	/* Enable DAIs */
 	error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30);
-	error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07);
+	error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x01);
 
 err_access:
 	if (error < 0)
Signature · 1 line
1.7.9.5
#10 lore raw

PATCH v2 6/6 Sound: MAX98095: Support I2S0 channel

Quoted 10 lines · Dani Krishna Mohan

This patch modifies the MAX98095 audio codec to support
I2S0 channel in codec slave mode.

Signed-off-by Dani Krishna Mohan <[email protected]>

---
changes in V2:
- New patch added to V2

 drivers/sound/max98095.c |   29 +++++++++++------------------
 1 file changed, 11 insertions(+), 18 deletions(-)

ditto.
Please do not replacing.
Please adds support i2s0.

Thanks,
Minkyu Kang.

#11 lore raw

v2 cover EXYNOS: I2S: Enable I2S0 channel

In reply to Dani Krishna Mohan
Acked-by Rajeshwari Shinde <[email protected]>
Tested-by Rajeshwari Shinde <[email protected]>
Quoted 39 lines · Dani Krishna Mohan

This patch set replaces I2S1 channel with I2S0 channel. Corresponding changes have been done in audio codec to
support I2S0 channel.

Changes in V2:
- Added cover letter.
- Configured GPIO chipselect to enable MAX98095 codec.

Dani Krishna Mohan (6):
Sound: WM8994: Support I2S0 channel
DTS: Addition of I2S0 channel and replacing I2S1
ARM: Change from I2S1 to I2S0 for audio on SMDK5250
Sound: I2S: Replacing I2S1 with I2S0 channel.
DTS: Addition of GPIO chipselect for MAX98095
Sound: MAX98095: Support I2S0 channel

 arch/arm/cpu/armv7/exynos/clock.c           |   13 ++--
 arch/arm/cpu/armv7/exynos/pinmux.c          |   15 ++++-
 arch/arm/dts/exynos5250.dtsi                |   10 ++-
 arch/arm/include/asm/arch-exynos/clock.h    |    8 ++-
 arch/arm/include/asm/arch-exynos/cpu.h      |    2 +
 arch/arm/include/asm/arch-exynos/i2s-regs.h |    6 ++
 arch/arm/include/asm/arch-exynos/periph.h   |    1 +
 board/samsung/dts/exynos5250-smdk5250.dts   |    8 +--
 board/samsung/dts/exynos5250-snow.dts       |    9 +--
 drivers/sound/max98095.c                    |   29 ++++----
 drivers/sound/samsung-i2s.c                 |   16 +++--
 drivers/sound/sound.c                       |    2 +-
 drivers/sound/wm8994.c                      |   95 +++++++++++----------------
 drivers/sound/wm8994_registers.h            |   77 ++++++++++++----------
 14 files changed, 149 insertions(+), 142 deletions(-)

--
1.7.9.5

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Signature · 2 lines
Regards,
Rajeshwari Shinde