OMAP4+: Get rid of internal SRAM handling

PATCH New Rajendra Nayak 4 participants 20 messages Aug 29, 2013 – Sep 3, 2013

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Device tree bindings Arm (32-bit) Arm sub-architectures OMAP2+ support

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Rajendra Nayak

author

2013-08-29 11:23 UTC #0 lore raw

v2 cover OMAP4+: Get rid of internal SRAM handling

v2:
Removed the static iotable mapping for sram done to handle errata I688, and used gen_pool instead.

Make all OMAP DT only platforms (am33xx, am43xx, omap4 and omap5) use drivers/misc/sram.c driver instead of the omap internal implementation for SRAM handling.

Rajendra Nayak (3):
ARM: AM335x: Get rid of unused sram init function
ARM: OMAP4+: Move SRAM data to DT
ARM: OMAP4+: Remove static iotable mappings for SRAM

 Documentation/devicetree/bindings/arm/omap/mpu.txt |    5 ++-
 arch/arm/boot/dts/am33xx.dtsi                      |    5 +--
 arch/arm/boot/dts/am4372.dtsi                      |    5 +++
 arch/arm/boot/dts/omap4.dtsi                       |    6 +++
 arch/arm/boot/dts/omap5.dtsi                       |    8 +++-
 arch/arm/configs/omap2plus_defconfig               |    1 +
 arch/arm/mach-omap2/io.c                           |   17 ---------
 arch/arm/mach-omap2/omap4-common.c                 |   17 ++++++++-
 arch/arm/mach-omap2/sram.c                         |   39 +-------------------
 arch/arm/mach-omap2/sram.h                         |    7 ----
 10 files changed, 42 insertions(+), 68 deletions(-)

Signature · 1 line

1.7.9.5

Rajendra Nayak

author

2013-08-29 11:23 UTC #1 lore raw

PATCH v2 1/3 ARM: AM335x: Get rid of unused sram init function

Remove the empty am33xx_sram_init() function.

Signed-off-by Rajendra Nayak <[email protected]>

---
 arch/arm/mach-omap2/sram.c |    7 -------
 1 file changed, 7 deletions(-)

arch/arm/mach-omap2/sram.c +0 -7

index 4bd0968..305fc2b 100644
@@ -285,11 +285,6 @@ static inline int omap34xx_sram_init(void)
 }
 #endif /* CONFIG_ARCH_OMAP3 */
 
-static inline int am33xx_sram_init(void)
-{
-	return 0;
-}
-
 int __init omap_sram_init(void)
 {
 	omap_detect_sram();

@@ -299,8 +294,6 @@ int __init omap_sram_init(void)
 		omap242x_sram_init();
 	else if (cpu_is_omap2430())
 		omap243x_sram_init();
-	else if (soc_is_am33xx())
-		am33xx_sram_init();
 	else if (cpu_is_omap34xx())
 		omap34xx_sram_init();

Signature · 1 line

1.7.9.5

Rajendra Nayak

author

2013-08-29 11:23 UTC #2 lore raw

PATCH v2 2/3 ARM: OMAP4+: Move SRAM data to DT

In reply to Rajendra Nayak

Use drivers/misc/sram.c driver to manage SRAM on all DT only OMAP platforms (am33xx, am43xx, omap4 and omap5) instead of the existing private plat-omap/sram.c

Address and size related data is removed from mach-omap2/sram.c and now passed to drivers/misc/sram.c from DT.

Users can hence use general purpose allocator apis instead of OMAP private ones to manage and use SRAM.

Signed-off-by Rajendra Nayak <[email protected]>

---
 arch/arm/boot/dts/am33xx.dtsi        |    5 ++---
 arch/arm/boot/dts/am4372.dtsi        |    5 +++++
 arch/arm/boot/dts/omap4.dtsi         |    5 +++++
 arch/arm/boot/dts/omap5.dtsi         |    5 +++++
 arch/arm/configs/omap2plus_defconfig |    1 +
 arch/arm/mach-omap2/sram.c           |   26 +-------------------------
 arch/arm/mach-omap2/sram.h           |    1 -
 7 files changed, 19 insertions(+), 29 deletions(-)

arch/arm/boot/dts/am33xx.dtsi +2 -3

index 38b446b..69cbce9 100644
@@ -482,9 +482,8 @@
 		};
 
 		ocmcram: ocmcram at 40300000 {
-			compatible = "ti,am3352-ocmcram";
-			reg = <0x40300000 0x10000>;
-			ti,hwmods = "ocmcram";
+			compatible = "mmio-sram";
+			reg = <0x40300000 0x10000>; /* 64k */
 		};
 
 		wkup_m3: wkup_m3 at 44d00000 {

arch/arm/boot/dts/am4372.dtsi +5 -0

index ddc1df7..5c8cee1 100644
@@ -64,5 +64,10 @@
 			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
 			reg = <0x44e86000 0x40>;
 		};
+
+		ocmcram: ocmcram at 40300000 {
+			compatible = "mmio-sram";
+			reg = <0x40300000 0x40000>; /* 256k */
+		};
 	};
 };

arch/arm/boot/dts/omap4.dtsi +5 -0

index 22d9f2b..1ba6a77 100644
@@ -126,6 +126,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
+		ocmcram: ocmcram at 40304000 {
+			compatible = "mmio-sram";
+			reg = <0x40304000 0xa000>; /* 40k */
+		};
+
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;

arch/arm/boot/dts/omap5.dtsi +5 -0

index e643620..461ffd8 100644
@@ -119,6 +119,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
+		ocmcram: ocmcram at 40300000 {
+			compatible = "mmio-sram";
+			reg = <0x40300000 0x20000>; /* 128k */
+		};
+
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;

arch/arm/configs/omap2plus_defconfig +1 -0

index 5339e6a..5d4c9b8 100644
@@ -101,6 +101,7 @@ CONFIG_SENSORS_LIS3LV02D=m
 CONFIG_SENSORS_TSL2550=m
 CONFIG_SENSORS_LIS3_I2C=m
 CONFIG_BMP085_I2C=m
+CONFIG_SRAM=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y

arch/arm/mach-omap2/sram.c +1 ~~-25~~

index 305fc2b..d5ecb75 100644
@@ -32,12 +32,6 @@
 
 #define OMAP2_SRAM_PUB_PA	(OMAP2_SRAM_PA + 0xf800)
 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PUB_PA	OMAP4_SRAM_PA
-#else
-#define OMAP4_SRAM_PUB_PA	(OMAP4_SRAM_PA + 0x4000)
-#endif
-#define OMAP5_SRAM_PA		0x40300000
 
 #define SRAM_BOOTLOADER_SZ	0x00

@@ -105,32 +99,14 @@ static void __init omap_detect_sram(void)
 			} else {
 				omap_sram_size = 0x8000; /* 32K */
 			}
-		} else if (cpu_is_omap44xx()) {
-			omap_sram_start = OMAP4_SRAM_PUB_PA;
-			omap_sram_size = 0xa000; /* 40K */
-		} else if (soc_is_omap54xx()) {
-			omap_sram_start = OMAP5_SRAM_PA;
-			omap_sram_size = SZ_128K; /* 128KB */
 		} else {
 			omap_sram_start = OMAP2_SRAM_PUB_PA;
 			omap_sram_size = 0x800; /* 2K */
 		}
 	} else {
-		if (soc_is_am33xx()) {
-			omap_sram_start = AM33XX_SRAM_PA;
-			omap_sram_size = 0x10000; /* 64K */
-		} else if (soc_is_am43xx()) {
-			omap_sram_start = AM33XX_SRAM_PA;
-			omap_sram_size = SZ_256K;
-		} else if (cpu_is_omap34xx()) {
+		if (cpu_is_omap34xx()) {
 			omap_sram_start = OMAP3_SRAM_PA;
 			omap_sram_size = 0x10000; /* 64K */
-		} else if (cpu_is_omap44xx()) {
-			omap_sram_start = OMAP4_SRAM_PA;
-			omap_sram_size = 0xe000; /* 56K */
-		} else if (soc_is_omap54xx()) {
-			omap_sram_start = OMAP5_SRAM_PA;
-			omap_sram_size = SZ_128K; /* 128KB */
 		} else {
 			omap_sram_start = OMAP2_SRAM_PA;
 			if (cpu_is_omap242x())

arch/arm/mach-omap2/sram.h +0 -1

index ca7277c..3f83b80 100644
@@ -80,4 +80,3 @@ static inline void omap_push_sram_idle(void) {}
 #else
 #define OMAP4_SRAM_PA		0x40300000
 #endif
-#define AM33XX_SRAM_PA		0x40300000

Signature · 1 line

1.7.9.5

Sekhar Nori

2013-08-29 13:26 UTC #3 lore raw

PATCH v2 2/3 ARM: OMAP4+: Move SRAM data to DT

arch/arm/boot/dts/omap4.dtsi line 129

Quoted 9 lines · Rajendra Nayak

arch/arm/boot/dts/omap4.dtsi +1 -0

index 22d9f2b..1ba6a77 100644
@@ -126,6 +126,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
+		ocmcram: ocmcram at 40304000 {

This can now be changed to 0x40300000 now that you have moved to gen_pool_alloc()?

Thanks,
Sekhar

Santosh Shilimkar

2013-08-29 13:31 UTC #4 lore raw

PATCH v2 2/3 ARM: OMAP4+: Move SRAM data to DT

Quoted 9 lines · Sekhar Nori

Quoted 8 lines · Rajendra Nayak
arch/arm/boot/dts/omap4.dtsi +0 -0
index 22d9f2b..1ba6a77 100644
@@ -126,6 +126,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 

Quoted 5 lines

arch/arm/boot/dts/omap4.dtsi line 129
Quoted 1 line
arch/arm/boot/dts/omap4.dtsi +1 -0
+		ocmcram: ocmcram at 40304000 {
This can now be changed to 0x40300000 now that you have moved to gen_pool_alloc()?

NO.
It won't work on secure devices since first 16 KB is occupied for default configuration. Its not worth trouble also to handle secure/non-secure considering the use of SRAM which is actually just limited to errata. 40304000 will work for both devices.

Regards,
Santosh

Sekhar Nori

2013-08-29 13:44 UTC #5 lore raw

PATCH v2 2/3 ARM: OMAP4+: Move SRAM data to DT

Quoted 15 lines · Santosh Shilimkar

Quoted 9 lines · Sekhar Nori
Quoted 8 lines · Rajendra Nayak
arch/arm/boot/dts/omap4.dtsi +0 -0
index 22d9f2b..1ba6a77 100644
@@ -126,6 +126,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
Quoted 5 lines
arch/arm/boot/dts/omap4.dtsi line 129
Quoted 1 line
arch/arm/boot/dts/omap4.dtsi +1 -0
+		ocmcram: ocmcram at 40304000 {
This can now be changed to 0x40300000 now that you have moved to gen_pool_alloc()?

Quoted 5 lines

NO.
It won't work on secure devices since first 16 KB is occupied for default configuration. Its not worth trouble also to handle secure/non-secure considering the use of SRAM which is actually just limited to errata. 40304000 will work for both devices.

Okay, the same problem is not applicable to OMAP5 and other devices? I am okay with this as such, may be just add a comment explaining why there is an offset.

Thanks,
Sekhar

Santosh Shilimkar

2013-08-29 13:48 UTC #6 lore raw

PATCH v2 2/3 ARM: OMAP4+: Move SRAM data to DT

Quoted 22 lines · Sekhar Nori

Quoted 15 lines · Santosh Shilimkar
Quoted 9 lines · Sekhar Nori
Quoted 8 lines · Rajendra Nayak
arch/arm/boot/dts/omap4.dtsi +0 -0
index 22d9f2b..1ba6a77 100644
@@ -126,6 +126,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
Quoted 5 lines
arch/arm/boot/dts/omap4.dtsi line 129
Quoted 1 line
arch/arm/boot/dts/omap4.dtsi +1 -0
+		ocmcram: ocmcram at 40304000 {
This can now be changed to 0x40300000 now that you have moved to gen_pool_alloc()?
Quoted 5 lines
NO.
It won't work on secure devices since first 16 KB is occupied for default configuration. Its not worth trouble also to handle secure/non-secure considering the use of SRAM which is actually just limited to errata. 40304000 will work for both devices.

Quoted 5 lines

Okay, the same problem is not applicable to OMAP5 and other devices? I am okay with this as such, may be just add a comment explaining why there is an offset.
From specs the errata is applicable only for O4 though OMAP5 downstream

kernel enabled it. Its ok to limit this one for O5 now.

Regards,
Santosh

Rajendra Nayak

author

2013-08-29 13:50 UTC #7 lore raw

PATCH v2 2/3 ARM: OMAP4+: Move SRAM data to DT

In reply to Santosh Shilimkar

Quoted 15 lines · Santosh Shilimkar

Quoted 9 lines · Sekhar Nori
Quoted 8 lines · Rajendra Nayak
arch/arm/boot/dts/omap4.dtsi +0 -0
index 22d9f2b..1ba6a77 100644
@@ -126,6 +126,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
Quoted 5 lines
arch/arm/boot/dts/omap4.dtsi line 129
Quoted 1 line
arch/arm/boot/dts/omap4.dtsi +1 -0
+		ocmcram: ocmcram at 40304000 {
This can now be changed to 0x40300000 now that you have moved to gen_pool_alloc()?

Quoted 5 lines

NO.
It won't work on secure devices since first 16 KB is occupied for default configuration. Its not worth trouble also to handle secure/non-secure considering the use of SRAM which is actually just limited to errata. 40304000 will work for both devices.

Right. Sekhar, you might have confused because of the existing buggy code in sram.c and sram.h which did this (and is removed in this series)

from sram.c
-----------
#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
-#else
-#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
-#endif
-#define OMAP5_SRAM_PA 0x40300000

from sram.h
-----------
#define OMAP2_SRAM_PA 0x40200000
#define OMAP3_SRAM_PA 0x40200000
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA 0x40304000
-#define OMAP4_SRAM_VA 0xfe404000
-#else
-#define OMAP4_SRAM_PA 0x40300000
-#endif

I am not sure where the checks for CONFIG_OMAP4_ERRATA_I688 came in from, but these are done, like Santosh said, to handle secure and non-secure sram across GP and HS devices and in no way related to handling errata I688.

Quoted 4 lines

Regards,
Santosh

Santosh Shilimkar

2013-08-29 13:51 UTC #8 lore raw

PATCH v2 2/3 ARM: OMAP4+: Move SRAM data to DT

Quoted 47 lines · Rajendra Nayak

Quoted 15 lines · Santosh Shilimkar
Quoted 9 lines · Sekhar Nori
Quoted 8 lines · Rajendra Nayak
arch/arm/boot/dts/omap4.dtsi +0 -0
index 22d9f2b..1ba6a77 100644
@@ -126,6 +126,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
Quoted 5 lines
arch/arm/boot/dts/omap4.dtsi line 129
Quoted 1 line
arch/arm/boot/dts/omap4.dtsi +1 -0
+		ocmcram: ocmcram at 40304000 {
This can now be changed to 0x40300000 now that you have moved to gen_pool_alloc()?
Quoted 5 lines
NO.
It won't work on secure devices since first 16 KB is occupied for default configuration. Its not worth trouble also to handle secure/non-secure considering the use of SRAM which is actually just limited to errata. 40304000 will work for both devices.
Right. Sekhar, you might have confused because of the existing buggy code in sram.c and sram.h which did this (and is removed in this series)
from sram.c
-----------
#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
arch/arm/mach-omap2/sram.c +0 -6
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PUB_PA	OMAP4_SRAM_PA
-#else
-#define OMAP4_SRAM_PUB_PA	(OMAP4_SRAM_PA + 0x4000)
-#endif
-#define OMAP5_SRAM_PA		0x40300000
from sram.h
-----------
#define OMAP2_SRAM_PA 0x40200000
#define OMAP3_SRAM_PA 0x40200000
arch/arm/mach-omap2/sram.c +0 -6
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA		0x40304000
-#define OMAP4_SRAM_VA		0xfe404000
-#else
-#define OMAP4_SRAM_PA		0x40300000
-#endif

Quoted 5 lines

I am not sure where the checks for CONFIG_OMAP4_ERRATA_I688 came in from, but these are done, like Santosh said, to handle secure and non-secure sram across GP and HS devices and in no way related to handling errata I688.

The check was to ensure that with errata enabled, we don't care about first 16 KB ;-)

Sekhar Nori

2013-09-02 17:03 UTC #9 lore raw

PATCH v2 2/3 ARM: OMAP4+: Move SRAM data to DT

Quoted 48 lines · Santosh Shilimkar

Quoted 47 lines · Rajendra Nayak
Quoted 15 lines · Santosh Shilimkar
Quoted 9 lines · Sekhar Nori
Quoted 8 lines · Rajendra Nayak
arch/arm/boot/dts/omap4.dtsi +0 -0
index 22d9f2b..1ba6a77 100644
@@ -126,6 +126,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
Quoted 5 lines
arch/arm/boot/dts/omap4.dtsi line 129
Quoted 1 line
arch/arm/boot/dts/omap4.dtsi +1 -0
+		ocmcram: ocmcram at 40304000 {
This can now be changed to 0x40300000 now that you have moved to gen_pool_alloc()?
Quoted 5 lines
NO.
It won't work on secure devices since first 16 KB is occupied for default configuration. Its not worth trouble also to handle secure/non-secure considering the use of SRAM which is actually just limited to errata. 40304000 will work for both devices.
Right. Sekhar, you might have confused because of the existing buggy code in sram.c and sram.h which did this (and is removed in this series)
from sram.c
-----------
#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
arch/arm/mach-omap2/sram.c +0 -6
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PUB_PA	OMAP4_SRAM_PA
-#else
-#define OMAP4_SRAM_PUB_PA	(OMAP4_SRAM_PA + 0x4000)
-#endif
-#define OMAP5_SRAM_PA		0x40300000
from sram.h
-----------
#define OMAP2_SRAM_PA 0x40200000
#define OMAP3_SRAM_PA 0x40200000
arch/arm/mach-omap2/sram.c +0 -6
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA		0x40304000
-#define OMAP4_SRAM_VA		0xfe404000
-#else
-#define OMAP4_SRAM_PA		0x40300000
-#endif

Quoted 7 lines

Quoted 5 lines
I am not sure where the checks for CONFIG_OMAP4_ERRATA_I688 came in from, but these are done, like Santosh said, to handle secure and non-secure sram across GP and HS devices and in no way related to handling errata I688.
The check was to ensure that with errata enabled, we don't care about first 16 KB ;-)

Hi Rajendra, thanks for the explanation. Other devices like AM437x which have HS variants might need such adjustment too. It will be nice to check that.

Thanks,
Sekhar

Sekhar Nori

2013-09-03 13:37 UTC #10 lore raw

PATCH v2 2/3 ARM: OMAP4+: Move SRAM data to DT

Quoted 57 lines · Sekhar Nori

Quoted 48 lines · Santosh Shilimkar
Quoted 47 lines · Rajendra Nayak
Quoted 15 lines · Santosh Shilimkar
Quoted 9 lines · Sekhar Nori
Quoted 8 lines · Rajendra Nayak
arch/arm/boot/dts/omap4.dtsi +0 -0
index 22d9f2b..1ba6a77 100644
@@ -126,6 +126,11 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
Quoted 5 lines
arch/arm/boot/dts/omap4.dtsi line 129
Quoted 1 line
arch/arm/boot/dts/omap4.dtsi +1 -0
+		ocmcram: ocmcram at 40304000 {
This can now be changed to 0x40300000 now that you have moved to gen_pool_alloc()?
Quoted 5 lines
NO.
It won't work on secure devices since first 16 KB is occupied for default configuration. Its not worth trouble also to handle secure/non-secure considering the use of SRAM which is actually just limited to errata. 40304000 will work for both devices.
Right. Sekhar, you might have confused because of the existing buggy code in sram.c and sram.h which did this (and is removed in this series)
from sram.c
-----------
#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
arch/arm/mach-omap2/sram.c +0 -6
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PUB_PA	OMAP4_SRAM_PA
-#else
-#define OMAP4_SRAM_PUB_PA	(OMAP4_SRAM_PA + 0x4000)
-#endif
-#define OMAP5_SRAM_PA		0x40300000
from sram.h
-----------
#define OMAP2_SRAM_PA 0x40200000
#define OMAP3_SRAM_PA 0x40200000
arch/arm/mach-omap2/sram.c +0 -6
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA		0x40304000
-#define OMAP4_SRAM_VA		0xfe404000
-#else
-#define OMAP4_SRAM_PA		0x40300000
-#endif
Quoted 7 lines
Quoted 5 lines
I am not sure where the checks for CONFIG_OMAP4_ERRATA_I688 came in from, but these are done, like Santosh said, to handle secure and non-secure sram across GP and HS devices and in no way related to handling errata I688.
The check was to ensure that with errata enabled, we don't care about first 16 KB ;-)

Quoted 3 lines

Hi Rajendra, thanks for the explanation. Other devices like AM437x which have HS variants might need such adjustment too. It will be nice to check that.

So I checked with folks working on the HS variant and what you have for AM437x is just fine. The secure runtime uses a different SRAM bank and even if there is a need to use the GP SRAM, the space will first be carved using gen_pool APIs on Linux. Only requirement from secure runtime software is physically contiguous area - which I think gen_pool_alloc() guarantees.

Thanks,
Sekhar

Rajendra Nayak

author

2013-08-29 11:23 UTC #11 lore raw

PATCH v2 3/3 ARM: OMAP4+: Remove static iotable mappings for SRAM

In reply to Rajendra Nayak

In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688.

Signed-off-by Rajendra Nayak <[email protected]>

---
 Documentation/devicetree/bindings/arm/omap/mpu.txt |    5 ++++-
 arch/arm/boot/dts/omap4.dtsi                       |    1 +
 arch/arm/boot/dts/omap5.dtsi                       |    3 ++-
 arch/arm/mach-omap2/io.c                           |   17 -----------------
 arch/arm/mach-omap2/omap4-common.c                 |   17 ++++++++++++++++-
 arch/arm/mach-omap2/sram.c                         |    6 ------
 arch/arm/mach-omap2/sram.h                         |    6 ------
 7 files changed, 23 insertions(+), 32 deletions(-)

Documentation/devicetree/bindings/arm/omap/mpu.txt +4 -1

index 1a5a42c..8915ba3 100644
@@ -6,9 +6,12 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
 
 Required properties:
 - compatible : Should be "ti,omap3-mpu" for OMAP3
-               Should be "ti,omap4-mpu" for OMAP4
+               Should be "ti,omap4-mpu" for OMAP4 and OMAP5
 - ti,hwmods: "mpu"
 
+Optional properties:
+- sram:	Phandle to the ocmcram node
+
 Examples:
 
 - For an OMAP4 SMP system:

arch/arm/boot/dts/omap4.dtsi +1 -0

index 1ba6a77..9114241 100644
@@ -71,6 +71,7 @@
 		mpu {
 			compatible = "ti,omap4-mpu";
 			ti,hwmods = "mpu";
+			sram = <&ocmcram>;
 		};
 
 		dsp {

arch/arm/boot/dts/omap5.dtsi +2 -1

index 461ffd8..e9b735b 100644
@@ -72,8 +72,9 @@
 	soc {
 		compatible = "ti,omap-infra";
 		mpu {
-			compatible = "ti,omap5-mpu";
+			compatible = "ti,omap4-mpu";
 			ti,hwmods = "mpu";
+			sram = <&ocmcram>;
 		};
 	};

arch/arm/mach-omap2/io.c +0 ~~-17~~

index 4a3f06f..8b2334e 100644
@@ -239,15 +239,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
 		.length		= L4_PER_44XX_SIZE,
 		.type		= MT_DEVICE,
 	},
-#ifdef CONFIG_OMAP4_ERRATA_I688
-	{
-		.virtual	= OMAP4_SRAM_VA,
-		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
-		.length		= PAGE_SIZE,
-		.type		= MT_MEMORY_SO,
-	},
-#endif
-
 };
 #endif

@@ -277,14 +268,6 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
 		.length		= L4_PER_54XX_SIZE,
 		.type		= MT_DEVICE,
 	},
-#ifdef CONFIG_OMAP4_ERRATA_I688
-	{
-		.virtual	= OMAP4_SRAM_VA,
-		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
-		.length		= PAGE_SIZE,
-		.type		= MT_MEMORY_SO,
-	},
-#endif
 };
 #endif

arch/arm/mach-omap2/omap4-common.c +16 -1

index 5791143..6b5ffb3 100644
@@ -24,6 +24,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
 #include <linux/reboot.h>
+#include <linux/genalloc.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>

@@ -71,6 +72,21 @@ void omap_bus_sync(void)
 }
 EXPORT_SYMBOL(omap_bus_sync);
 
+static int __init omap4_sram_init(void)
+{
+	struct device_node *np;
+	struct gen_pool *sram_pool;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
+	if (!np)
+		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+			 __func__);
+	sram_pool = of_get_named_gen_pool(np, "sram", 0);
+	sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
+	return 0;
+}
+omap_arch_initcall(omap4_sram_init);
+
 /* Steal one page physical memory for barrier implementation */
 int __init omap_barrier_reserve_memblock(void)
 {

@@ -91,7 +107,6 @@ void __init omap_barriers_init(void)
 	dram_io_desc[0].type = MT_MEMORY_SO;
 	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
 	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
-	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
 
 	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
 		(long long) paddr, dram_io_desc[0].virtual);

arch/arm/mach-omap2/sram.c +0 -6

index d5ecb75..8591044 100644
@@ -124,12 +124,6 @@ static void __init omap2_map_sram(void)
 {
 	int cached = 1;
 
-#ifdef CONFIG_OMAP4_ERRATA_I688
-	if (cpu_is_omap44xx()) {
-		omap_sram_start += PAGE_SIZE;
-		omap_sram_size -= SZ_16K;
-	}
-#endif
 	if (cpu_is_omap34xx()) {
 		/*
 		 * SRAM must be marked as non-cached on OMAP3 since the

arch/arm/mach-omap2/sram.h +0 -6

index 3f83b80..948d3ed 100644
@@ -74,9 +74,3 @@ static inline void omap_push_sram_idle(void) {}
  */
 #define OMAP2_SRAM_PA		0x40200000
 #define OMAP3_SRAM_PA           0x40200000
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA		0x40304000
-#define OMAP4_SRAM_VA		0xfe404000
-#else
-#define OMAP4_SRAM_PA		0x40300000
-#endif

Signature · 1 line

1.7.9.5

Santosh Shilimkar

2013-08-29 13:23 UTC #12 lore raw

PATCH v2 3/3 ARM: OMAP4+: Remove static iotable mappings for SRAM

Quoted 7 lines · Rajendra Nayak

In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688.
Suggested-by Sekhar Nori <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>

Quoted 10 lines

---
 Documentation/devicetree/bindings/arm/omap/mpu.txt |    5 ++++-
 arch/arm/boot/dts/omap4.dtsi                       |    1 +
 arch/arm/boot/dts/omap5.dtsi                       |    3 ++-
 arch/arm/mach-omap2/io.c                           |   17 -----------------
 arch/arm/mach-omap2/omap4-common.c                 |   17 ++++++++++++++++-
 arch/arm/mach-omap2/sram.c                         |    6 ------
 arch/arm/mach-omap2/sram.h                         |    6 ------
 7 files changed, 23 insertions(+), 32 deletions(-)

Add a note in the change-log about about omap_bus_sync() being NOP till the SRAM is initialized. Its not a problem since the idle loop hasn't started yet.

Other than that looks fine.

Quoted 154 lines

Documentation/devicetree/bindings/arm/omap/mpu.txt +4 -1

index 1a5a42c..8915ba3 100644
@@ -6,9 +6,12 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
 
 Required properties:
 - compatible : Should be "ti,omap3-mpu" for OMAP3
-               Should be "ti,omap4-mpu" for OMAP4
+               Should be "ti,omap4-mpu" for OMAP4 and OMAP5
 - ti,hwmods: "mpu"
 
+Optional properties:
+- sram:	Phandle to the ocmcram node
+
 Examples:
 
 - For an OMAP4 SMP system:

arch/arm/boot/dts/omap4.dtsi +1 -0

index 1ba6a77..9114241 100644
@@ -71,6 +71,7 @@
 		mpu {
 			compatible = "ti,omap4-mpu";
 			ti,hwmods = "mpu";
+			sram = <&ocmcram>;
 		};
 
 		dsp {

arch/arm/boot/dts/omap5.dtsi +2 -1

index 461ffd8..e9b735b 100644
@@ -72,8 +72,9 @@
 	soc {
 		compatible = "ti,omap-infra";
 		mpu {
-			compatible = "ti,omap5-mpu";
+			compatible = "ti,omap4-mpu";
 			ti,hwmods = "mpu";
+			sram = <&ocmcram>;
 		};
 	};

arch/arm/mach-omap2/io.c +0 ~~-17~~

index 4a3f06f..8b2334e 100644
@@ -239,15 +239,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
 		.length		= L4_PER_44XX_SIZE,
 		.type		= MT_DEVICE,
 	},
-#ifdef CONFIG_OMAP4_ERRATA_I688
-	{
-		.virtual	= OMAP4_SRAM_VA,
-		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
-		.length		= PAGE_SIZE,
-		.type		= MT_MEMORY_SO,
-	},
-#endif
-
 };
 #endif

@@ -277,14 +268,6 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
 		.length		= L4_PER_54XX_SIZE,
 		.type		= MT_DEVICE,
 	},
-#ifdef CONFIG_OMAP4_ERRATA_I688
-	{
-		.virtual	= OMAP4_SRAM_VA,
-		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
-		.length		= PAGE_SIZE,
-		.type		= MT_MEMORY_SO,
-	},
-#endif
 };
 #endif

arch/arm/mach-omap2/omap4-common.c +16 -1

index 5791143..6b5ffb3 100644
@@ -24,6 +24,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
 #include <linux/reboot.h>
+#include <linux/genalloc.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>

@@ -71,6 +72,21 @@ void omap_bus_sync(void)
 }
 EXPORT_SYMBOL(omap_bus_sync);
 
+static int __init omap4_sram_init(void)
+{
+	struct device_node *np;
+	struct gen_pool *sram_pool;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
+	if (!np)
+		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+			 __func__);
+	sram_pool = of_get_named_gen_pool(np, "sram", 0);
+	sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
+	return 0;
+}
+omap_arch_initcall(omap4_sram_init);
+
 /* Steal one page physical memory for barrier implementation */
 int __init omap_barrier_reserve_memblock(void)
 {

@@ -91,7 +107,6 @@ void __init omap_barriers_init(void)
 	dram_io_desc[0].type = MT_MEMORY_SO;
 	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
 	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
-	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
 
 	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
 		(long long) paddr, dram_io_desc[0].virtual);

arch/arm/mach-omap2/sram.c +0 -6

index d5ecb75..8591044 100644
@@ -124,12 +124,6 @@ static void __init omap2_map_sram(void)
 {
 	int cached = 1;
 
-#ifdef CONFIG_OMAP4_ERRATA_I688
-	if (cpu_is_omap44xx()) {
-		omap_sram_start += PAGE_SIZE;
-		omap_sram_size -= SZ_16K;
-	}
-#endif
 	if (cpu_is_omap34xx()) {
 		/*
 		 * SRAM must be marked as non-cached on OMAP3 since the

arch/arm/mach-omap2/sram.h +0 -6

index 3f83b80..948d3ed 100644
@@ -74,9 +74,3 @@ static inline void omap_push_sram_idle(void) {}
  */
 #define OMAP2_SRAM_PA		0x40200000
 #define OMAP3_SRAM_PA           0x40200000
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA		0x40304000
-#define OMAP4_SRAM_VA		0xfe404000
-#else
-#define OMAP4_SRAM_PA		0x40300000
-#endif

Rajendra Nayak

author

2013-08-29 13:56 UTC #13 lore raw

PATCH v2 3/3 ARM: OMAP4+: Remove static iotable mappings for SRAM

Quoted 18 lines · Santosh Shilimkar

Quoted 7 lines · Rajendra Nayak
In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688.
Suggested-by Sekhar Nori <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Quoted 10 lines
---
 Documentation/devicetree/bindings/arm/omap/mpu.txt |    5 ++++-
 arch/arm/boot/dts/omap4.dtsi                       |    1 +
 arch/arm/boot/dts/omap5.dtsi                       |    3 ++-
 arch/arm/mach-omap2/io.c                           |   17 -----------------
 arch/arm/mach-omap2/omap4-common.c                 |   17 ++++++++++++++++-
 arch/arm/mach-omap2/sram.c                         |    6 ------
 arch/arm/mach-omap2/sram.h                         |    6 ------
 7 files changed, 23 insertions(+), 32 deletions(-)

Quoted 3 lines

Add a note in the change-log about about omap_bus_sync() being NOP till the SRAM is initialized. Its not a problem since the idle loop hasn't started yet.

ok, will update the changelog, thanks.

Quoted 158 lines

Other than that looks fine.

Quoted 154 lines

Documentation/devicetree/bindings/arm/omap/mpu.txt +4 -1

index 1a5a42c..8915ba3 100644
@@ -6,9 +6,12 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
 
 Required properties:
 - compatible : Should be "ti,omap3-mpu" for OMAP3
-               Should be "ti,omap4-mpu" for OMAP4
+               Should be "ti,omap4-mpu" for OMAP4 and OMAP5
 - ti,hwmods: "mpu"
 
+Optional properties:
+- sram:	Phandle to the ocmcram node
+
 Examples:
 
 - For an OMAP4 SMP system:

arch/arm/boot/dts/omap4.dtsi +1 -0

index 1ba6a77..9114241 100644
@@ -71,6 +71,7 @@
 		mpu {
 			compatible = "ti,omap4-mpu";
 			ti,hwmods = "mpu";
+			sram = <&ocmcram>;
 		};
 
 		dsp {

arch/arm/boot/dts/omap5.dtsi +2 -1

index 461ffd8..e9b735b 100644
@@ -72,8 +72,9 @@
 	soc {
 		compatible = "ti,omap-infra";
 		mpu {
-			compatible = "ti,omap5-mpu";
+			compatible = "ti,omap4-mpu";
 			ti,hwmods = "mpu";
+			sram = <&ocmcram>;
 		};
 	};

arch/arm/mach-omap2/io.c +0 ~~-17~~

index 4a3f06f..8b2334e 100644
@@ -239,15 +239,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
 		.length		= L4_PER_44XX_SIZE,
 		.type		= MT_DEVICE,
 	},
-#ifdef CONFIG_OMAP4_ERRATA_I688
-	{
-		.virtual	= OMAP4_SRAM_VA,
-		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
-		.length		= PAGE_SIZE,
-		.type		= MT_MEMORY_SO,
-	},
-#endif
-
 };
 #endif

@@ -277,14 +268,6 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
 		.length		= L4_PER_54XX_SIZE,
 		.type		= MT_DEVICE,
 	},
-#ifdef CONFIG_OMAP4_ERRATA_I688
-	{
-		.virtual	= OMAP4_SRAM_VA,
-		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
-		.length		= PAGE_SIZE,
-		.type		= MT_MEMORY_SO,
-	},
-#endif
 };
 #endif

arch/arm/mach-omap2/omap4-common.c +16 -1

index 5791143..6b5ffb3 100644
@@ -24,6 +24,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
 #include <linux/reboot.h>
+#include <linux/genalloc.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>

@@ -71,6 +72,21 @@ void omap_bus_sync(void)
 }
 EXPORT_SYMBOL(omap_bus_sync);
 
+static int __init omap4_sram_init(void)
+{
+	struct device_node *np;
+	struct gen_pool *sram_pool;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
+	if (!np)
+		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+			 __func__);
+	sram_pool = of_get_named_gen_pool(np, "sram", 0);
+	sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
+	return 0;
+}
+omap_arch_initcall(omap4_sram_init);
+
 /* Steal one page physical memory for barrier implementation */
 int __init omap_barrier_reserve_memblock(void)
 {

@@ -91,7 +107,6 @@ void __init omap_barriers_init(void)
 	dram_io_desc[0].type = MT_MEMORY_SO;
 	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
 	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
-	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
 
 	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
 		(long long) paddr, dram_io_desc[0].virtual);

arch/arm/mach-omap2/sram.c +0 -6

index d5ecb75..8591044 100644
@@ -124,12 +124,6 @@ static void __init omap2_map_sram(void)
 {
 	int cached = 1;
 
-#ifdef CONFIG_OMAP4_ERRATA_I688
-	if (cpu_is_omap44xx()) {
-		omap_sram_start += PAGE_SIZE;
-		omap_sram_size -= SZ_16K;
-	}
-#endif
 	if (cpu_is_omap34xx()) {
 		/*
 		 * SRAM must be marked as non-cached on OMAP3 since the

arch/arm/mach-omap2/sram.h +0 -6

index 3f83b80..948d3ed 100644
@@ -74,9 +74,3 @@ static inline void omap_push_sram_idle(void) {}
  */
 #define OMAP2_SRAM_PA		0x40200000
 #define OMAP3_SRAM_PA           0x40200000
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA		0x40304000
-#define OMAP4_SRAM_VA		0xfe404000
-#else
-#define OMAP4_SRAM_PA		0x40300000
-#endif

Kevin Hilman

2013-08-29 17:20 UTC #14 lore raw

PATCH v2 3/3 ARM: OMAP4+: Remove static iotable mappings for SRAM

In reply to Rajendra Nayak

Quoted 7 lines · Rajendra Nayak

In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688.
Suggested-by Sekhar Nori <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>

[...]

Quoted 4 lines

arch/arm/mach-omap2/omap4-common.c +0 -0

@@ -71,6 +72,21 @@ void omap_bus_sync(void)
 }
 EXPORT_SYMBOL(omap_bus_sync);

arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 84

Quoted 10 lines

arch/arm/mach-omap2/omap4-common.c +10 -0

+static int __init omap4_sram_init(void)
+{
+	struct device_node *np;
+	struct gen_pool *sram_pool;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
+	if (!np)
+		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+			 __func__);
+	sram_pool = of_get_named_gen_pool(np, "sram", 0);

I haven't actually tested this, but if there is no 'sram' property defined...

arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 85

Quoted 1 line

arch/arm/mach-omap2/omap4-common.c +1 -0
+	sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);

... does this still behave properly?

arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 87

Quoted 2 lines

arch/arm/mach-omap2/omap4-common.c +2 -0
+	return 0;
+}

Kevin

Santosh Shilimkar

2013-08-29 17:25 UTC #15 lore raw

PATCH v2 3/3 ARM: OMAP4+: Remove static iotable mappings for SRAM

Quoted 16 lines · Kevin Hilman

Quoted 7 lines · Rajendra Nayak
In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688.
Suggested-by Sekhar Nori <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
[...]
Quoted 4 lines
arch/arm/mach-omap2/omap4-common.c +0 -0
@@ -71,6 +72,21 @@ void omap_bus_sync(void)
 }
 EXPORT_SYMBOL(omap_bus_sync);
 

Quoted 13 lines

arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 84
Quoted 10 lines
arch/arm/mach-omap2/omap4-common.c +10 -0
+static int __init omap4_sram_init(void)
+{
+	struct device_node *np;
+	struct gen_pool *sram_pool;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
+	if (!np)
+		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+			 __func__);
+	sram_pool = of_get_named_gen_pool(np, "sram", 0);
I haven't actually tested this, but if there is no 'sram' property defined...

If the sram property is not defined, the bus_sync will be just a nop. Below check will take care of it.

if (dram_sync && sram_sync)

Regards,
Santosh

Rajendra Nayak

author

2013-08-30 09:27 UTC #16 lore raw

PATCH v2 3/3 ARM: OMAP4+: Remove static iotable mappings for SRAM

In reply to Kevin Hilman

Quoted 29 lines · Kevin Hilman

Quoted 7 lines · Rajendra Nayak
In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688.
Suggested-by Sekhar Nori <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
[...]
Quoted 4 lines
arch/arm/mach-omap2/omap4-common.c +0 -0
@@ -71,6 +72,21 @@ void omap_bus_sync(void)
 }
 EXPORT_SYMBOL(omap_bus_sync);
 
arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 84
Quoted 10 lines
arch/arm/mach-omap2/omap4-common.c +10 -0
+static int __init omap4_sram_init(void)
+{
+	struct device_node *np;
+	struct gen_pool *sram_pool;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
+	if (!np)
+		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+			 __func__);
+	sram_pool = of_get_named_gen_pool(np, "sram", 0);
I haven't actually tested this, but if there is no 'sram' property defined...

Quoted 3 lines

arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 85
Quoted 1 line
arch/arm/mach-omap2/omap4-common.c +1 -0
+	sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
... does this still behave properly?

I guess not :(
of_get_named_gen_pool() ends up returning NULL, but passing NULL to gen_pool_alloc() crashes. Will fix with the additional check for non-NULL sram_pool, thanks.

regards,
Rajendra

Quoted 6 lines

arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 87
Quoted 3 lines
arch/arm/mach-omap2/omap4-common.c +2 -0
+	return 0;
+}
Kevin

Kevin Hilman

2013-08-30 14:39 UTC #17 lore raw

PATCH v2 3/3 ARM: OMAP4+: Remove static iotable mappings for SRAM

Quoted 30 lines · Rajendra Nayak

Quoted 29 lines · Kevin Hilman
Quoted 7 lines · Rajendra Nayak
In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688.
Suggested-by Sekhar Nori <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
[...]
Quoted 4 lines
arch/arm/mach-omap2/omap4-common.c +0 -0
@@ -71,6 +72,21 @@ void omap_bus_sync(void)
 }
 EXPORT_SYMBOL(omap_bus_sync);
 
arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 84
Quoted 10 lines
arch/arm/mach-omap2/omap4-common.c +10 -0
+static int __init omap4_sram_init(void)
+{
+	struct device_node *np;
+	struct gen_pool *sram_pool;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
+	if (!np)
+		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+			 __func__);
+	sram_pool = of_get_named_gen_pool(np, "sram", 0);
I haven't actually tested this, but if there is no 'sram' property defined...

Quoted 7 lines

Quoted 3 lines
arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 85
Quoted 1 line
arch/arm/mach-omap2/omap4-common.c +1 -0
+	sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
... does this still behave properly?
I guess not :(
of_get_named_gen_pool() ends up returning NULL, but passing NULL to gen_pool_alloc() crashes. Will fix with the additional check for non-NULL sram_pool, thanks.

OK, that's what I suspected. Thanks for checking/testing.

Kevin

Santosh Shilimkar

2013-08-30 14:41 UTC #18 lore raw

PATCH v2 3/3 ARM: OMAP4+: Remove static iotable mappings for SRAM

Quoted 36 lines · Kevin Hilman

Quoted 34 lines · Rajendra Nayak
Quoted 32 lines · Kevin Hilman
Quoted 7 lines · Rajendra Nayak
In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688.
Suggested-by Sekhar Nori <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
[...]
Quoted 4 lines
arch/arm/mach-omap2/omap4-common.c +0 -0
@@ -71,6 +72,21 @@ void omap_bus_sync(void)
 }
 EXPORT_SYMBOL(omap_bus_sync);
 
arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 84
Quoted 10 lines
arch/arm/mach-omap2/omap4-common.c +10 -0
+static int __init omap4_sram_init(void)
+{
+	struct device_node *np;
+	struct gen_pool *sram_pool;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
+	if (!np)
+		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+			 __func__);
+	sram_pool = of_get_named_gen_pool(np, "sram", 0);
I haven't actually tested this, but if there is no 'sram' property defined...
arch/arm/mach-omap2/omap4-common.c void omap_bus_sync(void) · line 85
Quoted 1 line
arch/arm/mach-omap2/omap4-common.c +1 -0
+	sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
... does this still behave properly?

Quoted 6 lines

Quoted 3 lines
I guess not :(
of_get_named_gen_pool() ends up returning NULL, but passing NULL to gen_pool_alloc() crashes. Will fix with the additional check for non-NULL sram_pool, thanks.
OK, that's what I suspected. Thanks for checking/testing.

I miss-understood your comment initially. Now re-reading it, its clear now.

Regards,
Santosh

Santosh Shilimkar

2013-08-29 13:24 UTC #19 lore raw

v2 cover OMAP4+: Get rid of internal SRAM handling

In reply to Rajendra Nayak

Quoted 13 lines · Rajendra Nayak

v2:
Removed the static iotable mapping for sram done to handle errata I688, and used gen_pool instead.
Make all OMAP DT only platforms (am33xx, am43xx, omap4 and omap5) use drivers/misc/sram.c driver instead of the omap internal implementation for SRAM handling.
Rajendra Nayak (3):
ARM: AM335x: Get rid of unused sram init function
ARM: OMAP4+: Move SRAM data to DT
ARM: OMAP4+: Remove static iotable mappings for SRAM

Quoted 12 lines

 Documentation/devicetree/bindings/arm/omap/mpu.txt |    5 ++-
 arch/arm/boot/dts/am33xx.dtsi                      |    5 +--
 arch/arm/boot/dts/am4372.dtsi                      |    5 +++
 arch/arm/boot/dts/omap4.dtsi                       |    6 +++
 arch/arm/boot/dts/omap5.dtsi                       |    8 +++-
 arch/arm/configs/omap2plus_defconfig               |    1 +
 arch/arm/mach-omap2/io.c                           |   17 ---------
 arch/arm/mach-omap2/omap4-common.c                 |   17 ++++++++-
 arch/arm/mach-omap2/sram.c                         |   39 +-------------------
 arch/arm/mach-omap2/sram.h                         |    7 ----
 10 files changed, 42 insertions(+), 68 deletions(-)

Apart from one minor comment of last patch, the series looks fine ti me.

Acked-by Santosh Shilimkar <[email protected]>

Regards,
Santosh