ARM: keystone: clock tree and PM bus support

PATCH New Santosh Shilimkar 2 participants 11 messages Aug 29, 2013 – Oct 14, 2013

Subsystems (4)

Device tree bindings Arm (32-bit) Arm sub-architectures Arm/Texas instrument Keystone architecture

lore

Share & tools

lore

Santosh Shilimkar

author

2013-08-29 23:36 UTC #0 lore raw

v2 cover ARM: keystone: clock tree and PM bus support

Refreshed version of the ealier patch series against the updated clock dt bidnings series[1] and [2]

Tested on Keystone EVM with [1] [2] integrated.

Cc Mike Turquette <[email protected]>

Cc arm at kernel.org

Santosh Shilimkar (4):
ARM: dts: keystone: Add clock tree data to devicetree
ARM: dts: keystone: Add clock phandle to UART nodes
ARM: keystone: Enable clock drivers
ARM: keystone: add PM bus support for clock management

 arch/arm/boot/dts/keystone-clocks.dtsi |  821 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/keystone.dts         |    4 +
 arch/arm/mach-keystone/Kconfig         |    1 +
 drivers/bus/Makefile                   |    2 +
 drivers/bus/keystone_pm_bus.c          |   70 +++
 5 files changed, 898 insertions(+)
 create mode 100644 arch/arm/boot/dts/keystone-clocks.dtsi
 create mode 100644 drivers/bus/keystone_pm_bus.c

Regards,
Santosh

[1] http://lkml.org/lkml/2013/8/22/52
[2] http://www.spinics.net/lists/arm-kernel/msg270884.html

Signature · 1 line

1.7.9.5

Santosh Shilimkar

author

2013-08-29 23:36 UTC #1 lore raw

PATCH v2 1/4 ARM: dts: keystone: Add clock tree data to devicetree

Add clock tree for Keystone 2 based SOCs.

Cc Mike Turquette <[email protected]>

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/boot/dts/keystone-clocks.dtsi |  821 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/keystone.dts         |    2 +
 2 files changed, 823 insertions(+)
 create mode 100644 arch/arm/boot/dts/keystone-clocks.dtsi

arch/arm/boot/dts/keystone-clocks.dtsi new file +821 -0

new file mode 100644
index 0000000..148ab87
@@ -0,0 +1,821 @@
+/*
+ * Device Tree Source for Keystone 2 clock tree
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clocks {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	refclkmain: refclkmain {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <122880000>;
+		clock-output-names = "refclk-main";
+	};
+
+	mainpllclk: mainpllclk at 2310110 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,main-pll-clock";
+		clocks = <&refclkmain>;
+		reg = <0x02620350 4>, <0x02310110 4>;
+		reg-names = "control", "multiplier";
+		fixed-postdiv = <2>;
+	};
+
+	papllclk: papllclk at 2620358 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,pll-clock";
+		clocks = <&refclkmain>;
+		clock-output-names = "pa-pll-clk";
+		reg = <0x02620358 4>;
+		reg-names = "control";
+		fixed-postdiv = <6>;
+	};
+
+	ddr3allclk: ddr3apllclk at 2620360 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,pll-clock";
+		clocks = <&refclkmain>;
+		clock-output-names = "ddr-3a-pll-clk";
+		reg = <0x02620360 4>;
+		reg-names = "control";
+		fixed-postdiv = <6>;
+	};
+
+	ddr3bllclk: ddr3bpllclk at 2620368 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,pll-clock";
+		clocks = <&refclkmain>;
+		clock-output-names = "ddr-3b-pll-clk";
+		reg = <0x02620368 4>;
+		reg-names = "control";
+		fixed-postdiv = <6>;
+	};
+
+	armpllclk: armpllclk at 2620370 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,pll-clock";
+		clocks = <&refclkmain>;
+		clock-output-names = "arm-pll-clk";
+		reg = <0x02620370 4>;
+		reg-names = "control";
+		fixed-postdiv = <6>;
+	};
+
+	mainmuxclk: mainmuxclk at 2310108 {
+		#clock-cells = <0>;
+		compatible = "mux-clock";
+		clocks = <&mainpllclk>, <&refclkmain>;
+		reg = <0x02310108 4>;
+		bit-shift = <23>;
+		bit-mask = <1>;
+		clock-output-names = "mainmuxclk";
+	};
+
+	chipclk1: chipclk1 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&mainmuxclk>;
+		clock-div = <1>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk1";
+	};
+
+	chipclk1rstiso: chipclk1rstiso {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&mainmuxclk>;
+		clock-div = <1>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk1rstiso";
+	};
+
+	gemtraceclk: gemtraceclk at 2310120 {
+		#clock-cells = <0>;
+		compatible = "divider-clock";
+		clocks = <&mainmuxclk>;
+		reg = <0x02310120 4>;
+		bit-shift = <0>;
+		bit-mask = <8>;
+		clock-output-names = "gemtraceclk";
+	};
+
+	chipstmxptclk: chipstmxptclk {
+		#clock-cells = <0>;
+		compatible = "divider-clock";
+		clocks = <&mainmuxclk>;
+		reg = <0x02310164 4>;
+		bit-shift = <0>;
+		bit-mask = <8>;
+		clock-output-names = "chipstmxptclk";
+	};
+
+	chipclk12: chipclk12 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1>;
+		clock-div = <2>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk12";
+	};
+
+	chipclk13: chipclk13 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1>;
+		clock-div = <3>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk13";
+	};
+
+	chipclk14: chipclk14 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1>;
+		clock-div = <4>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk14";
+	};
+
+	chipclk16: chipclk16 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1>;
+		clock-div = <6>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk16";
+	};
+
+	chipclk112: chipclk112 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1>;
+		clock-div = <12>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk112";
+	};
+
+	chipclk124: chipclk124 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1>;
+		clock-div = <24>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk114";
+	};
+
+	chipclk1rstiso13: chipclk1rstiso13 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1rstiso>;
+		clock-div = <3>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk1rstiso13";
+	};
+
+	chipclk1rstiso14: chipclk1rstiso14 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1rstiso>;
+		clock-div = <4>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk1rstiso14";
+	};
+
+	chipclk1rstiso16: chipclk1rstiso16 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1rstiso>;
+		clock-div = <6>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk1rstiso16";
+	};
+
+	chipclk1rstiso112: chipclk1rstiso112 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&chipclk1rstiso>;
+		clock-div = <12>;
+		clock-mult = <1>;
+		clock-output-names = "chipclk1rstiso112";
+	};
+
+	clkmodrst0: clkmodrst0 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk16>;
+		clock-output-names = "modrst0";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+
+	clkusb: clkusb {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk16>;
+		clock-output-names = "usb";
+		reg = <0x02350008 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkaemifspi: clkaemifspi {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk16>;
+		clock-output-names = "aemif-spi";
+		reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+
+	clkdebugsstrc: clkdebugsstrc {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "debugss-trc";
+		reg = <0x02350014 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clktetbtrc: clktetbtrc {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "tetb-trc";
+		reg = <0x02350018 0xb00>, <0x02350004 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <1>;
+	};
+
+	clkpa: clkpa {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk16>;
+		clock-output-names = "pa";
+		reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <2>;
+	};
+
+	clkcpgmac: clkcpgmac {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkpa>;
+		clock-output-names = "cpgmac";
+		reg = <0x02350020 0xb00>, <0x02350008 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <2>;
+	};
+
+	clksa: clksa {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkpa>;
+		clock-output-names = "sa";
+		reg = <0x02350024 0xb00>, <0x02350008 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <2>;
+	};
+
+	clkpcie: clkpcie {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk12>;
+		clock-output-names = "pcie";
+		reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <3>;
+	};
+
+	clksrio: clksrio {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1rstiso13>;
+		clock-output-names = "srio";
+		reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <4>;
+	};
+
+	clkhyperlink0: clkhyperlink0 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk12>;
+		clock-output-names = "hyperlink-0";
+		reg = <0x02350030 0xb00>, <0x02350014 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <5>;
+	};
+
+	clksr: clksr {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1rstiso112>;
+		clock-output-names = "sr";
+		reg = <0x02350034 0xb00>, <0x02350018 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <6>;
+	};
+
+	clkmsmcsram: clkmsmcsram {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1>;
+		clock-output-names = "msmcsram";
+		reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <7>;
+	};
+
+	clkgem0: clkgem0 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1>;
+		clock-output-names = "gem0";
+		reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <8>;
+	};
+
+	clkgem1: clkgem1 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1>;
+		clock-output-names = "gem1";
+		reg = <0x02350040 0xb00>, <0x02350024 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <9>;
+	};
+
+	clkgem2: clkgem2 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1>;
+		clock-output-names = "gem2";
+		reg = <0x02350044 0xb00>, <0x02350028 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <10>;
+	};
+
+	clkgem3: clkgem3 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1>;
+		clock-output-names = "gem3";
+		reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <11>;
+	};
+
+	clkgem4: clkgem4 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1>;
+		clock-output-names = "gem4";
+		reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <12>;
+	};
+
+	clkgem5: clkgem5 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1>;
+		clock-output-names = "gem5";
+		reg = <0x02350050 0xb00>, <0x02350034 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <13>;
+	};
+
+	clkgem6: clkgem6 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1>;
+		clock-output-names = "gem6";
+		reg = <0x02350054 0xb00>, <0x02350038 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <14>;
+	};
+
+	clkgem7: clkgem7 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk1>;
+		clock-output-names = "gem7";
+		reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <15>;
+	};
+
+	clkddr30: clkddr30 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk12>;
+		clock-output-names = "ddr3-0";
+		reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <16>;
+	};
+
+	clkddr31: clkddr31 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "ddr3-1";
+		reg = <0x02350060 0xb00>, <0x02350040 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <16>;
+	};
+
+	clktac: clktac {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "tac";
+		reg = <0x02350064 0xb00>, <0x02350044 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <17>;
+	};
+
+	clkrac01: clktac01 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "rac-01";
+		reg = <0x02350068 0xb00>, <0x02350044 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <17>;
+	};
+
+	clkrac23: clktac23 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "rac-23";
+		reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <18>;
+	};
+
+	clkfftc0: clkfftc0 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "fftc-0";
+		reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <19>;
+	};
+
+	clkfftc1: clkfftc1 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "fftc-1";
+		reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <19>;
+	};
+
+	clkfftc2: clkfftc2 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "fftc-2";
+		reg = <0x02350078 0xb00>, <0x02350050 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <20>;
+	};
+
+	clkfftc3: clkfftc3 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "fftc-3";
+		reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <20>;
+	};
+
+	clkfftc4: clkfftc4 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "fftc-4";
+		reg = <0x02350080 0xb00>, <0x02350050 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <20>;
+	};
+
+	clkfftc5: clkfftc5 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "fftc-5";
+		reg = <0x02350084 0xb00>, <0x02350050 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <20>;
+	};
+
+	clkaif: clkaif {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "aif";
+		reg = <0x02350088 0xb00>, <0x02350054 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <21>;
+	};
+
+	clktcp3d0: clktcp3d0 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "tcp3d-0";
+		reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <22>;
+	};
+
+	clktcp3d1: clktcp3d1 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "tcp3d-1";
+		reg = <0x02350090 0xb00>, <0x02350058 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <22>;
+	};
+
+	clktcp3d2: clktcp3d2 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "tcp3d-2";
+		reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <23>;
+	};
+
+	clktcp3d3: clktcp3d3 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "tcp3d-3";
+		reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <23>;
+	};
+
+	clkvcp0: clkvcp0 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "vcp-0";
+		reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <24>;
+	};
+
+	clkvcp1: clkvcp1 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "vcp-1";
+		reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <24>;
+	};
+
+	clkvcp2: clkvcp2 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "vcp-2";
+		reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <24>;
+	};
+
+	clkvcp3: clkvcp3 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "vcp-3";
+		reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <24>;
+	};
+
+	clkvcp4: clkvcp4 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "vcp-4";
+		reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <25>;
+	};
+
+	clkvcp5: clkvcp5 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "vcp-5";
+		reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <25>;
+	};
+
+	clkvcp6: clkvcp6 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "vcp-6";
+		reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <25>;
+	};
+
+	clkvcp7: clkvcp7 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "vcp-7";
+		reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <25>;
+	};
+
+	clkbcp: clkbcp {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "bcp";
+		reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <26>;
+	};
+
+	clkdxb: clkdxb {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "dxb";
+		reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <27>;
+	};
+
+	clkhyperlink1: clkhyperlink1 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk12>;
+		clock-output-names = "hyperlink-1";
+		reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <28>;
+	};
+
+	clkxge: clkxge {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk13>;
+		clock-output-names = "xge";
+		reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <29>;
+	};
+
+	clkwdtimer0: clkwdtimer0 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "timer0";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkwdtimer1: clkwdtimer1 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "timer1";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkwdtimer2: clkwdtimer2 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "timer2";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkwdtimer3: clkwdtimer3 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "timer3";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkuart0: clkuart0 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "uart0";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkuart1: clkuart1 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "uart1";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkaemif: clkaemif {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkaemifspi>;
+		clock-output-names = "aemif";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkusim: clkusim {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "usim";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clki2c: clki2c {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "i2c";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkspi: clkspi {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkaemifspi>;
+		clock-output-names = "spi";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkgpio: clkgpio {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "gpio";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+
+	clkkeymgr: clkkeymgr {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&clkmodrst0>;
+		clock-output-names = "keymgr";
+		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};
+};

arch/arm/boot/dts/keystone.dts +2 -0

index 1334b42..57a7cd9 100644
@@ -93,6 +93,8 @@
 			reg = <0x023100e8 4>;	/* pll reset control reg */
 		};
 
+		/include/ "keystone-clocks.dtsi"
+
 		uart0: serial at 02530c00 {
 			compatible = "ns16550a";
 			current-speed = <115200>;

Signature · 1 line

1.7.9.5

Santosh Shilimkar

author

2013-08-29 23:36 UTC #2 lore raw

PATCH v2 2/4 ARM: dts: keystone: Add clock phandle to UART nodes

In reply to Santosh Shilimkar

Now since the clock tree is added, update UART dt nodes with clock data.

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/boot/dts/keystone.dts |    2 ++
 1 file changed, 2 insertions(+)

arch/arm/boot/dts/keystone.dts +2 -0

index 57a7cd9..5a2d632 100644
@@ -102,6 +102,7 @@
 			reg-io-width = <4>;
 			reg = <0x02530c00 0x100>;
 			clock-frequency = <133120000>;
+			clocks	= <&clkuart0>;
 			interrupts = <0 277 0xf01>;
 		};

@@ -112,6 +113,7 @@
 			reg-io-width = <4>;
 			reg = <0x02531000 0x100>;
 			clock-frequency = <133120000>;
+			clocks	= <&clkuart1>;
 			interrupts = <0 280 0xf01>;
 		};

Signature · 1 line

1.7.9.5

Santosh Shilimkar

author

2013-08-29 23:36 UTC #3 lore raw

PATCH v2 3/4 ARM: keystone: Enable clock drivers

In reply to Santosh Shilimkar

Enable common clock drivers on Keystone 2 based SOCs.

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/mach-keystone/Kconfig |    1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-keystone/Kconfig +1 -0

index 51a50e9..f912776 100644
@@ -10,6 +10,7 @@ config ARCH_KEYSTONE
 	select HAVE_SCHED_CLOCK
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_ERRATA_798181 if SMP
+	select COMMON_CLK_KEYSTONE
 	help
 	  Support for boards based on the Texas Instruments Keystone family of
 	  SoCs.

Signature · 1 line

1.7.9.5

Santosh Shilimkar

author

2013-08-29 23:36 UTC #4 lore raw

PATCH v2 4/4 ARM: keystone: add PM bus support for clock management

In reply to Santosh Shilimkar

Add runtime PM core support to Keystone SOCs by using the pm_clk infrastructure of the PM core. Patch is based on Kevin's pm_domain work on DaVinci SOCs.

Keystone SOC doesn't have depedency to enable clocks in early in the boot and hence the clock and PM bus initialisation is done at subsys_init() level.

Cc Kevin Hilman <[email protected]>

Signed-off-by Santosh Shilimkar <[email protected]>

---
 drivers/bus/Makefile          |    2 ++
 drivers/bus/keystone_pm_bus.c |   70 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+)
 create mode 100644 drivers/bus/keystone_pm_bus.c

drivers/bus/Makefile +2 -0

index 8947bdd..cb7f304 100644
@@ -10,3 +10,5 @@ obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 obj-$(CONFIG_OMAP_INTERCONNECT)	+= omap_l3_smx.o omap_l3_noc.o
 # CCI cache coherent interconnect for ARM platforms
 obj-$(CONFIG_ARM_CCI)		+= arm-cci.o
+# PM bus driver for Keystone SOCs
+obj-$(CONFIG_ARCH_KEYSTONE)	+= keystone_pm_bus.o

drivers/bus/keystone_pm_bus.c new file +70 -0

70 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Kevin Hilman

2013-08-30 16:18 UTC #5 lore raw

PATCH v2 4/4 ARM: keystone: add PM bus support for clock management

Quoted 8 lines · Santosh Shilimkar

Add runtime PM core support to Keystone SOCs by using the pm_clk infrastructure of the PM core. Patch is based on Kevin's pm_domain work on DaVinci SOCs.
Keystone SOC doesn't have depedency to enable clocks in early in the boot and hence the clock and PM bus initialisation is done at subsys_init() level.

Quoted 6 lines

Cc Kevin Hilman <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---
 drivers/bus/Makefile          |    2 ++
 drivers/bus/keystone_pm_bus.c |   70 +++++++++++++++++++++++++++++++++++++++++

Maybe I missed some earlier discussion on this, but why drivers/bus?

I called the davinci stuff 'bus' initially because it piggy-backed the platform_bus, but now that we have pm_domains, it's using that, and is unrelated the bus.

Therefore, as with davinci, I suspect this belongs in mach-keystone.

[...]

Quoted 6 lines

drivers/bus/keystone_pm_bus.c new file +0 -0
new file mode 100644
index 0000000..6cc56f1

drivers/bus/keystone_pm_bus.c line 8

Quoted 8 lines

drivers/bus/keystone_pm_bus.c new file +8 -0

@@ -0,0 +1,70 @@
+/*
+ * PM Bus driver for Keystone2 devices
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *	Santosh Shilimkar <[email protected]>
+ *
+ * Based on Kevins work on DAVINCI SOCs
+ *	Kevin Hilman <[email protected]>

Dead email address (as you know) ;) You can just leave off the email, or use khilman at kernel.org as one that shouldn't change.

Kevin

Santosh Shilimkar

author

2013-08-30 16:25 UTC #6 lore raw

PATCH v2 4/4 ARM: keystone: add PM bus support for clock management

Quoted 17 lines · Kevin Hilman

Quoted 8 lines · Santosh Shilimkar
Add runtime PM core support to Keystone SOCs by using the pm_clk infrastructure of the PM core. Patch is based on Kevin's pm_domain work on DaVinci SOCs.
Keystone SOC doesn't have depedency to enable clocks in early in the boot and hence the clock and PM bus initialisation is done at subsys_init() level.
Quoted 6 lines
Cc Kevin Hilman <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---
 drivers/bus/Makefile          |    2 ++
 drivers/bus/keystone_pm_bus.c |   70 +++++++++++++++++++++++++++++++++++++++++

Quoted 8 lines

Maybe I missed some earlier discussion on this, but why drivers/bus?
I called the davinci stuff 'bus' initially because it piggy-backed the platform_bus, but now that we have pm_domains, it's using that, and is unrelated the bus.
Therefore, as with davinci, I suspect this belongs in mach-keystone.

There is not much keystone specific code and hence thought it doesn't have to be part of mach-keystone/*. drivers/bus/* I picked out of hat ;-) thinking it is much of PM bus code. I couldn't find a better place than that. Any other better place you can suggest ??

Quoted 11 lines

[...]
Quoted 9 lines
drivers/bus/keystone_pm_bus.c new file +3 -0
new file mode 100644
index 0000000..6cc56f1
@@ -0,0 +1,70 @@
+/*
+ * PM Bus driver for Keystone2 devices
+ *

Quoted 9 lines

drivers/bus/keystone_pm_bus.c line 8
Quoted 5 lines
drivers/bus/keystone_pm_bus.c new file +5 -0
+ * Copyright 2013 Texas Instruments, Inc.
+ *	Santosh Shilimkar <[email protected]>
+ *
+ * Based on Kevins work on DAVINCI SOCs
+ *	Kevin Hilman <[email protected]>
Dead email address (as you know) ;) You can just leave off the email, or use khilman at kernel.org as one that shouldn't change.

Sorry I will fix that. Will use "khilman at kernel.org".

Regards,
Santosh

Santosh Shilimkar

author

2013-10-11 00:15 UTC #7 lore raw

PATCH v2 4/4 ARM: keystone: add PM bus support for clock management

In reply to Santosh Shilimkar

Quoted 4 lines · Santosh Shilimkar

Add runtime PM core support to Keystone SOCs by using the pm_clk infrastructure of the PM core. Patch is based on Kevin's pm_domain work on DaVinci SOCs.

Quoted 8 lines

Keystone SOC doesn't have depedency to enable clocks in early in the boot and hence the clock and PM bus initialisation is done at subsys_init() level.
Cc Kevin Hilman <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---

For record, updated patch end of the email as discussed here [1]

Regards,
Santosh

[1] http://www.spinics.net/lists/arm-kernel/msg278991.html

Quoted 1 line

From fc20ffe1213beb09bb7fb6687b404fe48183a55e Mon Sep 17 00:00:00 2001

From: Santosh Shilimkar <[email protected]>
Date: Sun, 14 Jul 2013 17:17:39 -0400
Subject: [PATCH 4/4] ARM: keystone: add PM domain support for clock
management

Add runtime PM core support to Keystone SOCs by using the pm_clk infrastructure of the PM core. Patch is based on Kevin's pm_domain work on DaVinci SOCs.

Keystone SOC doesn't have dependency to enable clocks in early in the boot and hence the clock and PM domain initialisation is done at subsys_init() level.

Cc Kevin Hilman <[email protected]>

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/mach-keystone/Makefile    |    3 ++
 arch/arm/mach-keystone/pm_domain.c |   70 ++++++++++++++++++++++++++++++++++++
 2 files changed, 73 insertions(+)
 create mode 100644 arch/arm/mach-keystone/pm_domain.c

arch/arm/mach-keystone/Makefile +3 -0

index ddc52b0..25d9239 100644
@@ -4,3 +4,6 @@ plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_smc.o				:=-Wa,-march=armv7-a$(plus_sec)
 
 obj-$(CONFIG_SMP)			+= platsmp.o
+
+# PM domain driver for Keystone SOCs
+obj-$(CONFIG_ARCH_KEYSTONE)		+= pm_domain.o

arch/arm/mach-keystone/pm_domain.c new file +70 -0

70 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Kevin Hilman

2013-10-14 17:32 UTC #8 lore raw

PATCH v2 4/4 ARM: keystone: add PM bus support for clock management

Quoted 9 lines · Santosh Shilimkar

Quoted 8 lines · Santosh Shilimkar
Add runtime PM core support to Keystone SOCs by using the pm_clk infrastructure of the PM core. Patch is based on Kevin's pm_domain work on DaVinci SOCs.
Keystone SOC doesn't have depedency to enable clocks in early in the boot and hence the clock and PM bus initialisation is done at subsys_init() level.

Quoted 5 lines

Quoted 4 lines
Cc Kevin Hilman <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
---
For record, updated patch end of the email as discussed here [1]

Unfortunately, this one broke boot for muilti_v7_defconfig:

http://lists.linaro.org/pipermail/kernel-build-reports/2013-October/000652.html

[...]

Review

Quoted 8 lines

(quoted diff) +8 -0

+int __init keystone_pm_runtime_init(void)
+{
+	of_clk_init(NULL);
+	pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier);
+
+	return 0;
+}
+subsys_initcall(keystone_pm_runtime_init);

The reason is this initcall which runs on *all* platforms, so needs some sort of platform specific check.

The patch below does the trick, but I'm not sure if you want to match on something more specific for this check. If you're OK, with this, I'll add it to next/soc with your ack.

Kevin

Quoted 1 line

From 435ed298c804048548276b60fd5efdf697f6b82f Mon Sep 17 00:00:00 2001

From: Kevin Hilman <[email protected]>
Date: Mon, 14 Oct 2013 10:30:11 -0700
Subject: [PATCH] ARM: keystone: fix PM domain initcall to be keystone only

initcalls need to have platform specific checks so they are not run in multi-platform builds.

Cc Santosh Shilimkar <[email protected]>

Signed-off-by Kevin Hilman <[email protected]>

---
 arch/arm/mach-keystone/pm_domain.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/mach-keystone/pm_domain.c +12 -0

index beac3fb..2962523 100644
@@ -17,6 +17,7 @@
 #include <linux/pm_clock.h>
 #include <linux/platform_device.h>
 #include <linux/clk-provider.h>
+#include <linux/of.h>
 
 #ifdef CONFIG_PM_RUNTIME
 static int keystone_pm_runtime_suspend(struct device *dev)

@@ -60,8 +61,19 @@ static struct pm_clk_notifier_block platform_domain_notifier = {
 	.pm_domain = &keystone_pm_domain,
 };
 
+static struct of_device_id of_keystone_table[] = {
+	{.compatible = "ti,keystone"},
+	{ /* end of list */ },
+};
+
 int __init keystone_pm_runtime_init(void)
 {
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, of_keystone_table);
+	if (!np)
+		return 0;
+
 	of_clk_init(NULL);
 	pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier);

Signature · 1 line

1.8.3

Santosh Shilimkar

author

2013-10-14 18:00 UTC #9 lore raw

PATCH v2 4/4 ARM: keystone: add PM bus support for clock management

Quoted 13 lines · Kevin Hilman

Quoted 11 lines · Santosh Shilimkar
Quoted 10 lines · Santosh Shilimkar
Add runtime PM core support to Keystone SOCs by using the pm_clk infrastructure of the PM core. Patch is based on Kevin's pm_domain work on DaVinci SOCs.
Keystone SOC doesn't have depedency to enable clocks in early in the boot and hence the clock and PM bus initialisation is done at subsys_init() level.
Cc Kevin Hilman <[email protected]>

Quoted 8 lines

Quoted 3 lines
Quoted 2 lines
Signed-off-by Santosh Shilimkar <[email protected]>
---
For record, updated patch end of the email as discussed here [1]
Unfortunately, this one broke boot for muilti_v7_defconfig:
   http://lists.linaro.org/pipermail/kernel-build-reports/2013-October/000652.html

Damn. Sorry about that.

Quoted 25 lines

[...]
Review
Quoted 8 lines
(quoted diff) +8 -0
+int __init keystone_pm_runtime_init(void)
+{
+	of_clk_init(NULL);
+	pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier);
+
+	return 0;
+}
+subsys_initcall(keystone_pm_runtime_init);
The reason is this initcall which runs on *all* platforms, so needs some sort of platform specific check.
The patch below does the trick, but I'm not sure if you want to match on something more specific for this check. If you're OK, with this, I'll add it to next/soc with your ack.
Kevin
From 435ed298c804048548276b60fd5efdf697f6b82f Mon Sep 17 00:00:00 2001
From: Kevin Hilman <[email protected]>
Date: Mon, 14 Oct 2013 10:30:11 -0700
Subject: [PATCH] ARM: keystone: fix PM domain initcall to be keystone only

Quoted 6 lines

initcalls need to have platform specific checks so they are not run in multi-platform builds.
Cc Santosh Shilimkar <[email protected]>
Signed-off-by Kevin Hilman <[email protected]>
---

Acked-by Santosh Shilimkar <[email protected]>

Looks right. Thanks a lot Kevin.

Kevin Hilman

2013-10-14 18:18 UTC #10 lore raw

PATCH v2 4/4 ARM: keystone: add PM bus support for clock management

Quoted 50 lines · Santosh Shilimkar

Quoted 13 lines · Kevin Hilman
Quoted 11 lines · Santosh Shilimkar
Quoted 10 lines · Santosh Shilimkar
Add runtime PM core support to Keystone SOCs by using the pm_clk infrastructure of the PM core. Patch is based on Kevin's pm_domain work on DaVinci SOCs.
Keystone SOC doesn't have depedency to enable clocks in early in the boot and hence the clock and PM bus initialisation is done at subsys_init() level.
Cc Kevin Hilman <[email protected]>
Quoted 8 lines
Quoted 3 lines
Quoted 2 lines
Signed-off-by Santosh Shilimkar <[email protected]>
---
For record, updated patch end of the email as discussed here [1]
Unfortunately, this one broke boot for muilti_v7_defconfig:
   http://lists.linaro.org/pipermail/kernel-build-reports/2013-October/000652.html
Damn. Sorry about that.
Quoted 25 lines
[...]
Review
Quoted 8 lines
(quoted diff) +8 -0
+int __init keystone_pm_runtime_init(void)
+{
+	of_clk_init(NULL);
+	pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier);
+
+	return 0;
+}
+subsys_initcall(keystone_pm_runtime_init);
The reason is this initcall which runs on *all* platforms, so needs some sort of platform specific check.
The patch below does the trick, but I'm not sure if you want to match on something more specific for this check. If you're OK, with this, I'll add it to next/soc with your ack.
Kevin
From 435ed298c804048548276b60fd5efdf697f6b82f Mon Sep 17 00:00:00 2001
From: Kevin Hilman <[email protected]>
Date: Mon, 14 Oct 2013 10:30:11 -0700
Subject: [PATCH] ARM: keystone: fix PM domain initcall to be keystone only

Quoted 8 lines

Quoted 6 lines
initcalls need to have platform specific checks so they are not run in multi-platform builds.
Cc Santosh Shilimkar <[email protected]>
Signed-off-by Kevin Hilman <[email protected]>
---
Acked-by Santosh Shilimkar <[email protected]>
Looks right. Thanks a lot Kevin.

Thanks, appled to next/soc after keystone/soc merge.

Kevin