am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF
PATCH 1/1 am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF
Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches.
--- arch/arm/cpu/armv7/am33xx/board.c | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/arm/cpu/armv7/am33xx/board.c +8 -0
@@ -225,3 +225,11 @@ void s_init(void)sdram_init ();#endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); +} +#endif /* !CONFIG_SYS_DCACHE_OFF */
Signature · 1 line
1.7.9.5
PATCH 1/1 am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF
Hi Tom,
Quoted 14 lines · Tom Rini
Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches.
Signed-off-by Tom Rini <[email protected]>--- arch/arm/cpu/armv7/am33xx/board.c | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm/cpu/armv7/am33xx/board.c +0
-0@@ -225,3 +225,11 @@ void s_init(void)sdram_init ();
arch/arm/cpu/armv7/am33xx/board.c void s_init(void) · line 235
Quoted 10 lines
arch/arm/cpu/armv7/am33xx/board.c +8
-0#endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); +} +#endif /* !CONFIG_SYS_DCACHE_OFF */
This is fine. Do we have secure devices here ?
If so, we should take care of setting the domains permissions for avoiding prefetch aborts. As it was done for OMAP using arm_init_domains. So that function and the above should be executed on am33xx as well.
Thanks to Lokesh for reminding this.
Regards,
Sricharan
PATCH 1/1 am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF
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Hash: SHA1
Quoted 29 lines · Sricharan R
Hi Tom,
Quoted 14 lines · Tom Rini
Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches.
Signed-off-by Tom Rini <[email protected]>--- arch/arm/cpu/armv7/am33xx/board.c | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm/cpu/armv7/am33xx/board.c +0
-0@@ -225,3 +225,11 @@ void s_init(void)sdram_init ();arch/arm/cpu/armv7/am33xx/board.c void s_init(void) · line 235
Quoted 10 lines
arch/arm/cpu/armv7/am33xx/board.c +8
-0#endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); +} +#endif /* !CONFIG_SYS_DCACHE_OFF */ This is fine. Do we have secure devices here ?
Quoted 6 lines
If so, we should take care of setting the domains permissions for avoiding prefetch aborts. As it was done for OMAP using
arm_init_domains. So that function and the above should be executed on am33xx as well.Thanks to Lokesh for reminding this.
Yes, but I can't easily test them. I'll see if arm_init_domains just works on non-HS devices (I know I had a failure pulling all the OMAP4 code over, but didn't try hard, just looked again at the "easy" path).
- --
Tom
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PATCH 1/1 am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF
Quoted 38 lines · Tom Rini
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Hash: SHA1Quoted 34 lines · Sricharan R
Hi Tom,
Quoted 14 lines · Tom Rini
Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches.
Signed-off-by Tom Rini <[email protected]>--- arch/arm/cpu/armv7/am33xx/board.c | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm/cpu/armv7/am33xx/board.c +0
-0@@ -225,3 +225,11 @@ void s_init(void)sdram_init ();arch/arm/cpu/armv7/am33xx/board.c void s_init(void) · line 235
Quoted 10 lines
arch/arm/cpu/armv7/am33xx/board.c +8
-0#endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); +} +#endif /* !CONFIG_SYS_DCACHE_OFF */ This is fine. Do we have secure devices here ?
If so, we should take care of setting the domains permissions for avoiding prefetch aborts. As it was done for OMAP using
arm_init_domains. So that function and the above should be executed on am33xx as well.
Quoted 5 lines
Quoted 1 line
Thanks to Lokesh for reminding this.
Yes, but I can't easily test them. I'll see if
arm_init_domainsjust works on non-HS devices (I know I had a failure pulling all the OMAP4 code over, but didn't try hard, just looked again at the "easy" path).
Yeah, that code as-is hangs the boards. So if the HS devices need something, it'll go with the rest of their patches until we're moving it upstream. But good to note a potential problem area!
Signature · 8 lines
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PATCH 1/1 am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF
Hi Tom,
Quoted 42 lines · Tom Rini
Quoted 40 lines · Tom Rini
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Hash: SHA1Quoted 35 lines · Sricharan R
Hi Tom,
Quoted 14 lines · Tom Rini
Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches.
Signed-off-by Tom Rini <[email protected]>--- arch/arm/cpu/armv7/am33xx/board.c | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm/cpu/armv7/am33xx/board.c +0
-0@@ -225,3 +225,11 @@ void s_init(void)sdram_init ();arch/arm/cpu/armv7/am33xx/board.c void s_init(void) · line 235
Quoted 10 lines
arch/arm/cpu/armv7/am33xx/board.c +8
-0#endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); +} +#endif /* !CONFIG_SYS_DCACHE_OFF */ This is fine. Do we have secure devices here ?
If so, we should take care of setting the domains permissions for avoiding prefetch aborts. As it was done for OMAP using
arm_init_domains. So that function and the above should be executed on am33xx as well.Thanks to Lokesh for reminding this.
Quoted 7 lines
Quoted 3 lines
Yes, but I can't easily test them. I'll see if
arm_init_domainsjust works on non-HS devices (I know I had a failure pulling all the OMAP4 code over, but didn't try hard, just looked again at the "easy" path).Yeah, that code as-is hangs the boards. So if the HS devices need something, it'll go with the rest of their patches until we're moving it upstream. But good to note a potential problem area!
I added the following diff and I am able to boot my BBB over cpsw.
arch/arm/cpu/armv7/am33xx/board.c +42 -0
@@ -31,6 +31,11 @@#include <linux/usb/gadget.h> #include <linux/usb/musb.h> #include <asm/omap_musb.h> +#include <asm/cache.h> + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0)DECLARE_GLOBAL_DATA_PTR ;
@@ -225,3 +230,40 @@ void s_init(void)sdram_init ();#endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); +} + +void dram_bank_mmu_setup (int bank) +{ +bd_t *bd = gd->bd; +int i; + +u32 start = bd->bi_dram[bank].start >>20 ; +u32 size = bd->bi_dram[bank].size >>20 ; +u32 end = start + size; + +debug ("%s: bank: %d\n" , __func__, bank); +for (i = start; i < end; i++) +set_section_dcache (i,ARMV7_DCACHE_WRITEBACK ); + +} + +void arm_init_domains (void ) +{ +u32 reg; + + reg =get_dacr (); +/* +* Set DOMAIN to client access so that all permissions +* set in pagetables are validated by the mmu. +*/ + reg &= ~ARMV7_DOMAIN_MASK ; + reg |=ARMV7_DOMAIN_CLIENT ; +set_dacr (reg); +} +#endif
AM I missing something here ?
Thanks and regards,
Lokesh
Quoted 8 lines
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PATCH 1/1 am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF
Quoted 111 lines · Lokesh Vutla
Hi Tom,
Quoted 42 lines · Tom Rini
Quoted 40 lines · Tom Rini
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Hash: SHA1Quoted 35 lines · Sricharan R
Hi Tom,
Quoted 14 lines · Tom Rini
Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches.
Signed-off-by Tom Rini <[email protected]>--- arch/arm/cpu/armv7/am33xx/board.c | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm/cpu/armv7/am33xx/board.c +0
-0@@ -225,3 +225,11 @@ void s_init(void)sdram_init ();arch/arm/cpu/armv7/am33xx/board.c void s_init(void) · line 235
Quoted 10 lines
arch/arm/cpu/armv7/am33xx/board.c +8
-0#endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); +} +#endif /* !CONFIG_SYS_DCACHE_OFF */ This is fine. Do we have secure devices here ?
If so, we should take care of setting the domains permissions for avoiding prefetch aborts. As it was done for OMAP using
arm_init_domains. So that function and the above should be executed on am33xx as well.Thanks to Lokesh for reminding this.
Quoted 7 lines
Quoted 3 lines
Yes, but I can't easily test them. I'll see if
arm_init_domainsjust works on non-HS devices (I know I had a failure pulling all the OMAP4 code over, but didn't try hard, just looked again at the "easy" path).Yeah, that code as-is hangs the boards. So if the HS devices need something, it'll go with the rest of their patches until we're moving it upstream. But good to note a potential problem area!
I added the following diff and I am able to boot my BBB over cpsw.
arch/arm/cpu/armv7/am33xx/board.c +42
-0@@ -31,6 +31,11 @@#include <linux/usb/gadget.h> #include <linux/usb/musb.h> #include <asm/omap_musb.h> +#include <asm/cache.h> + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0)DECLARE_GLOBAL_DATA_PTR ;@@ -225,3 +230,40 @@ void s_init(void)sdram_init ();#endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); +} + +void dram_bank_mmu_setup (int bank) +{ +bd_t *bd = gd->bd; +int i; + +u32 start = bd->bi_dram[bank].start >>20 ; +u32 size = bd->bi_dram[bank].size >>20 ; +u32 end = start + size; + +debug ("%s: bank: %d\n" , __func__, bank); +for (i = start; i < end; i++) +set_section_dcache (i,ARMV7_DCACHE_WRITEBACK ); + +} + +void arm_init_domains (void ) +{ +u32 reg; + + reg =get_dacr (); +/* +* Set DOMAIN to client access so that all permissions +* set in pagetables are validated by the mmu. +*/ + reg &= ~ARMV7_DOMAIN_MASK ; + reg |=ARMV7_DOMAIN_CLIENT ; +set_dacr (reg); +} +#endif
Quoted 1 line
AM I missing something here ?
Or I am. That gives me a straight up hang, like I saw before. What toolchain are you using? I'm trying ELDK 5.2 and Linaro 2013.04.
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Quoted 4 lines · Tom Rini
Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches.
Signed-off-by Tom Rini <[email protected]>
Applied to u-boot-ti/master, thanks!
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