clk/exynos convert clock IDs to macros
v2 cover clk/exynos convert clock IDs to macros
Hi,
This patch set adds headers with defines of exynos clocks. Then it converts dts files and drivers to use macros instead of magic numbers/enums to describe clock bindings.
The patch set is based on the latest mturquette/clk-next branch.
The patches are generated by script.
I have verified random clocks by hand.
I have also tested it on exynos4 based board.
This is the 2nd version of the patchset.
Changes:
- corrected devicetree mailing list,
- added comments to include/dt-bindings/clock/exynos4.h for clocks present only in particular chip,
- added tab alignement in headers,
- added comment to CLK_NR_CLKS,
- added copyright headers,
- split long lines in dts,
- corrected example in bindings/clock/exynos5250-clock.txt, to point appropriate clocks.
Regards
Andrzej
Andrzej Hajda (12):
ARM: exynos4: create a DT header defining CLK IDs
ARM: dts: exynos4: convert magic numbers to macros in clock bindings
clk: exynos4: replace clock ID private enums with IDs from DT header
ARM: exynos5250: create a DT header defining CLK IDs
ARM: dts: exynos5250: convert magic numbers to macros in clock
bindings
clk: exynos5250: replace clock ID private enums with IDs from DT
header
ARM: exynos5420: create a DT header defining CLK IDs
ARM: dts: exynos5420: convert magic numbers to macros in clock
bindings
clk: exynos5420: replace clock ID private enums with IDs from DT
header
ARM: exynos5440: create a DT header defining CLK IDs
ARM: dts: exynos5440: convert magic numbers to macros in clock
bindings
clk: exynos5440: replace clock ID private enums with IDs from DT
header
.../devicetree/bindings/clock/exynos4-clock.txt | 259 +------ .../devicetree/bindings/clock/exynos5250-clock.txt | 160 +--- .../devicetree/bindings/clock/exynos5420-clock.txt | 184 +---- .../devicetree/bindings/clock/exynos5440-clock.txt | 45 +- arch/arm/boot/dts/exynos4.dtsi | 55 +- arch/arm/boot/dts/exynos4210.dtsi | 6 +- arch/arm/boot/dts/exynos4412.dtsi | 2 +- arch/arm/boot/dts/exynos4x12.dtsi | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 92 +-- arch/arm/boot/dts/exynos5420.dtsi | 13 +- arch/arm/boot/dts/exynos5440.dtsi | 27 +- drivers/clk/samsung/clk-exynos4.c | 857 ++++++++++----------- drivers/clk/samsung/clk-exynos5250.c | 501 ++++++------ drivers/clk/samsung/clk-exynos5420.c | 648 ++++++++-------- drivers/clk/samsung/clk-exynos5440.c | 81 +- include/dt-bindings/clock/exynos4.h | 244 ++++++ include/dt-bindings/clock/exynos5250.h | 157 ++++ include/dt-bindings/clock/exynos5420.h | 188 +++++ include/dt-bindings/clock/exynos5440.h | 42 + 19 files changed, 1734 insertions(+), 1829 deletions(-) create mode 100644 include/dt-bindings/clock/exynos4.h create mode 100644 include/dt-bindings/clock/exynos5250.h create mode 100644 include/dt-bindings/clock/exynos5420.h create mode 100644 include/dt-bindings/clock/exynos5440.h
Signature · 1 line
1.8.1.2
PATCH v2 1/12 ARM: exynos4: create a DT header defining CLK IDs
The patch adds header file defining clock IDs.
This allows to use macros instead of magic numbers in DT bindings.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- include/dt-bindings/clock/exynos4.h | 244 ++++++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) create mode 100644 include/dt-bindings/clock/exynos4.h
include/dt-bindings/clock/exynos4.h new file +244 -0
@@ -0,0 +1,244 @@ +/* +* Copyright (c) 2013 Samsung Electronics Co., Ltd. +* Author: Andrzej Haja <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* Device Tree binding constants for Exynos4 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H +#define _DT_BINDINGS_CLOCK_EXYNOS_4_H + +/* core clocks */ +#define CLK_XXTI 1 +#define CLK_XUSBXTI 2 +#define CLK_FIN_PLL 3 +#define CLK_FOUT_APLL 4 +#define CLK_FOUT_MPLL 5 +#define CLK_FOUT_EPLL 6 +#define CLK_FOUT_VPLL 7 +#define CLK_SCLK_APLL 8 +#define CLK_SCLK_MPLL 9 +#define CLK_SCLK_EPLL 10 +#define CLK_SCLK_VPLL 11 +#define CLK_ARM_CLK 12 +#define CLK_ACLK200 13 +#define CLK_ACLK100 14 +#define CLK_ACLK160 15 +#define CLK_ACLK133 16 +#define CLK_MOUT_MPLL_USER_T 17/* Exynos4x12 only */ +#define CLK_MOUT_MPLL_USER_C 18/* Exynos4x12 only */ +#define CLK_MOUT_CORE 19 +#define CLK_MOUT_APLL 20 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_FIMC0 128 +#define CLK_SCLK_FIMC1 129 +#define CLK_SCLK_FIMC2 130 +#define CLK_SCLK_FIMC3 131 +#define CLK_SCLK_CAM0 132 +#define CLK_SCLK_CAM1 133 +#define CLK_SCLK_CSIS0 134 +#define CLK_SCLK_CSIS1 135 +#define CLK_SCLK_HDMI 136 +#define CLK_SCLK_MIXER 137 +#define CLK_SCLK_DAC 138 +#define CLK_SCLK_PIXEL 139 +#define CLK_SCLK_FIMD0 140 +#define CLK_SCLK_MDNIE0 141/* Exynos4412 only */ +#define CLK_SCLK_MDNIE_PWM0 142 +#define CLK_SCLK_MIPI0 143 +#define CLK_SCLK_AUDIO0 144 +#define CLK_SCLK_MMC0 145 +#define CLK_SCLK_MMC1 146 +#define CLK_SCLK_MMC2 147 +#define CLK_SCLK_MMC3 148 +#define CLK_SCLK_MMC4 149 +#define CLK_SCLK_SATA 150/* Exynos4210 only */ +#define CLK_SCLK_UART0 151 +#define CLK_SCLK_UART1 152 +#define CLK_SCLK_UART2 153 +#define CLK_SCLK_UART3 154 +#define CLK_SCLK_UART4 155 +#define CLK_SCLK_AUDIO1 156 +#define CLK_SCLK_AUDIO2 157 +#define CLK_SCLK_SPDIF 158 +#define CLK_SCLK_SPI0 159 +#define CLK_SCLK_SPI1 160 +#define CLK_SCLK_SPI2 161 +#define CLK_SCLK_SLIMBUS 162 +#define CLK_SCLK_FIMD1 163/* Exynos4210 only */ +#define CLK_SCLK_MIPI1 164/* Exynos4210 only */ +#define CLK_SCLK_PCM1 165 +#define CLK_SCLK_PCM2 166 +#define CLK_SCLK_I2S1 167 +#define CLK_SCLK_I2S2 168 +#define CLK_SCLK_MIPIHSI 169/* Exynos4412 only */ +#define CLK_SCLK_MFC 170 +#define CLK_SCLK_PCM0 171 +#define CLK_SCLK_G3D 172 +#define CLK_SCLK_PWM_ISP 173/* Exynos4x12 only */ +#define CLK_SCLK_SPI0_ISP 174/* Exynos4x12 only */ +#define CLK_SCLK_SPI1_ISP 175/* Exynos4x12 only */ +#define CLK_SCLK_UART_ISP 176/* Exynos4x12 only */ +#define CLK_SCLK_FIMG2D 177 + +/* gate clocks */ +#define CLK_FIMC0 256 +#define CLK_FIMC1 257 +#define CLK_FIMC2 258 +#define CLK_FIMC3 259 +#define CLK_CSIS0 260 +#define CLK_CSIS1 261 +#define CLK_JPEG 262 +#define CLK_SMMU_FIMC0 263 +#define CLK_SMMU_FIMC1 264 +#define CLK_SMMU_FIMC2 265 +#define CLK_SMMU_FIMC3 266 +#define CLK_SMMU_JPEG 267 +#define CLK_VP 268 +#define CLK_MIXER 269 +#define CLK_TVENC 270/* Exynos4210 only */ +#define CLK_HDMI 271 +#define CLK_SMMU_TV 272 +#define CLK_MFC 273 +#define CLK_SMMU_MFCL 274 +#define CLK_SMMU_MFCR 275 +#define CLK_G3D 276 +#define CLK_G2D 277 +#define CLK_ROTATOR 278/* Exynos4210 only */ +#define CLK_MDMA 279/* Exynos4210 only */ +#define CLK_SMMU_G2D 280/* Exynos4210 only */ +#define CLK_SMMU_ROTATOR 281/* Exynos4210 only */ +#define CLK_SMMU_MDMA 282/* Exynos4210 only */ +#define CLK_FIMD0 283 +#define CLK_MIE0 284 +#define CLK_MDNIE0 285/* Exynos4412 only */ +#define CLK_DSIM0 286 +#define CLK_SMMU_FIMD0 287 +#define CLK_FIMD1 288/* Exynos4210 only */ +#define CLK_MIE1 289/* Exynos4210 only */ +#define CLK_DSIM1 290/* Exynos4210 only */ +#define CLK_SMMU_FIMD1 291/* Exynos4210 only */ +#define CLK_PDMA0 292 +#define CLK_PDMA1 293 +#define CLK_PCIE_PHY 294 +#define CLK_SATA_PHY 295/* Exynos4210 only */ +#define CLK_TSI 296 +#define CLK_SDMMC0 297 +#define CLK_SDMMC1 298 +#define CLK_SDMMC2 299 +#define CLK_SDMMC3 300 +#define CLK_SDMMC4 301 +#define CLK_SATA 302/* Exynos4210 only */ +#define CLK_SROMC 303 +#define CLK_USB_HOST 304 +#define CLK_USB_DEVICE 305 +#define CLK_PCIE 306 +#define CLK_ONENAND 307 +#define CLK_NFCON 308 +#define CLK_SMMU_PCIE 309 +#define CLK_GPS 310 +#define CLK_SMMU_GPS 311 +#define CLK_UART0 312 +#define CLK_UART1 313 +#define CLK_UART2 314 +#define CLK_UART3 315 +#define CLK_UART4 316 +#define CLK_I2C0 317 +#define CLK_I2C1 318 +#define CLK_I2C2 319 +#define CLK_I2C3 320 +#define CLK_I2C4 321 +#define CLK_I2C5 322 +#define CLK_I2C6 323 +#define CLK_I2C7 324 +#define CLK_I2C_HDMI 325 +#define CLK_TSADC 326 +#define CLK_SPI0 327 +#define CLK_SPI1 328 +#define CLK_SPI2 329 +#define CLK_I2S1 330 +#define CLK_I2S2 331 +#define CLK_PCM0 332 +#define CLK_I2S0 333 +#define CLK_PCM1 334 +#define CLK_PCM2 335 +#define CLK_PWM 336 +#define CLK_SLIMBUS 337 +#define CLK_SPDIF 338 +#define CLK_AC97 339 +#define CLK_MODEMIF 340 +#define CLK_CHIPID 341 +#define CLK_SYSREG 342 +#define CLK_HDMI_CEC 343 +#define CLK_MCT 344 +#define CLK_WDT 345 +#define CLK_RTC 346 +#define CLK_KEYIF 347 +#define CLK_AUDSS 348 +#define CLK_MIPI_HSI 349/* Exynos4210 only */ +#define CLK_MDMA2 350/* Exynos4210 only */ +#define CLK_PIXELASYNCM0 351 +#define CLK_PIXELASYNCM1 352 +#define CLK_FIMC_LITE0 353/* Exynos4x12 only */ +#define CLK_FIMC_LITE1 354/* Exynos4x12 only */ +#define CLK_PPMUISPX 355/* Exynos4x12 only */ +#define CLK_PPMUISPMX 356/* Exynos4x12 only */ +#define CLK_FIMC_ISP 357/* Exynos4x12 only */ +#define CLK_FIMC_DRC 358/* Exynos4x12 only */ +#define CLK_FIMC_FD 359/* Exynos4x12 only */ +#define CLK_MCUISP 360/* Exynos4x12 only */ +#define CLK_GICISP 361/* Exynos4x12 only */ +#define CLK_SMMU_ISP 362/* Exynos4x12 only */ +#define CLK_SMMU_DRC 363/* Exynos4x12 only */ +#define CLK_SMMU_FD 364/* Exynos4x12 only */ +#define CLK_SMMU_LITE0 365/* Exynos4x12 only */ +#define CLK_SMMU_LITE1 366/* Exynos4x12 only */ +#define CLK_MCUCTL_ISP 367/* Exynos4x12 only */ +#define CLK_MPWM_ISP 368/* Exynos4x12 only */ +#define CLK_I2C0_ISP 369/* Exynos4x12 only */ +#define CLK_I2C1_ISP 370/* Exynos4x12 only */ +#define CLK_MTCADC_ISP 371/* Exynos4x12 only */ +#define CLK_PWM_ISP 372/* Exynos4x12 only */ +#define CLK_WDT_ISP 373/* Exynos4x12 only */ +#define CLK_UART_ISP 374/* Exynos4x12 only */ +#define CLK_ASYNCAXIM 375/* Exynos4x12 only */ +#define CLK_SMMU_ISPCX 376/* Exynos4x12 only */ +#define CLK_SPI0_ISP 377/* Exynos4x12 only */ +#define CLK_SPI1_ISP 378/* Exynos4x12 only */ +#define CLK_PWM_ISP_SCLK 379/* Exynos4x12 only */ +#define CLK_SPI0_ISP_SCLK 380/* Exynos4x12 only */ +#define CLK_SPI1_ISP_SCLK 381/* Exynos4x12 only */ +#define CLK_UART_ISP_SCLK 382/* Exynos4x12 only */ +#define CLK_TMU_APBIF 383 + +/* mux clocks */ +#define CLK_MOUT_FIMC0 384 +#define CLK_MOUT_FIMC1 385 +#define CLK_MOUT_FIMC2 386 +#define CLK_MOUT_FIMC3 387 +#define CLK_MOUT_CAM0 388 +#define CLK_MOUT_CAM1 389 +#define CLK_MOUT_CSIS0 390 +#define CLK_MOUT_CSIS1 391 +#define CLK_MOUT_G3D0 392 +#define CLK_MOUT_G3D1 393 +#define CLK_MOUT_G3D 394 +#define CLK_ACLK400_MCUISP 395/* Exynos4x12 only */ + +/* div clocks */ +#define CLK_DIV_ISP0 450/* Exynos4x12 only */ +#define CLK_DIV_ISP1 451/* Exynos4x12 only */ +#define CLK_DIV_MCUISP0 452/* Exynos4x12 only */ +#define CLK_DIV_MCUISP1 453/* Exynos4x12 only */ +#define CLK_DIV_ACLK200 454/* Exynos4x12 only */ +#define CLK_DIV_ACLK400_MCUISP 455/* Exynos4x12 only */ + +/* must be greater than maximal clock id */ +#define CLK_NR_CLKS 456 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
Signature · 1 line
1.8.1.2
PATCH v2 2/12 ARM: dts: exynos4: convert magic numbers to macros in clock bindings
In reply to Andrzej HajdaThe patch replaces magic numbers with macros defined in DT header in exynos4 clock bindings.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- .../devicetree/bindings/clock/exynos4-clock.txt | 259 +-------------------- arch/arm/boot/dts/exynos4.dtsi | 55 ++--- arch/arm/boot/dts/exynos4210.dtsi | 6 +- arch/arm/boot/dts/exynos4412.dtsi | 2 +- arch/arm/boot/dts/exynos4x12.dtsi | 2 +- 5 files changed, 39 insertions(+), 285 deletions(-)
Documentation/devicetree/bindings/clock/exynos4-clock.txt +6 -253
@@ -15,259 +15,12 @@ Required Properties: - #clock-cells: should be 1. -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. Some of the clocks are available only on a particular -Exynos4 SoC and this is specified where applicable. - - - [Core Clocks] - - Clock ID SoC (if specific) - ----------------------------------------------- - - xxti 1 - xusbxti 2 - fin_pll 3 - fout_apll 4 - fout_mpll 5 - fout_epll 6 - fout_vpll 7 - sclk_apll 8 - sclk_mpll 9 - sclk_epll 10 - sclk_vpll 11 - arm_clk 12 - aclk200 13 - aclk100 14 - aclk160 15 - aclk133 16 - mout_mpll_user_t 17 Exynos4x12 - mout_mpll_user_c 18 Exynos4x12 - mout_core 19 - mout_apll 20 - - - [Clock Gate for Special Clocks] - - Clock ID SoC (if specific) - ----------------------------------------------- - - sclk_fimc0 128 - sclk_fimc1 129 - sclk_fimc2 130 - sclk_fimc3 131 - sclk_cam0 132 - sclk_cam1 133 - sclk_csis0 134 - sclk_csis1 135 - sclk_hdmi 136 - sclk_mixer 137 - sclk_dac 138 - sclk_pixel 139 - sclk_fimd0 140 - sclk_mdnie0 141 Exynos4412 - sclk_mdnie_pwm0 12 142 Exynos4412 - sclk_mipi0 143 - sclk_audio0 144 - sclk_mmc0 145 - sclk_mmc1 146 - sclk_mmc2 147 - sclk_mmc3 148 - sclk_mmc4 149 - sclk_sata 150 Exynos4210 - sclk_uart0 151 - sclk_uart1 152 - sclk_uart2 153 - sclk_uart3 154 - sclk_uart4 155 - sclk_audio1 156 - sclk_audio2 157 - sclk_spdif 158 - sclk_spi0 159 - sclk_spi1 160 - sclk_spi2 161 - sclk_slimbus 162 - sclk_fimd1 163 Exynos4210 - sclk_mipi1 164 Exynos4210 - sclk_pcm1 165 - sclk_pcm2 166 - sclk_i2s1 167 - sclk_i2s2 168 - sclk_mipihsi 169 Exynos4412 - sclk_mfc 170 - sclk_pcm0 171 - sclk_g3d 172 - sclk_pwm_isp 173 Exynos4x12 - sclk_spi0_isp 174 Exynos4x12 - sclk_spi1_isp 175 Exynos4x12 - sclk_uart_isp 176 Exynos4x12 - sclk_fimg2d 177 - - [Peripheral Clock Gates] - - Clock ID SoC (if specific) - ----------------------------------------------- - - fimc0 256 - fimc1 257 - fimc2 258 - fimc3 259 - csis0 260 - csis1 261 - jpeg 262 - smmu_fimc0 263 - smmu_fimc1 264 - smmu_fimc2 265 - smmu_fimc3 266 - smmu_jpeg 267 - vp 268 - mixer 269 - tvenc 270 Exynos4210 - hdmi 271 - smmu_tv 272 - mfc 273 - smmu_mfcl 274 - smmu_mfcr 275 - g3d 276 - g2d 277 - rotator 278 Exynos4210 - mdma 279 Exynos4210 - smmu_g2d 280 Exynos4210 - smmu_rotator 281 Exynos4210 - smmu_mdma 282 Exynos4210 - fimd0 283 - mie0 284 - mdnie0 285 Exynos4412 - dsim0 286 - smmu_fimd0 287 - fimd1 288 Exynos4210 - mie1 289 Exynos4210 - dsim1 290 Exynos4210 - smmu_fimd1 291 Exynos4210 - pdma0 292 - pdma1 293 - pcie_phy 294 - sata_phy 295 Exynos4210 - tsi 296 - sdmmc0 297 - sdmmc1 298 - sdmmc2 299 - sdmmc3 300 - sdmmc4 301 - sata 302 Exynos4210 - sromc 303 - usb_host 304 - usb_device 305 - pcie 306 - onenand 307 - nfcon 308 - smmu_pcie 309 - gps 310 - smmu_gps 311 - uart0 312 - uart1 313 - uart2 314 - uart3 315 - uart4 316 - i2c0 317 - i2c1 318 - i2c2 319 - i2c3 320 - i2c4 321 - i2c5 322 - i2c6 323 - i2c7 324 - i2c_hdmi 325 - tsadc 326 - spi0 327 - spi1 328 - spi2 329 - i2s1 330 - i2s2 331 - pcm0 332 - i2s0 333 - pcm1 334 - pcm2 335 - pwm 336 - slimbus 337 - spdif 338 - ac97 339 - modemif 340 - chipid 341 - sysreg 342 - hdmi_cec 343 - mct 344 - wdt 345 - rtc 346 - keyif 347 - audss 348 - mipi_hsi 349 Exynos4210 - mdma2 350 Exynos4210 - pixelasyncm0 351 - pixelasyncm1 352 - fimc_lite0 353 Exynos4x12 - fimc_lite1 354 Exynos4x12 - ppmuispx 355 Exynos4x12 - ppmuispmx 356 Exynos4x12 - fimc_isp 357 Exynos4x12 - fimc_drc 358 Exynos4x12 - fimc_fd 359 Exynos4x12 - mcuisp 360 Exynos4x12 - gicisp 361 Exynos4x12 - smmu_isp 362 Exynos4x12 - smmu_drc 363 Exynos4x12 - smmu_fd 364 Exynos4x12 - smmu_lite0 365 Exynos4x12 - smmu_lite1 366 Exynos4x12 - mcuctl_isp 367 Exynos4x12 - mpwm_isp 368 Exynos4x12 - i2c0_isp 369 Exynos4x12 - i2c1_isp 370 Exynos4x12 - mtcadc_isp 371 Exynos4x12 - pwm_isp 372 Exynos4x12 - wdt_isp 373 Exynos4x12 - uart_isp 374 Exynos4x12 - asyncaxim 375 Exynos4x12 - smmu_ispcx 376 Exynos4x12 - spi0_isp 377 Exynos4x12 - spi1_isp 378 Exynos4x12 - pwm_isp_sclk 379 Exynos4x12 - spi0_isp_sclk 380 Exynos4x12 - spi1_isp_sclk 381 Exynos4x12 - uart_isp_sclk 382 Exynos4x12 - tmu_apbif 383 - - [Mux Clocks] - - Clock ID SoC (if specific) - ----------------------------------------------- - - mout_fimc0 384 - mout_fimc1 385 - mout_fimc2 386 - mout_fimc3 387 - mout_cam0 388 - mout_cam1 389 - mout_csis0 390 - mout_csis1 391 - mout_g3d0 392 - mout_g3d1 393 - mout_g3d 394 - aclk400_mcuisp 395 Exynos4x12 - - [Div Clocks] - - Clock ID SoC (if specific) - ----------------------------------------------- - - div_isp0 450 Exynos4x12 - div_isp1 451 Exynos4x12 - div_mcuisp0 452 Exynos4x12 - div_mcuisp1 453 Exynos4x12 - div_aclk200 454 Exynos4x12 - div_aclk400_mcuisp 455 Exynos4x12 +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos4.h header and can be used in device +tree sources. Example 1: An example of a clock controller node is listed below.
@@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; interrupts = <0 54 0>; - clocks = <&clock 314>, <&clock 153>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; };
arch/arm/boot/dts/exynos4.dtsi +28 -27
223 lines not on this page · raw message
arch/arm/boot/dts/exynos4210.dtsi +3 -3
@@ -56,7 +56,7 @@ interrupt-parent = <&mct_map>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>; - clocks = <&clock 3>, <&clock 344>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; mct_map: mct-map {
@@ -112,7 +112,7 @@ interrupt-parent = <&combiner>; reg = <0x100C0000 0x100>; interrupts = <2 4>; - clocks = <&clock 383>; + clocks = <&clock CLK_TMU_APBIF>; clock-names = "tmu_apbif"; status = "disabled"; };
@@ -121,7 +121,7 @@ compatible = "samsung,s5pv210-g2d"; reg = <0x12800000 0x1000>; interrupts = <0 89 0>; - clocks = <&clock 177>, <&clock 277>; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; status = "disabled"; };
arch/arm/boot/dts/exynos4412.dtsi +1 -1
@@ -43,7 +43,7 @@ interrupt-parent = <&mct_map>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>; - clocks = <&clock 3>, <&clock 344>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; mct_map: mct-map {
arch/arm/boot/dts/exynos4x12.dtsi +1 -1
@@ -69,7 +69,7 @@ compatible = "samsung,exynos4212-g2d"; reg = <0x10800000 0x1000>; interrupts = <0 89 0>; - clocks = <&clock 177>, <&clock 277>; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; status = "disabled"; };
Signature · 1 line
1.8.1.2
PATCH v2 3/12 clk: exynos4: replace clock ID private enums with IDs from DT header
In reply to Andrzej HajdaThe patch replaces private enum clock IDs in the driver with macros provided by the DT header.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- drivers/clk/samsung/clk-exynos4.c | 857 ++++++++++++++++++-------------------- 1 file changed, 406 insertions(+), 451 deletions(-)
drivers/clk/samsung/clk-exynos4.c +406 -451
@@ -10,6 +10,7 @@* Common Clock Framework support for all Exynos4 SoCs. */ +#include <dt-bindings/clock/exynos4.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h>
@@ -129,68 +130,6 @@ enum exynos4_plls { };/* -* Let each supported clock get a unique id. This id is used to lookup the clock -* for device tree based platforms. The clocks are categorized into three -* sections: core, sclk gate and bus interface gate clocks. -* -* When adding a new clock to this list, it is advised to choose a clock -* category and add it to the end of that category. That is because the the -* device tree source file is referring to these ids and any change in the -* sequence number of existing clocks will require corresponding change in the -* device tree files. This limitation would go away when pre-processor support -* for dtc would be available. -*/ -enum exynos4_clks { - none, - -/* core clocks */ - xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll, - sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100, - aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core, - mout_apll,/* 20 */ - -/* gate for special clocks (sclk) */ - sclk_fimc0 =128 , sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0, - sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac, - sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0, - sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4, - sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4, - sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, - sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, - sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, - sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d, - -/* gate clocks */ - fimc0 =256 , fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, - smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi, - smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d, - smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1, - mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0, - sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie, - onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3, - uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, - spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus, - spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif, - audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0, - fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp, - gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp, - mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp, - asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk, - spi1_isp_sclk, uart_isp_sclk, tmu_apbif, - -/* mux clocks */ - mout_fimc0 =384 , mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, - mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d, - aclk400_mcuisp, - -/* div clocks */ - div_isp0 =450 , div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200, - div_aclk400_mcuisp, - - nr_clks, -}; - -/* * list of controller registers to be saved and restored during a * suspend/resume cycle. */
@@ -346,254 +285,258 @@ PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[]__initdata = { -FRATE (xxti,"xxti" ,NULL ,CLK_IS_ROOT ,0 ), -FRATE (xusbxti,"xusbxti" ,NULL ,CLK_IS_ROOT ,0 ), +FRATE (CLK_XXTI ,"xxti" ,NULL ,CLK_IS_ROOT ,0 ), +FRATE (CLK_XUSBXTI ,"xusbxti" ,NULL ,CLK_IS_ROOT ,0 ), };/* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[]__initdata = { -FRATE (none,"sclk_hdmi24m" ,NULL ,CLK_IS_ROOT ,24000000 ), -FRATE (none,"sclk_hdmiphy" ,NULL ,CLK_IS_ROOT ,27000000 ), -FRATE (none,"sclk_usbphy0" ,NULL ,CLK_IS_ROOT ,48000000 ), +FRATE (0 ,"sclk_hdmi24m" ,NULL ,CLK_IS_ROOT ,24000000 ), +FRATE (0 ,"sclk_hdmiphy" ,NULL ,CLK_IS_ROOT ,27000000 ), +FRATE (0 ,"sclk_usbphy0" ,NULL ,CLK_IS_ROOT ,48000000 ), };static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[]__initdata = { -FRATE (none,"sclk_usbphy1" ,NULL ,CLK_IS_ROOT ,48000000 ), +FRATE (0 ,"sclk_usbphy1" ,NULL ,CLK_IS_ROOT ,48000000 ), };/* list of mux clocks supported in all exynos4 soc's */ static struct samsung_mux_clock exynos4_mux_clks[]__initdata = { -MUX_FA (mout_apll,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 , +MUX_FA (CLK_MOUT_APLL ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 ,CLK_SET_RATE_PARENT ,0 ,"mout_apll" ), -MUX (none,"mout_hdmi" , mout_hdmi_p,SRC_TV ,0 ,1 ), -MUX (none,"mout_mfc1" , sclk_evpll_p,SRC_MFC ,4 ,1 ), -MUX (none,"mout_mfc" , mout_mfc_p,SRC_MFC ,8 ,1 ), -MUX_F (mout_g3d1,"mout_g3d1" , sclk_evpll_p,SRC_G3D ,4 ,1 , +MUX (0 ,"mout_hdmi" , mout_hdmi_p,SRC_TV ,0 ,1 ), +MUX (0 ,"mout_mfc1" , sclk_evpll_p,SRC_MFC ,4 ,1 ), +MUX (0 ,"mout_mfc" , mout_mfc_p,SRC_MFC ,8 ,1 ), +MUX_F (CLK_MOUT_G3D1 ,"mout_g3d1" , sclk_evpll_p,SRC_G3D ,4 ,1 ,CLK_SET_RATE_PARENT ,0 ), -MUX_F (mout_g3d,"mout_g3d" , mout_g3d_p,SRC_G3D ,8 ,1 , +MUX_F (CLK_MOUT_G3D ,"mout_g3d" , mout_g3d_p,SRC_G3D ,8 ,1 ,CLK_SET_RATE_PARENT ,0 ), -MUX (none,"mout_spdif" , mout_spdif_p,SRC_PERIL1 ,8 ,2 ), -MUX (none,"mout_onenand1" , mout_onenand1_p,SRC_TOP0 ,0 ,1 ), -MUX_A (sclk_epll,"sclk_epll" , mout_epll_p,SRC_TOP0 ,4 ,1 ,"sclk_epll" ), -MUX (none,"mout_onenand" , mout_onenand_p,SRC_TOP0 ,28 ,1 ), +MUX (0 ,"mout_spdif" , mout_spdif_p,SRC_PERIL1 ,8 ,2 ), +MUX (0 ,"mout_onenand1" , mout_onenand1_p,SRC_TOP0 ,0 ,1 ), +MUX_A (CLK_SCLK_EPLL ,"sclk_epll" , mout_epll_p,SRC_TOP0 ,4 ,1 , +"sclk_epll" ), +MUX (0 ,"mout_onenand" , mout_onenand_p,SRC_TOP0 ,28 ,1 ), };/* list of mux clocks supported in exynos4210 soc */ static struct samsung_mux_clock exynos4210_mux_clks[]__initdata = { -MUX (none,"mout_aclk200" , sclk_ampll_p4210,SRC_TOP0 ,12 ,1 ), -MUX (none,"mout_aclk100" , sclk_ampll_p4210,SRC_TOP0 ,16 ,1 ), -MUX (none,"mout_aclk160" , sclk_ampll_p4210,SRC_TOP0 ,20 ,1 ), -MUX (none,"mout_aclk133" , sclk_ampll_p4210,SRC_TOP0 ,24 ,1 ), -MUX (none,"mout_vpllsrc" , mout_vpllsrc_p,SRC_TOP1 ,0 ,1 ), -MUX (none,"mout_mixer" , mout_mixer_p4210,SRC_TV ,4 ,1 ), -MUX (none,"mout_dac" , mout_dac_p4210,SRC_TV ,8 ,1 ), -MUX (none,"mout_g2d0" , sclk_ampll_p4210,E4210_SRC_IMAGE ,0 ,1 ), -MUX (none,"mout_g2d1" , sclk_evpll_p,E4210_SRC_IMAGE ,4 ,1 ), -MUX (none,"mout_g2d" , mout_g2d_p,E4210_SRC_IMAGE ,8 ,1 ), -MUX (none,"mout_fimd1" , group1_p4210,E4210_SRC_LCD1 ,0 ,4 ), -MUX (none,"mout_mipi1" , group1_p4210,E4210_SRC_LCD1 ,12 ,4 ), -MUX_A (sclk_mpll,"sclk_mpll" , mout_mpll_p,SRC_CPU ,8 ,1 ,"mout_mpll" ), -MUX_A (mout_core,"mout_core" , mout_core_p4210, +MUX (0 ,"mout_aclk200" , sclk_ampll_p4210,SRC_TOP0 ,12 ,1 ), +MUX (0 ,"mout_aclk100" , sclk_ampll_p4210,SRC_TOP0 ,16 ,1 ), +MUX (0 ,"mout_aclk160" , sclk_ampll_p4210,SRC_TOP0 ,20 ,1 ), +MUX (0 ,"mout_aclk133" , sclk_ampll_p4210,SRC_TOP0 ,24 ,1 ), +MUX (0 ,"mout_vpllsrc" , mout_vpllsrc_p,SRC_TOP1 ,0 ,1 ), +MUX (0 ,"mout_mixer" , mout_mixer_p4210,SRC_TV ,4 ,1 ), +MUX (0 ,"mout_dac" , mout_dac_p4210,SRC_TV ,8 ,1 ), +MUX (0 ,"mout_g2d0" , sclk_ampll_p4210,E4210_SRC_IMAGE ,0 ,1 ), +MUX (0 ,"mout_g2d1" , sclk_evpll_p,E4210_SRC_IMAGE ,4 ,1 ), +MUX (0 ,"mout_g2d" , mout_g2d_p,E4210_SRC_IMAGE ,8 ,1 ), +MUX (0 ,"mout_fimd1" , group1_p4210,E4210_SRC_LCD1 ,0 ,4 ), +MUX (0 ,"mout_mipi1" , group1_p4210,E4210_SRC_LCD1 ,12 ,4 ), +MUX_A (CLK_SCLK_MPLL ,"sclk_mpll" , mout_mpll_p,SRC_CPU ,8 ,1 , +"mout_mpll" ), +MUX_A (CLK_MOUT_CORE ,"mout_core" , mout_core_p4210,SRC_CPU ,16 ,1 ,"moutcore" ), -MUX_A (sclk_vpll,"sclk_vpll" , sclk_vpll_p4210, +MUX_A (CLK_SCLK_VPLL ,"sclk_vpll" , sclk_vpll_p4210,SRC_TOP0 ,8 ,1 ,"sclk_vpll" ), -MUX (mout_fimc0,"mout_fimc0" , group1_p4210,SRC_CAM ,0 ,4 ), -MUX (mout_fimc1,"mout_fimc1" , group1_p4210,SRC_CAM ,4 ,4 ), -MUX (mout_fimc2,"mout_fimc2" , group1_p4210,SRC_CAM ,8 ,4 ), -MUX (mout_fimc3,"mout_fimc3" , group1_p4210,SRC_CAM ,12 ,4 ), -MUX (mout_cam0,"mout_cam0" , group1_p4210,SRC_CAM ,16 ,4 ), -MUX (mout_cam1,"mout_cam1" , group1_p4210,SRC_CAM ,20 ,4 ), -MUX (mout_csis0,"mout_csis0" , group1_p4210,SRC_CAM ,24 ,4 ), -MUX (mout_csis1,"mout_csis1" , group1_p4210,SRC_CAM ,28 ,4 ), -MUX (none,"mout_mfc0" , sclk_ampll_p4210,SRC_MFC ,0 ,1 ), -MUX_F (mout_g3d0,"mout_g3d0" , sclk_ampll_p4210,SRC_G3D ,0 ,1 , +MUX (CLK_MOUT_FIMC0 ,"mout_fimc0" , group1_p4210,SRC_CAM ,0 ,4 ), +MUX (CLK_MOUT_FIMC1 ,"mout_fimc1" , group1_p4210,SRC_CAM ,4 ,4 ), +MUX (CLK_MOUT_FIMC2 ,"mout_fimc2" , group1_p4210,SRC_CAM ,8 ,4 ), +MUX (CLK_MOUT_FIMC3 ,"mout_fimc3" , group1_p4210,SRC_CAM ,12 ,4 ), +MUX (CLK_MOUT_CAM0 ,"mout_cam0" , group1_p4210,SRC_CAM ,16 ,4 ), +MUX (CLK_MOUT_CAM1 ,"mout_cam1" , group1_p4210,SRC_CAM ,20 ,4 ), +MUX (CLK_MOUT_CSIS0 ,"mout_csis0" , group1_p4210,SRC_CAM ,24 ,4 ), +MUX (CLK_MOUT_CSIS1 ,"mout_csis1" , group1_p4210,SRC_CAM ,28 ,4 ), +MUX (0 ,"mout_mfc0" , sclk_ampll_p4210,SRC_MFC ,0 ,1 ), +MUX_F (CLK_MOUT_G3D0 ,"mout_g3d0" , sclk_ampll_p4210,SRC_G3D ,0 ,1 ,CLK_SET_RATE_PARENT ,0 ), -MUX (none,"mout_fimd0" , group1_p4210,SRC_LCD0 ,0 ,4 ), -MUX (none,"mout_mipi0" , group1_p4210,SRC_LCD0 ,12 ,4 ), -MUX (none,"mout_audio0" , mout_audio0_p4210,SRC_MAUDIO ,0 ,4 ), -MUX (none,"mout_mmc0" , group1_p4210,SRC_FSYS ,0 ,4 ), -MUX (none,"mout_mmc1" , group1_p4210,SRC_FSYS ,4 ,4 ), -MUX (none,"mout_mmc2" , group1_p4210,SRC_FSYS ,8 ,4 ), -MUX (none,"mout_mmc3" , group1_p4210,SRC_FSYS ,12 ,4 ), -MUX (none,"mout_mmc4" , group1_p4210,SRC_FSYS ,16 ,4 ), -MUX (none,"mout_sata" , sclk_ampll_p4210,SRC_FSYS ,24 ,1 ), -MUX (none,"mout_uart0" , group1_p4210,SRC_PERIL0 ,0 ,4 ), -MUX (none,"mout_uart1" , group1_p4210,SRC_PERIL0 ,4 ,4 ), -MUX (none,"mout_uart2" , group1_p4210,SRC_PERIL0 ,8 ,4 ), -MUX (none,"mout_uart3" , group1_p4210,SRC_PERIL0 ,12 ,4 ), -MUX (none,"mout_uart4" , group1_p4210,SRC_PERIL0 ,16 ,4 ), -MUX (none,"mout_audio1" , mout_audio1_p4210,SRC_PERIL1 ,0 ,4 ), -MUX (none,"mout_audio2" , mout_audio2_p4210,SRC_PERIL1 ,4 ,4 ), -MUX (none,"mout_spi0" , group1_p4210,SRC_PERIL1 ,16 ,4 ), -MUX (none,"mout_spi1" , group1_p4210,SRC_PERIL1 ,20 ,4 ), -MUX (none,"mout_spi2" , group1_p4210,SRC_PERIL1 ,24 ,4 ), +MUX (0 ,"mout_fimd0" , group1_p4210,SRC_LCD0 ,0 ,4 ), +MUX (0 ,"mout_mipi0" , group1_p4210,SRC_LCD0 ,12 ,4 ), +MUX (0 ,"mout_audio0" , mout_audio0_p4210,SRC_MAUDIO ,0 ,4 ), +MUX (0 ,"mout_mmc0" , group1_p4210,SRC_FSYS ,0 ,4 ), +MUX (0 ,"mout_mmc1" , group1_p4210,SRC_FSYS ,4 ,4 ), +MUX (0 ,"mout_mmc2" , group1_p4210,SRC_FSYS ,8 ,4 ), +MUX (0 ,"mout_mmc3" , group1_p4210,SRC_FSYS ,12 ,4 ), +MUX (0 ,"mout_mmc4" , group1_p4210,SRC_FSYS ,16 ,4 ), +MUX (0 ,"mout_sata" , sclk_ampll_p4210,SRC_FSYS ,24 ,1 ), +MUX (0 ,"mout_uart0" , group1_p4210,SRC_PERIL0 ,0 ,4 ), +MUX (0 ,"mout_uart1" , group1_p4210,SRC_PERIL0 ,4 ,4 ), +MUX (0 ,"mout_uart2" , group1_p4210,SRC_PERIL0 ,8 ,4 ), +MUX (0 ,"mout_uart3" , group1_p4210,SRC_PERIL0 ,12 ,4 ), +MUX (0 ,"mout_uart4" , group1_p4210,SRC_PERIL0 ,16 ,4 ), +MUX (0 ,"mout_audio1" , mout_audio1_p4210,SRC_PERIL1 ,0 ,4 ), +MUX (0 ,"mout_audio2" , mout_audio2_p4210,SRC_PERIL1 ,4 ,4 ), +MUX (0 ,"mout_spi0" , group1_p4210,SRC_PERIL1 ,16 ,4 ), +MUX (0 ,"mout_spi1" , group1_p4210,SRC_PERIL1 ,20 ,4 ), +MUX (0 ,"mout_spi2" , group1_p4210,SRC_PERIL1 ,24 ,4 ), };/* list of mux clocks supported in exynos4x12 soc */ static struct samsung_mux_clock exynos4x12_mux_clks[]__initdata = { -MUX_A (mout_mpll_user_c,"mout_mpll_user_c" , mout_mpll_user_p4x12, +MUX_A (CLK_MOUT_MPLL_USER_C ,"mout_mpll_user_c" , mout_mpll_user_p4x12,SRC_CPU ,24 ,1 ,"mout_mpll" ), -MUX (none,"mout_aclk266_gps" , aclk_p4412,SRC_TOP1 ,4 ,1 ), -MUX (none,"mout_aclk400_mcuisp" , aclk_p4412,SRC_TOP1 ,8 ,1 ), -MUX (mout_mpll_user_t,"mout_mpll_user_t" , mout_mpll_user_p4x12, +MUX (0 ,"mout_aclk266_gps" , aclk_p4412,SRC_TOP1 ,4 ,1 ), +MUX (0 ,"mout_aclk400_mcuisp" , aclk_p4412,SRC_TOP1 ,8 ,1 ), +MUX (CLK_MOUT_MPLL_USER_T ,"mout_mpll_user_t" , mout_mpll_user_p4x12,SRC_TOP1 ,12 ,1 ), -MUX (none,"mout_user_aclk266_gps" , mout_user_aclk266_gps_p4x12, +MUX (0 ,"mout_user_aclk266_gps" , mout_user_aclk266_gps_p4x12,SRC_TOP1 ,16 ,1 ), -MUX (aclk200,"aclk200" , mout_user_aclk200_p4x12,SRC_TOP1 ,20 ,1 ), -MUX (aclk400_mcuisp,"aclk400_mcuisp" , mout_user_aclk400_mcuisp_p4x12, -SRC_TOP1 ,24 ,1 ), -MUX (none,"mout_aclk200" , aclk_p4412,SRC_TOP0 ,12 ,1 ), -MUX (none,"mout_aclk100" , aclk_p4412,SRC_TOP0 ,16 ,1 ), -MUX (none,"mout_aclk160" , aclk_p4412,SRC_TOP0 ,20 ,1 ), -MUX (none,"mout_aclk133" , aclk_p4412,SRC_TOP0 ,24 ,1 ), -MUX (none,"mout_mdnie0" , group1_p4x12,SRC_LCD0 ,4 ,4 ), -MUX (none,"mout_mdnie_pwm0" , group1_p4x12,SRC_LCD0 ,8 ,4 ), -MUX (none,"mout_sata" , sclk_ampll_p4x12,SRC_FSYS ,24 ,1 ), -MUX (none,"mout_jpeg0" , sclk_ampll_p4x12,E4X12_SRC_CAM1 ,0 ,1 ), -MUX (none,"mout_jpeg1" , sclk_evpll_p,E4X12_SRC_CAM1 ,4 ,1 ), -MUX (none,"mout_jpeg" , mout_jpeg_p,E4X12_SRC_CAM1 ,8 ,1 ), -MUX_A (sclk_mpll,"sclk_mpll" , mout_mpll_p, +MUX (CLK_ACLK200 ,"aclk200" , mout_user_aclk200_p4x12,SRC_TOP1 ,20 ,1 ), +MUX (CLK_ACLK400_MCUISP ,"aclk400_mcuisp" , + mout_user_aclk400_mcuisp_p4x12,SRC_TOP1 ,24 ,1 ), +MUX (0 ,"mout_aclk200" , aclk_p4412,SRC_TOP0 ,12 ,1 ), +MUX (0 ,"mout_aclk100" , aclk_p4412,SRC_TOP0 ,16 ,1 ), +MUX (0 ,"mout_aclk160" , aclk_p4412,SRC_TOP0 ,20 ,1 ), +MUX (0 ,"mout_aclk133" , aclk_p4412,SRC_TOP0 ,24 ,1 ), +MUX (0 ,"mout_mdnie0" , group1_p4x12,SRC_LCD0 ,4 ,4 ), +MUX (0 ,"mout_mdnie_pwm0" , group1_p4x12,SRC_LCD0 ,8 ,4 ), +MUX (0 ,"mout_sata" , sclk_ampll_p4x12,SRC_FSYS ,24 ,1 ), +MUX (0 ,"mout_jpeg0" , sclk_ampll_p4x12,E4X12_SRC_CAM1 ,0 ,1 ), +MUX (0 ,"mout_jpeg1" , sclk_evpll_p,E4X12_SRC_CAM1 ,4 ,1 ), +MUX (0 ,"mout_jpeg" , mout_jpeg_p,E4X12_SRC_CAM1 ,8 ,1 ), +MUX_A (CLK_SCLK_MPLL ,"sclk_mpll" , mout_mpll_p,SRC_DMC ,12 ,1 ,"sclk_mpll" ), -MUX_A (sclk_vpll,"sclk_vpll" , mout_vpll_p, +MUX_A (CLK_SCLK_VPLL ,"sclk_vpll" , mout_vpll_p,SRC_TOP0 ,8 ,1 ,"sclk_vpll" ), -MUX_A (mout_core,"mout_core" , mout_core_p4x12, +MUX_A (CLK_MOUT_CORE ,"mout_core" , mout_core_p4x12,SRC_CPU ,16 ,1 ,"moutcore" ), -MUX (mout_fimc0,"mout_fimc0" , group1_p4x12,SRC_CAM ,0 ,4 ), -MUX (mout_fimc1,"mout_fimc1" , group1_p4x12,SRC_CAM ,4 ,4 ), -MUX (mout_fimc2,"mout_fimc2" , group1_p4x12,SRC_CAM ,8 ,4 ), -MUX (mout_fimc3,"mout_fimc3" , group1_p4x12,SRC_CAM ,12 ,4 ), -MUX (mout_cam0,"mout_cam0" , group1_p4x12,SRC_CAM ,16 ,4 ), -MUX (mout_cam1,"mout_cam1" , group1_p4x12,SRC_CAM ,20 ,4 ), -MUX (mout_csis0,"mout_csis0" , group1_p4x12,SRC_CAM ,24 ,4 ), -MUX (mout_csis1,"mout_csis1" , group1_p4x12,SRC_CAM ,28 ,4 ), -MUX (none,"mout_mfc0" , sclk_ampll_p4x12,SRC_MFC ,0 ,1 ), -MUX_F (mout_g3d0,"mout_g3d0" , sclk_ampll_p4x12,SRC_G3D ,0 ,1 , +MUX (CLK_MOUT_FIMC0 ,"mout_fimc0" , group1_p4x12,SRC_CAM ,0 ,4 ), +MUX (CLK_MOUT_FIMC1 ,"mout_fimc1" , group1_p4x12,SRC_CAM ,4 ,4 ), +MUX (CLK_MOUT_FIMC2 ,"mout_fimc2" , group1_p4x12,SRC_CAM ,8 ,4 ), +MUX (CLK_MOUT_FIMC3 ,"mout_fimc3" , group1_p4x12,SRC_CAM ,12 ,4 ), +MUX (CLK_MOUT_CAM0 ,"mout_cam0" , group1_p4x12,SRC_CAM ,16 ,4 ), +MUX (CLK_MOUT_CAM1 ,"mout_cam1" , group1_p4x12,SRC_CAM ,20 ,4 ), +MUX (CLK_MOUT_CSIS0 ,"mout_csis0" , group1_p4x12,SRC_CAM ,24 ,4 ), +MUX (CLK_MOUT_CSIS1 ,"mout_csis1" , group1_p4x12,SRC_CAM ,28 ,4 ), +MUX (0 ,"mout_mfc0" , sclk_ampll_p4x12,SRC_MFC ,0 ,1 ), +MUX_F (CLK_MOUT_G3D0 ,"mout_g3d0" , sclk_ampll_p4x12,SRC_G3D ,0 ,1 ,CLK_SET_RATE_PARENT ,0 ), -MUX (none,"mout_fimd0" , group1_p4x12,SRC_LCD0 ,0 ,4 ), -MUX (none,"mout_mipi0" , group1_p4x12,SRC_LCD0 ,12 ,4 ), -MUX (none,"mout_audio0" , mout_audio0_p4x12,SRC_MAUDIO ,0 ,4 ), -MUX (none,"mout_mmc0" , group1_p4x12,SRC_FSYS ,0 ,4 ), -MUX (none,"mout_mmc1" , group1_p4x12,SRC_FSYS ,4 ,4 ), -MUX (none,"mout_mmc2" , group1_p4x12,SRC_FSYS ,8 ,4 ), -MUX (none,"mout_mmc3" , group1_p4x12,SRC_FSYS ,12 ,4 ), -MUX (none,"mout_mmc4" , group1_p4x12,SRC_FSYS ,16 ,4 ), -MUX (none,"mout_mipihsi" , aclk_p4412,SRC_FSYS ,24 ,1 ), -MUX (none,"mout_uart0" , group1_p4x12,SRC_PERIL0 ,0 ,4 ), -MUX (none,"mout_uart1" , group1_p4x12,SRC_PERIL0 ,4 ,4 ), -MUX (none,"mout_uart2" , group1_p4x12,SRC_PERIL0 ,8 ,4 ), -MUX (none,"mout_uart3" , group1_p4x12,SRC_PERIL0 ,12 ,4 ), -MUX (none,"mout_uart4" , group1_p4x12,SRC_PERIL0 ,16 ,4 ), -MUX (none,"mout_audio1" , mout_audio1_p4x12,SRC_PERIL1 ,0 ,4 ), -MUX (none,"mout_audio2" , mout_audio2_p4x12,SRC_PERIL1 ,4 ,4 ), -MUX (none,"mout_spi0" , group1_p4x12,SRC_PERIL1 ,16 ,4 ), -MUX (none,"mout_spi1" , group1_p4x12,SRC_PERIL1 ,20 ,4 ), -MUX (none,"mout_spi2" , group1_p4x12,SRC_PERIL1 ,24 ,4 ), -MUX (none,"mout_pwm_isp" , group1_p4x12,E4X12_SRC_ISP ,0 ,4 ), -MUX (none,"mout_spi0_isp" , group1_p4x12,E4X12_SRC_ISP ,4 ,4 ), -MUX (none,"mout_spi1_isp" , group1_p4x12,E4X12_SRC_ISP ,8 ,4 ), -MUX (none,"mout_uart_isp" , group1_p4x12,E4X12_SRC_ISP ,12 ,4 ), -MUX (none,"mout_g2d0" , sclk_ampll_p4210,SRC_DMC ,20 ,1 ), -MUX (none,"mout_g2d1" , sclk_evpll_p,SRC_DMC ,24 ,1 ), -MUX (none,"mout_g2d" , mout_g2d_p,SRC_DMC ,28 ,1 ), +MUX (0 ,"mout_fimd0" , group1_p4x12,SRC_LCD0 ,0 ,4 ), +MUX (0 ,"mout_mipi0" , group1_p4x12,SRC_LCD0 ,12 ,4 ), +MUX (0 ,"mout_audio0" , mout_audio0_p4x12,SRC_MAUDIO ,0 ,4 ), +MUX (0 ,"mout_mmc0" , group1_p4x12,SRC_FSYS ,0 ,4 ), +MUX (0 ,"mout_mmc1" , group1_p4x12,SRC_FSYS ,4 ,4 ), +MUX (0 ,"mout_mmc2" , group1_p4x12,SRC_FSYS ,8 ,4 ), +MUX (0 ,"mout_mmc3" , group1_p4x12,SRC_FSYS ,12 ,4 ), +MUX (0 ,"mout_mmc4" , group1_p4x12,SRC_FSYS ,16 ,4 ), +MUX (0 ,"mout_mipihsi" , aclk_p4412,SRC_FSYS ,24 ,1 ), +MUX (0 ,"mout_uart0" , group1_p4x12,SRC_PERIL0 ,0 ,4 ), +MUX (0 ,"mout_uart1" , group1_p4x12,SRC_PERIL0 ,4 ,4 ), +MUX (0 ,"mout_uart2" , group1_p4x12,SRC_PERIL0 ,8 ,4 ), +MUX (0 ,"mout_uart3" , group1_p4x12,SRC_PERIL0 ,12 ,4 ), +MUX (0 ,"mout_uart4" , group1_p4x12,SRC_PERIL0 ,16 ,4 ), +MUX (0 ,"mout_audio1" , mout_audio1_p4x12,SRC_PERIL1 ,0 ,4 ), +MUX (0 ,"mout_audio2" , mout_audio2_p4x12,SRC_PERIL1 ,4 ,4 ), +MUX (0 ,"mout_spi0" , group1_p4x12,SRC_PERIL1 ,16 ,4 ), +MUX (0 ,"mout_spi1" , group1_p4x12,SRC_PERIL1 ,20 ,4 ), +MUX (0 ,"mout_spi2" , group1_p4x12,SRC_PERIL1 ,24 ,4 ), +MUX (0 ,"mout_pwm_isp" , group1_p4x12,E4X12_SRC_ISP ,0 ,4 ), +MUX (0 ,"mout_spi0_isp" , group1_p4x12,E4X12_SRC_ISP ,4 ,4 ), +MUX (0 ,"mout_spi1_isp" , group1_p4x12,E4X12_SRC_ISP ,8 ,4 ), +MUX (0 ,"mout_uart_isp" , group1_p4x12,E4X12_SRC_ISP ,12 ,4 ), +MUX (0 ,"mout_g2d0" , sclk_ampll_p4210,SRC_DMC ,20 ,1 ), +MUX (0 ,"mout_g2d1" , sclk_evpll_p,SRC_DMC ,24 ,1 ), +MUX (0 ,"mout_g2d" , mout_g2d_p,SRC_DMC ,28 ,1 ), };/* list of divider clocks supported in all exynos4 soc's */ static struct samsung_div_clock exynos4_div_clks[]__initdata = { -DIV (none,"div_core" ,"mout_core" ,DIV_CPU0 ,0 ,3 ), -DIV (none,"div_core2" ,"div_core" ,DIV_CPU0 ,28 ,3 ), -DIV (none,"div_fimc0" ,"mout_fimc0" ,DIV_CAM ,0 ,4 ), -DIV (none,"div_fimc1" ,"mout_fimc1" ,DIV_CAM ,4 ,4 ), -DIV (none,"div_fimc2" ,"mout_fimc2" ,DIV_CAM ,8 ,4 ), -DIV (none,"div_fimc3" ,"mout_fimc3" ,DIV_CAM ,12 ,4 ), -DIV (none,"div_cam0" ,"mout_cam0" ,DIV_CAM ,16 ,4 ), -DIV (none,"div_cam1" ,"mout_cam1" ,DIV_CAM ,20 ,4 ), -DIV (none,"div_csis0" ,"mout_csis0" ,DIV_CAM ,24 ,4 ), -DIV (none,"div_csis1" ,"mout_csis1" ,DIV_CAM ,28 ,4 ), -DIV (sclk_mfc,"sclk_mfc" ,"mout_mfc" ,DIV_MFC ,0 ,4 ), -DIV_F (none,"div_g3d" ,"mout_g3d" ,DIV_G3D ,0 ,4 , +DIV (0 ,"div_core" ,"mout_core" ,DIV_CPU0 ,0 ,3 ), +DIV (0 ,"div_core2" ,"div_core" ,DIV_CPU0 ,28 ,3 ), +DIV (0 ,"div_fimc0" ,"mout_fimc0" ,DIV_CAM ,0 ,4 ), +DIV (0 ,"div_fimc1" ,"mout_fimc1" ,DIV_CAM ,4 ,4 ), +DIV (0 ,"div_fimc2" ,"mout_fimc2" ,DIV_CAM ,8 ,4 ), +DIV (0 ,"div_fimc3" ,"mout_fimc3" ,DIV_CAM ,12 ,4 ), +DIV (0 ,"div_cam0" ,"mout_cam0" ,DIV_CAM ,16 ,4 ), +DIV (0 ,"div_cam1" ,"mout_cam1" ,DIV_CAM ,20 ,4 ), +DIV (0 ,"div_csis0" ,"mout_csis0" ,DIV_CAM ,24 ,4 ), +DIV (0 ,"div_csis1" ,"mout_csis1" ,DIV_CAM ,28 ,4 ), +DIV (CLK_SCLK_MFC ,"sclk_mfc" ,"mout_mfc" ,DIV_MFC ,0 ,4 ), +DIV_F (0 ,"div_g3d" ,"mout_g3d" ,DIV_G3D ,0 ,4 ,CLK_SET_RATE_PARENT ,0 ), -DIV (none,"div_fimd0" ,"mout_fimd0" ,DIV_LCD0 ,0 ,4 ), -DIV (none,"div_mipi0" ,"mout_mipi0" ,DIV_LCD0 ,16 ,4 ), -DIV (none,"div_audio0" ,"mout_audio0" ,DIV_MAUDIO ,0 ,4 ), -DIV (sclk_pcm0,"sclk_pcm0" ,"sclk_audio0" ,DIV_MAUDIO ,4 ,8 ), -DIV (none,"div_mmc0" ,"mout_mmc0" ,DIV_FSYS1 ,0 ,4 ), -DIV (none,"div_mmc1" ,"mout_mmc1" ,DIV_FSYS1 ,16 ,4 ), -DIV (none,"div_mmc2" ,"mout_mmc2" ,DIV_FSYS2 ,0 ,4 ), -DIV (none,"div_mmc3" ,"mout_mmc3" ,DIV_FSYS2 ,16 ,4 ), -DIV (sclk_pixel,"sclk_pixel" ,"sclk_vpll" ,DIV_TV ,0 ,4 ), -DIV (aclk100,"aclk100" ,"mout_aclk100" ,DIV_TOP ,4 ,4 ), -DIV (aclk160,"aclk160" ,"mout_aclk160" ,DIV_TOP ,8 ,3 ), -DIV (aclk133,"aclk133" ,"mout_aclk133" ,DIV_TOP ,12 ,3 ), -DIV (none,"div_onenand" ,"mout_onenand1" ,DIV_TOP ,16 ,3 ), -DIV (sclk_slimbus,"sclk_slimbus" ,"sclk_epll" ,DIV_PERIL3 ,4 ,4 ), -DIV (sclk_pcm1,"sclk_pcm1" ,"sclk_audio1" ,DIV_PERIL4 ,4 ,8 ), -DIV (sclk_pcm2,"sclk_pcm2" ,"sclk_audio2" ,DIV_PERIL4 ,20 ,8 ), -DIV (sclk_i2s1,"sclk_i2s1" ,"sclk_audio1" ,DIV_PERIL5 ,0 ,6 ), -DIV (sclk_i2s2,"sclk_i2s2" ,"sclk_audio2" ,DIV_PERIL5 ,8 ,6 ), -DIV (none,"div_mmc4" ,"mout_mmc4" ,DIV_FSYS3 ,0 ,4 ), -DIV (none,"div_mmc_pre4" ,"div_mmc4" ,DIV_FSYS3 ,8 ,8 ), -DIV (none,"div_uart0" ,"mout_uart0" ,DIV_PERIL0 ,0 ,4 ), -DIV (none,"div_uart1" ,"mout_uart1" ,DIV_PERIL0 ,4 ,4 ), -DIV (none,"div_uart2" ,"mout_uart2" ,DIV_PERIL0 ,8 ,4 ), -DIV (none,"div_uart3" ,"mout_uart3" ,DIV_PERIL0 ,12 ,4 ), -DIV (none,"div_uart4" ,"mout_uart4" ,DIV_PERIL0 ,16 ,4 ), -DIV (none,"div_spi0" ,"mout_spi0" ,DIV_PERIL1 ,0 ,4 ), -DIV (none,"div_spi_pre0" ,"div_spi0" ,DIV_PERIL1 ,8 ,8 ), -DIV (none,"div_spi1" ,"mout_spi1" ,DIV_PERIL1 ,16 ,4 ), -DIV (none,"div_spi_pre1" ,"div_spi1" ,DIV_PERIL1 ,24 ,8 ), -DIV (none,"div_spi2" ,"mout_spi2" ,DIV_PERIL2 ,0 ,4 ), -DIV (none,"div_spi_pre2" ,"div_spi2" ,DIV_PERIL2 ,8 ,8 ), -DIV (none,"div_audio1" ,"mout_audio1" ,DIV_PERIL4 ,0 ,4 ), -DIV (none,"div_audio2" ,"mout_audio2" ,DIV_PERIL4 ,16 ,4 ), -DIV_A (arm_clk,"arm_clk" ,"div_core2" ,DIV_CPU0 ,28 ,3 ,"armclk" ), -DIV_A (sclk_apll,"sclk_apll" ,"mout_apll" , +DIV (0 ,"div_fimd0" ,"mout_fimd0" ,DIV_LCD0 ,0 ,4 ), +DIV (0 ,"div_mipi0" ,"mout_mipi0" ,DIV_LCD0 ,16 ,4 ), +DIV (0 ,"div_audio0" ,"mout_audio0" ,DIV_MAUDIO ,0 ,4 ), +DIV (CLK_SCLK_PCM0 ,"sclk_pcm0" ,"sclk_audio0" ,DIV_MAUDIO ,4 ,8 ), +DIV (0 ,"div_mmc0" ,"mout_mmc0" ,DIV_FSYS1 ,0 ,4 ), +DIV (0 ,"div_mmc1" ,"mout_mmc1" ,DIV_FSYS1 ,16 ,4 ), +DIV (0 ,"div_mmc2" ,"mout_mmc2" ,DIV_FSYS2 ,0 ,4 ), +DIV (0 ,"div_mmc3" ,"mout_mmc3" ,DIV_FSYS2 ,16 ,4 ), +DIV (CLK_SCLK_PIXEL ,"sclk_pixel" ,"sclk_vpll" ,DIV_TV ,0 ,4 ), +DIV (CLK_ACLK100 ,"aclk100" ,"mout_aclk100" ,DIV_TOP ,4 ,4 ), +DIV (CLK_ACLK160 ,"aclk160" ,"mout_aclk160" ,DIV_TOP ,8 ,3 ), +DIV (CLK_ACLK133 ,"aclk133" ,"mout_aclk133" ,DIV_TOP ,12 ,3 ), +DIV (0 ,"div_onenand" ,"mout_onenand1" ,DIV_TOP ,16 ,3 ), +DIV (CLK_SCLK_SLIMBUS ,"sclk_slimbus" ,"sclk_epll" ,DIV_PERIL3 ,4 ,4 ), +DIV (CLK_SCLK_PCM1 ,"sclk_pcm1" ,"sclk_audio1" ,DIV_PERIL4 ,4 ,8 ), +DIV (CLK_SCLK_PCM2 ,"sclk_pcm2" ,"sclk_audio2" ,DIV_PERIL4 ,20 ,8 ), +DIV (CLK_SCLK_I2S1 ,"sclk_i2s1" ,"sclk_audio1" ,DIV_PERIL5 ,0 ,6 ), +DIV (CLK_SCLK_I2S2 ,"sclk_i2s2" ,"sclk_audio2" ,DIV_PERIL5 ,8 ,6 ), +DIV (0 ,"div_mmc4" ,"mout_mmc4" ,DIV_FSYS3 ,0 ,4 ), +DIV (0 ,"div_mmc_pre4" ,"div_mmc4" ,DIV_FSYS3 ,8 ,8 ), +DIV (0 ,"div_uart0" ,"mout_uart0" ,DIV_PERIL0 ,0 ,4 ), +DIV (0 ,"div_uart1" ,"mout_uart1" ,DIV_PERIL0 ,4 ,4 ), +DIV (0 ,"div_uart2" ,"mout_uart2" ,DIV_PERIL0 ,8 ,4 ), +DIV (0 ,"div_uart3" ,"mout_uart3" ,DIV_PERIL0 ,12 ,4 ), +DIV (0 ,"div_uart4" ,"mout_uart4" ,DIV_PERIL0 ,16 ,4 ), +DIV (0 ,"div_spi0" ,"mout_spi0" ,DIV_PERIL1 ,0 ,4 ), +DIV (0 ,"div_spi_pre0" ,"div_spi0" ,DIV_PERIL1 ,8 ,8 ), +DIV (0 ,"div_spi1" ,"mout_spi1" ,DIV_PERIL1 ,16 ,4 ), +DIV (0 ,"div_spi_pre1" ,"div_spi1" ,DIV_PERIL1 ,24 ,8 ), +DIV (0 ,"div_spi2" ,"mout_spi2" ,DIV_PERIL2 ,0 ,4 ), +DIV (0 ,"div_spi_pre2" ,"div_spi2" ,DIV_PERIL2 ,8 ,8 ), +DIV (0 ,"div_audio1" ,"mout_audio1" ,DIV_PERIL4 ,0 ,4 ), +DIV (0 ,"div_audio2" ,"mout_audio2" ,DIV_PERIL4 ,16 ,4 ), +DIV_A (CLK_ARM_CLK ,"arm_clk" ,"div_core2" ,DIV_CPU0 ,28 ,3 ,"armclk" ), +DIV_A (CLK_SCLK_APLL ,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 ,"sclk_apll" ), -DIV_F (none,"div_mipi_pre0" ,"div_mipi0" ,DIV_LCD0 ,20 ,4 , +DIV_F (0 ,"div_mipi_pre0" ,"div_mipi0" ,DIV_LCD0 ,20 ,4 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_mmc_pre0" ,"div_mmc0" ,DIV_FSYS1 ,8 ,8 , +DIV_F (0 ,"div_mmc_pre0" ,"div_mmc0" ,DIV_FSYS1 ,8 ,8 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_mmc_pre1" ,"div_mmc1" ,DIV_FSYS1 ,24 ,8 , +DIV_F (0 ,"div_mmc_pre1" ,"div_mmc1" ,DIV_FSYS1 ,24 ,8 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_mmc_pre2" ,"div_mmc2" ,DIV_FSYS2 ,8 ,8 , +DIV_F (0 ,"div_mmc_pre2" ,"div_mmc2" ,DIV_FSYS2 ,8 ,8 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_mmc_pre3" ,"div_mmc3" ,DIV_FSYS2 ,24 ,8 , +DIV_F (0 ,"div_mmc_pre3" ,"div_mmc3" ,DIV_FSYS2 ,24 ,8 ,CLK_SET_RATE_PARENT ,0 ), };/* list of divider clocks supported in exynos4210 soc */ static struct samsung_div_clock exynos4210_div_clks[]__initdata = { -DIV (aclk200,"aclk200" ,"mout_aclk200" ,DIV_TOP ,0 ,3 ), -DIV (sclk_fimg2d,"sclk_fimg2d" ,"mout_g2d" ,DIV_IMAGE ,0 ,4 ), -DIV (none,"div_fimd1" ,"mout_fimd1" ,E4210_DIV_LCD1 ,0 ,4 ), -DIV (none,"div_mipi1" ,"mout_mipi1" ,E4210_DIV_LCD1 ,16 ,4 ), -DIV (none,"div_sata" ,"mout_sata" ,DIV_FSYS0 ,20 ,4 ), -DIV_F (none,"div_mipi_pre1" ,"div_mipi1" ,E4210_DIV_LCD1 ,20 ,4 , +DIV (CLK_ACLK200 ,"aclk200" ,"mout_aclk200" ,DIV_TOP ,0 ,3 ), +DIV (CLK_SCLK_FIMG2D ,"sclk_fimg2d" ,"mout_g2d" ,DIV_IMAGE ,0 ,4 ), +DIV (0 ,"div_fimd1" ,"mout_fimd1" ,E4210_DIV_LCD1 ,0 ,4 ), +DIV (0 ,"div_mipi1" ,"mout_mipi1" ,E4210_DIV_LCD1 ,16 ,4 ), +DIV (0 ,"div_sata" ,"mout_sata" ,DIV_FSYS0 ,20 ,4 ), +DIV_F (0 ,"div_mipi_pre1" ,"div_mipi1" ,E4210_DIV_LCD1 ,20 ,4 ,CLK_SET_RATE_PARENT ,0 ), };/* list of divider clocks supported in exynos4x12 soc */ static struct samsung_div_clock exynos4x12_div_clks[]__initdata = { -DIV (none,"div_mdnie0" ,"mout_mdnie0" ,DIV_LCD0 ,4 ,4 ), -DIV (none,"div_mdnie_pwm0" ,"mout_mdnie_pwm0" ,DIV_LCD0 ,8 ,4 ), -DIV (none,"div_mdnie_pwm_pre0" ,"div_mdnie_pwm0" ,DIV_LCD0 ,12 ,4 ), -DIV (none,"div_mipihsi" ,"mout_mipihsi" ,DIV_FSYS0 ,20 ,4 ), -DIV (none,"div_jpeg" ,"mout_jpeg" ,E4X12_DIV_CAM1 ,0 ,4 ), -DIV (div_aclk200,"div_aclk200" ,"mout_aclk200" ,DIV_TOP ,0 ,3 ), -DIV (none,"div_aclk266_gps" ,"mout_aclk266_gps" ,DIV_TOP ,20 ,3 ), -DIV (div_aclk400_mcuisp,"div_aclk400_mcuisp" ,"mout_aclk400_mcuisp" , +DIV (0 ,"div_mdnie0" ,"mout_mdnie0" ,DIV_LCD0 ,4 ,4 ), +DIV (0 ,"div_mdnie_pwm0" ,"mout_mdnie_pwm0" ,DIV_LCD0 ,8 ,4 ), +DIV (0 ,"div_mdnie_pwm_pre0" ,"div_mdnie_pwm0" ,DIV_LCD0 ,12 ,4 ), +DIV (0 ,"div_mipihsi" ,"mout_mipihsi" ,DIV_FSYS0 ,20 ,4 ), +DIV (0 ,"div_jpeg" ,"mout_jpeg" ,E4X12_DIV_CAM1 ,0 ,4 ), +DIV (CLK_DIV_ACLK200 ,"div_aclk200" ,"mout_aclk200" ,DIV_TOP ,0 ,3 ), +DIV (0 ,"div_aclk266_gps" ,"mout_aclk266_gps" ,DIV_TOP ,20 ,3 ), +DIV (CLK_DIV_ACLK400_MCUISP ,"div_aclk400_mcuisp" ,"mout_aclk400_mcuisp" ,DIV_TOP ,24 ,3 ), -DIV (none,"div_pwm_isp" ,"mout_pwm_isp" ,E4X12_DIV_ISP ,0 ,4 ), -DIV (none,"div_spi0_isp" ,"mout_spi0_isp" ,E4X12_DIV_ISP ,4 ,4 ), -DIV (none,"div_spi0_isp_pre" ,"div_spi0_isp" ,E4X12_DIV_ISP ,8 ,8 ), -DIV (none,"div_spi1_isp" ,"mout_spi1_isp" ,E4X12_DIV_ISP ,16 ,4 ), -DIV (none,"div_spi1_isp_pre" ,"div_spi1_isp" ,E4X12_DIV_ISP ,20 ,8 ), -DIV (none,"div_uart_isp" ,"mout_uart_isp" ,E4X12_DIV_ISP ,28 ,4 ), -DIV (div_isp0,"div_isp0" ,"aclk200" ,E4X12_DIV_ISP0 ,0 ,3 ), -DIV (div_isp1,"div_isp1" ,"aclk200" ,E4X12_DIV_ISP0 ,4 ,3 ), -DIV (none,"div_mpwm" ,"div_isp1" ,E4X12_DIV_ISP1 ,0 ,3 ), -DIV (div_mcuisp0,"div_mcuisp0" ,"aclk400_mcuisp" ,E4X12_DIV_ISP1 ,4 ,3 ), -DIV (div_mcuisp1,"div_mcuisp1" ,"div_mcuisp0" ,E4X12_DIV_ISP1 ,8 ,3 ), -DIV (sclk_fimg2d,"sclk_fimg2d" ,"mout_g2d" ,DIV_DMC1 ,0 ,4 ), +DIV (0 ,"div_pwm_isp" ,"mout_pwm_isp" ,E4X12_DIV_ISP ,0 ,4 ), +DIV (0 ,"div_spi0_isp" ,"mout_spi0_isp" ,E4X12_DIV_ISP ,4 ,4 ), +DIV (0 ,"div_spi0_isp_pre" ,"div_spi0_isp" ,E4X12_DIV_ISP ,8 ,8 ), +DIV (0 ,"div_spi1_isp" ,"mout_spi1_isp" ,E4X12_DIV_ISP ,16 ,4 ), +DIV (0 ,"div_spi1_isp_pre" ,"div_spi1_isp" ,E4X12_DIV_ISP ,20 ,8 ), +DIV (0 ,"div_uart_isp" ,"mout_uart_isp" ,E4X12_DIV_ISP ,28 ,4 ), +DIV (CLK_DIV_ISP0 ,"div_isp0" ,"aclk200" ,E4X12_DIV_ISP0 ,0 ,3 ), +DIV (CLK_DIV_ISP1 ,"div_isp1" ,"aclk200" ,E4X12_DIV_ISP0 ,4 ,3 ), +DIV (0 ,"div_mpwm" ,"div_isp1" ,E4X12_DIV_ISP1 ,0 ,3 ), +DIV (CLK_DIV_MCUISP0 ,"div_mcuisp0" ,"aclk400_mcuisp" ,E4X12_DIV_ISP1 ,4 , +3 ), +DIV (CLK_DIV_MCUISP1 ,"div_mcuisp1" ,"div_mcuisp0" ,E4X12_DIV_ISP1 ,8 , +3 ), +DIV (CLK_SCLK_FIMG2D ,"sclk_fimg2d" ,"mout_g2d" ,DIV_DMC1 ,0 ,4 ), };/* list of gate clocks supported in all exynos4 soc's */
@@ -603,327 +546,339 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {* the device name and clock alias names specified below for some * of the clocks can be removed. */ -GATE (sclk_hdmi,"sclk_hdmi" ,"mout_hdmi" ,SRC_MASK_TV ,0 ,0 ,0 ), -GATE (sclk_spdif,"sclk_spdif" ,"mout_spdif" ,SRC_MASK_PERIL1 ,8 ,0 ,0 ), -GATE (jpeg,"jpeg" ,"aclk160" ,GATE_IP_CAM ,6 ,0 ,0 ), -GATE (mie0,"mie0" ,"aclk160" ,GATE_IP_LCD0 ,1 ,0 ,0 ), -GATE (dsim0,"dsim0" ,"aclk160" ,GATE_IP_LCD0 ,3 ,0 ,0 ), -GATE (fimd1,"fimd1" ,"aclk160" ,E4210_GATE_IP_LCD1 ,0 ,0 ,0 ), -GATE (mie1,"mie1" ,"aclk160" ,E4210_GATE_IP_LCD1 ,1 ,0 ,0 ), -GATE (dsim1,"dsim1" ,"aclk160" ,E4210_GATE_IP_LCD1 ,3 ,0 ,0 ), -GATE (smmu_fimd1,"smmu_fimd1" ,"aclk160" ,E4210_GATE_IP_LCD1 ,4 ,0 ,0 ), -GATE (tsi,"tsi" ,"aclk133" ,GATE_IP_FSYS ,4 ,0 ,0 ), -GATE (sromc,"sromc" ,"aclk133" ,GATE_IP_FSYS ,11 ,0 ,0 ), -GATE (sclk_g3d,"sclk_g3d" ,"div_g3d" ,GATE_IP_G3D ,0 , +GATE (CLK_SCLK_HDMI ,"sclk_hdmi" ,"mout_hdmi" ,SRC_MASK_TV ,0 ,0 ,0 ), +GATE (CLK_SCLK_SPDIF ,"sclk_spdif" ,"mout_spdif" ,SRC_MASK_PERIL1 ,8 ,0 , +0 ), +GATE (CLK_JPEG ,"jpeg" ,"aclk160" ,GATE_IP_CAM ,6 ,0 ,0 ), +GATE (CLK_MIE0 ,"mie0" ,"aclk160" ,GATE_IP_LCD0 ,1 ,0 ,0 ), +GATE (CLK_DSIM0 ,"dsim0" ,"aclk160" ,GATE_IP_LCD0 ,3 ,0 ,0 ), +GATE (CLK_FIMD1 ,"fimd1" ,"aclk160" ,E4210_GATE_IP_LCD1 ,0 ,0 ,0 ), +GATE (CLK_MIE1 ,"mie1" ,"aclk160" ,E4210_GATE_IP_LCD1 ,1 ,0 ,0 ), +GATE (CLK_DSIM1 ,"dsim1" ,"aclk160" ,E4210_GATE_IP_LCD1 ,3 ,0 ,0 ), +GATE (CLK_SMMU_FIMD1 ,"smmu_fimd1" ,"aclk160" ,E4210_GATE_IP_LCD1 ,4 ,0 , +0 ), +GATE (CLK_TSI ,"tsi" ,"aclk133" ,GATE_IP_FSYS ,4 ,0 ,0 ), +GATE (CLK_SROMC ,"sromc" ,"aclk133" ,GATE_IP_FSYS ,11 ,0 ,0 ), +GATE (CLK_SCLK_G3D ,"sclk_g3d" ,"div_g3d" ,GATE_IP_G3D ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (usb_device,"usb_device" ,"aclk133" ,GATE_IP_FSYS ,13 ,0 ,0 ), -GATE (onenand,"onenand" ,"aclk133" ,GATE_IP_FSYS ,15 ,0 ,0 ), -GATE (nfcon,"nfcon" ,"aclk133" ,GATE_IP_FSYS ,16 ,0 ,0 ), -GATE (gps,"gps" ,"aclk133" ,GATE_IP_GPS ,0 ,0 ,0 ), -GATE (smmu_gps,"smmu_gps" ,"aclk133" ,GATE_IP_GPS ,1 ,0 ,0 ), -GATE (slimbus,"slimbus" ,"aclk100" ,GATE_IP_PERIL ,25 ,0 ,0 ), -GATE (sclk_cam0,"sclk_cam0" ,"div_cam0" ,GATE_SCLK_CAM ,4 , +GATE (CLK_USB_DEVICE ,"usb_device" ,"aclk133" ,GATE_IP_FSYS ,13 ,0 ,0 ), +GATE (CLK_ONENAND ,"onenand" ,"aclk133" ,GATE_IP_FSYS ,15 ,0 ,0 ), +GATE (CLK_NFCON ,"nfcon" ,"aclk133" ,GATE_IP_FSYS ,16 ,0 ,0 ), +GATE (CLK_GPS ,"gps" ,"aclk133" ,GATE_IP_GPS ,0 ,0 ,0 ), +GATE (CLK_SMMU_GPS ,"smmu_gps" ,"aclk133" ,GATE_IP_GPS ,1 ,0 ,0 ), +GATE (CLK_SLIMBUS ,"slimbus" ,"aclk100" ,GATE_IP_PERIL ,25 ,0 ,0 ), +GATE (CLK_SCLK_CAM0 ,"sclk_cam0" ,"div_cam0" ,GATE_SCLK_CAM ,4 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_cam1,"sclk_cam1" ,"div_cam1" ,GATE_SCLK_CAM ,5 , +GATE (CLK_SCLK_CAM1 ,"sclk_cam1" ,"div_cam1" ,GATE_SCLK_CAM ,5 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mipi0,"sclk_mipi0" ,"div_mipi_pre0" , +GATE (CLK_SCLK_MIPI0 ,"sclk_mipi0" ,"div_mipi_pre0" ,SRC_MASK_LCD0 ,12 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_audio0,"sclk_audio0" ,"div_audio0" ,SRC_MASK_MAUDIO ,0 , +GATE (CLK_SCLK_AUDIO0 ,"sclk_audio0" ,"div_audio0" ,SRC_MASK_MAUDIO ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_audio1,"sclk_audio1" ,"div_audio1" ,SRC_MASK_PERIL1 ,0 , +GATE (CLK_SCLK_AUDIO1 ,"sclk_audio1" ,"div_audio1" ,SRC_MASK_PERIL1 ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE_D (vp,"s5p-mixer" ,"vp" ,"aclk160" ,GATE_IP_TV ,0 ,0 ,0 ), -GATE_D (mixer,"s5p-mixer" ,"mixer" ,"aclk160" ,GATE_IP_TV ,1 ,0 ,0 ), -GATE_D (hdmi,"exynos4-hdmi" ,"hdmi" ,"aclk160" ,GATE_IP_TV ,3 ,0 ,0 ), -GATE_A (pwm,"pwm" ,"aclk100" ,GATE_IP_PERIL ,24 ,0 ,0 ,"timers" ), -GATE_A (sdmmc4,"sdmmc4" ,"aclk133" ,GATE_IP_FSYS ,9 ,0 ,0 ,"biu" ), -GATE_A (usb_host,"usb_host" ,"aclk133" , +GATE_D (CLK_VP ,"s5p-mixer" ,"vp" ,"aclk160" ,GATE_IP_TV ,0 ,0 ,0 ), +GATE_D (CLK_MIXER ,"s5p-mixer" ,"mixer" ,"aclk160" ,GATE_IP_TV ,1 ,0 ,0 ), +GATE_D (CLK_HDMI ,"exynos4-hdmi" ,"hdmi" ,"aclk160" ,GATE_IP_TV ,3 ,0 , +0 ), +GATE_A (CLK_PWM ,"pwm" ,"aclk100" ,GATE_IP_PERIL ,24 ,0 ,0 ,"timers" ), +GATE_A (CLK_SDMMC4 ,"sdmmc4" ,"aclk133" ,GATE_IP_FSYS ,9 ,0 ,0 ,"biu" ), +GATE_A (CLK_USB_HOST ,"usb_host" ,"aclk133" ,GATE_IP_FSYS ,12 ,0 ,0 ,"usbhost" ), -GATE_DA (sclk_fimc0,"exynos4-fimc.0" ,"sclk_fimc0" ,"div_fimc0" , +GATE_DA (CLK_SCLK_FIMC0 ,"exynos4-fimc.0" ,"sclk_fimc0" ,"div_fimc0" ,SRC_MASK_CAM ,0 ,CLK_SET_RATE_PARENT ,0 ,"sclk_fimc" ), -GATE_DA (sclk_fimc1,"exynos4-fimc.1" ,"sclk_fimc1" ,"div_fimc1" , +GATE_DA (CLK_SCLK_FIMC1 ,"exynos4-fimc.1" ,"sclk_fimc1" ,"div_fimc1" ,SRC_MASK_CAM ,4 ,CLK_SET_RATE_PARENT ,0 ,"sclk_fimc" ), -GATE_DA (sclk_fimc2,"exynos4-fimc.2" ,"sclk_fimc2" ,"div_fimc2" , +GATE_DA (CLK_SCLK_FIMC2 ,"exynos4-fimc.2" ,"sclk_fimc2" ,"div_fimc2" ,SRC_MASK_CAM ,8 ,CLK_SET_RATE_PARENT ,0 ,"sclk_fimc" ), -GATE_DA (sclk_fimc3,"exynos4-fimc.3" ,"sclk_fimc3" ,"div_fimc3" , +GATE_DA (CLK_SCLK_FIMC3 ,"exynos4-fimc.3" ,"sclk_fimc3" ,"div_fimc3" ,SRC_MASK_CAM ,12 ,CLK_SET_RATE_PARENT ,0 ,"sclk_fimc" ), -GATE_DA (sclk_csis0,"s5p-mipi-csis.0" ,"sclk_csis0" ,"div_csis0" , +GATE_DA (CLK_SCLK_CSIS0 ,"s5p-mipi-csis.0" ,"sclk_csis0" ,"div_csis0" ,SRC_MASK_CAM ,24 ,CLK_SET_RATE_PARENT ,0 ,"sclk_csis" ), -GATE_DA (sclk_csis1,"s5p-mipi-csis.1" ,"sclk_csis1" ,"div_csis1" , +GATE_DA (CLK_SCLK_CSIS1 ,"s5p-mipi-csis.1" ,"sclk_csis1" ,"div_csis1" ,SRC_MASK_CAM ,28 ,CLK_SET_RATE_PARENT ,0 ,"sclk_csis" ), -GATE_DA (sclk_fimd0,"exynos4-fb.0" ,"sclk_fimd0" ,"div_fimd0" , +GATE_DA (CLK_SCLK_FIMD0 ,"exynos4-fb.0" ,"sclk_fimd0" ,"div_fimd0" ,SRC_MASK_LCD0 ,0 ,CLK_SET_RATE_PARENT ,0 ,"sclk_fimd" ), -GATE_DA (sclk_mmc0,"exynos4-sdhci.0" ,"sclk_mmc0" ,"div_mmc_pre0" , +GATE_DA (CLK_SCLK_MMC0 ,"exynos4-sdhci.0" ,"sclk_mmc0" ,"div_mmc_pre0" ,SRC_MASK_FSYS ,0 ,CLK_SET_RATE_PARENT ,0 ,"mmc_busclk.2" ), -GATE_DA (sclk_mmc1,"exynos4-sdhci.1" ,"sclk_mmc1" ,"div_mmc_pre1" , +GATE_DA (CLK_SCLK_MMC1 ,"exynos4-sdhci.1" ,"sclk_mmc1" ,"div_mmc_pre1" ,SRC_MASK_FSYS ,4 ,CLK_SET_RATE_PARENT ,0 ,"mmc_busclk.2" ), -GATE_DA (sclk_mmc2,"exynos4-sdhci.2" ,"sclk_mmc2" ,"div_mmc_pre2" , +GATE_DA (CLK_SCLK_MMC2 ,"exynos4-sdhci.2" ,"sclk_mmc2" ,"div_mmc_pre2" ,SRC_MASK_FSYS ,8 ,CLK_SET_RATE_PARENT ,0 ,"mmc_busclk.2" ), -GATE_DA (sclk_mmc3,"exynos4-sdhci.3" ,"sclk_mmc3" ,"div_mmc_pre3" , +GATE_DA (CLK_SCLK_MMC3 ,"exynos4-sdhci.3" ,"sclk_mmc3" ,"div_mmc_pre3" ,SRC_MASK_FSYS ,12 ,CLK_SET_RATE_PARENT ,0 ,"mmc_busclk.2" ), -GATE_DA (sclk_mmc4,NULL ,"sclk_mmc4" ,"div_mmc_pre4" , +GATE_DA (CLK_SCLK_MMC4 ,NULL ,"sclk_mmc4" ,"div_mmc_pre4" ,SRC_MASK_FSYS ,16 ,CLK_SET_RATE_PARENT ,0 ,"ciu" ), -GATE_DA (sclk_uart0,"exynos4210-uart.0" ,"uclk0" ,"div_uart0" , +GATE_DA (CLK_SCLK_UART0 ,"exynos4210-uart.0" ,"uclk0" ,"div_uart0" ,SRC_MASK_PERIL0 ,0 ,CLK_SET_RATE_PARENT ,0 ,"clk_uart_baud0" ), -GATE_DA (sclk_uart1,"exynos4210-uart.1" ,"uclk1" ,"div_uart1" , +GATE_DA (CLK_SCLK_UART1 ,"exynos4210-uart.1" ,"uclk1" ,"div_uart1" ,SRC_MASK_PERIL0 ,4 ,CLK_SET_RATE_PARENT ,0 ,"clk_uart_baud0" ), -GATE_DA (sclk_uart2,"exynos4210-uart.2" ,"uclk2" ,"div_uart2" , +GATE_DA (CLK_SCLK_UART2 ,"exynos4210-uart.2" ,"uclk2" ,"div_uart2" ,SRC_MASK_PERIL0 ,8 ,CLK_SET_RATE_PARENT ,0 ,"clk_uart_baud0" ), -GATE_DA (sclk_uart3,"exynos4210-uart.3" ,"uclk3" ,"div_uart3" , +GATE_DA (CLK_SCLK_UART3 ,"exynos4210-uart.3" ,"uclk3" ,"div_uart3" ,SRC_MASK_PERIL0 ,12 ,CLK_SET_RATE_PARENT ,0 ,"clk_uart_baud0" ), -GATE_DA (sclk_uart4,"exynos4210-uart.4" ,"uclk4" ,"div_uart4" , +GATE_DA (CLK_SCLK_UART4 ,"exynos4210-uart.4" ,"uclk4" ,"div_uart4" ,SRC_MASK_PERIL0 ,16 ,CLK_SET_RATE_PARENT ,0 ,"clk_uart_baud0" ), -GATE (sclk_audio2,"sclk_audio2" ,"div_audio2" ,SRC_MASK_PERIL1 ,4 , +GATE (CLK_SCLK_AUDIO2 ,"sclk_audio2" ,"div_audio2" ,SRC_MASK_PERIL1 ,4 ,CLK_SET_RATE_PARENT ,0 ), -GATE_DA (sclk_spi0,"exynos4210-spi.0" ,"sclk_spi0" ,"div_spi_pre0" , +GATE_DA (CLK_SCLK_SPI0 ,"exynos4210-spi.0" ,"sclk_spi0" ,"div_spi_pre0" ,SRC_MASK_PERIL1 ,16 ,CLK_SET_RATE_PARENT ,0 ,"spi_busclk0" ), -GATE_DA (sclk_spi1,"exynos4210-spi.1" ,"sclk_spi1" ,"div_spi_pre1" , +GATE_DA (CLK_SCLK_SPI1 ,"exynos4210-spi.1" ,"sclk_spi1" ,"div_spi_pre1" ,SRC_MASK_PERIL1 ,20 ,CLK_SET_RATE_PARENT ,0 ,"spi_busclk0" ), -GATE_DA (sclk_spi2,"exynos4210-spi.2" ,"sclk_spi2" ,"div_spi_pre2" , +GATE_DA (CLK_SCLK_SPI2 ,"exynos4210-spi.2" ,"sclk_spi2" ,"div_spi_pre2" ,SRC_MASK_PERIL1 ,24 ,CLK_SET_RATE_PARENT ,0 ,"spi_busclk0" ), -GATE_DA (fimc0,"exynos4-fimc.0" ,"fimc0" ,"aclk160" , +GATE_DA (CLK_FIMC0 ,"exynos4-fimc.0" ,"fimc0" ,"aclk160" ,GATE_IP_CAM ,0 ,0 ,0 ,"fimc" ), -GATE_DA (fimc1,"exynos4-fimc.1" ,"fimc1" ,"aclk160" , +GATE_DA (CLK_FIMC1 ,"exynos4-fimc.1" ,"fimc1" ,"aclk160" ,GATE_IP_CAM ,1 ,0 ,0 ,"fimc" ), -GATE_DA (fimc2,"exynos4-fimc.2" ,"fimc2" ,"aclk160" , +GATE_DA (CLK_FIMC2 ,"exynos4-fimc.2" ,"fimc2" ,"aclk160" ,GATE_IP_CAM ,2 ,0 ,0 ,"fimc" ), -GATE_DA (fimc3,"exynos4-fimc.3" ,"fimc3" ,"aclk160" , +GATE_DA (CLK_FIMC3 ,"exynos4-fimc.3" ,"fimc3" ,"aclk160" ,GATE_IP_CAM ,3 ,0 ,0 ,"fimc" ), -GATE_DA (csis0,"s5p-mipi-csis.0" ,"csis0" ,"aclk160" , +GATE_DA (CLK_CSIS0 ,"s5p-mipi-csis.0" ,"csis0" ,"aclk160" ,GATE_IP_CAM ,4 ,0 ,0 ,"fimc" ), -GATE_DA (csis1,"s5p-mipi-csis.1" ,"csis1" ,"aclk160" , +GATE_DA (CLK_CSIS1 ,"s5p-mipi-csis.1" ,"csis1" ,"aclk160" ,GATE_IP_CAM ,5 ,0 ,0 ,"fimc" ), -GATE_DA (smmu_fimc0,"exynos-sysmmu.5" ,"smmu_fimc0" ,"aclk160" , +GATE_DA (CLK_SMMU_FIMC0 ,"exynos-sysmmu.5" ,"smmu_fimc0" ,"aclk160" ,GATE_IP_CAM ,7 ,0 ,0 ,"sysmmu" ), -GATE_DA (smmu_fimc1,"exynos-sysmmu.6" ,"smmu_fimc1" ,"aclk160" , +GATE_DA (CLK_SMMU_FIMC1 ,"exynos-sysmmu.6" ,"smmu_fimc1" ,"aclk160" ,GATE_IP_CAM ,8 ,0 ,0 ,"sysmmu" ), -GATE_DA (smmu_fimc2,"exynos-sysmmu.7" ,"smmu_fimc2" ,"aclk160" , +GATE_DA (CLK_SMMU_FIMC2 ,"exynos-sysmmu.7" ,"smmu_fimc2" ,"aclk160" ,GATE_IP_CAM ,9 ,0 ,0 ,"sysmmu" ), -GATE_DA (smmu_fimc3,"exynos-sysmmu.8" ,"smmu_fimc3" ,"aclk160" , +GATE_DA (CLK_SMMU_FIMC3 ,"exynos-sysmmu.8" ,"smmu_fimc3" ,"aclk160" ,GATE_IP_CAM ,10 ,0 ,0 ,"sysmmu" ), -GATE_DA (smmu_jpeg,"exynos-sysmmu.3" ,"smmu_jpeg" ,"aclk160" , +GATE_DA (CLK_SMMU_JPEG ,"exynos-sysmmu.3" ,"smmu_jpeg" ,"aclk160" ,GATE_IP_CAM ,11 ,0 ,0 ,"sysmmu" ), -GATE (pixelasyncm0,"pxl_async0" ,"aclk160" ,GATE_IP_CAM ,17 ,0 ,0 ), -GATE (pixelasyncm1,"pxl_async1" ,"aclk160" ,GATE_IP_CAM ,18 ,0 ,0 ), -GATE_DA (smmu_tv,"exynos-sysmmu.2" ,"smmu_tv" ,"aclk160" , +GATE (CLK_PIXELASYNCM0 ,"pxl_async0" ,"aclk160" ,GATE_IP_CAM ,17 ,0 ,0 ), +GATE (CLK_PIXELASYNCM1 ,"pxl_async1" ,"aclk160" ,GATE_IP_CAM ,18 ,0 ,0 ), +GATE_DA (CLK_SMMU_TV ,"exynos-sysmmu.2" ,"smmu_tv" ,"aclk160" ,GATE_IP_TV ,4 ,0 ,0 ,"sysmmu" ), -GATE_DA (mfc,"s5p-mfc" ,"mfc" ,"aclk100" ,GATE_IP_MFC ,0 ,0 ,0 ,"mfc" ), -GATE_DA (smmu_mfcl,"exynos-sysmmu.0" ,"smmu_mfcl" ,"aclk100" , +GATE_DA (CLK_MFC ,"s5p-mfc" ,"mfc" ,"aclk100" ,GATE_IP_MFC ,0 ,0 ,0 , +"mfc" ), +GATE_DA (CLK_SMMU_MFCL ,"exynos-sysmmu.0" ,"smmu_mfcl" ,"aclk100" ,GATE_IP_MFC ,1 ,0 ,0 ,"sysmmu" ), -GATE_DA (smmu_mfcr,"exynos-sysmmu.1" ,"smmu_mfcr" ,"aclk100" , +GATE_DA (CLK_SMMU_MFCR ,"exynos-sysmmu.1" ,"smmu_mfcr" ,"aclk100" ,GATE_IP_MFC ,2 ,0 ,0 ,"sysmmu" ), -GATE_DA (fimd0,"exynos4-fb.0" ,"fimd0" ,"aclk160" , +GATE_DA (CLK_FIMD0 ,"exynos4-fb.0" ,"fimd0" ,"aclk160" ,GATE_IP_LCD0 ,0 ,0 ,0 ,"fimd" ), -GATE_DA (smmu_fimd0,"exynos-sysmmu.10" ,"smmu_fimd0" ,"aclk160" , +GATE_DA (CLK_SMMU_FIMD0 ,"exynos-sysmmu.10" ,"smmu_fimd0" ,"aclk160" ,GATE_IP_LCD0 ,4 ,0 ,0 ,"sysmmu" ), -GATE_DA (pdma0,"dma-pl330.0" ,"pdma0" ,"aclk133" , +GATE_DA (CLK_PDMA0 ,"dma-pl330.0" ,"pdma0" ,"aclk133" ,GATE_IP_FSYS ,0 ,0 ,0 ,"dma" ), -GATE_DA (pdma1,"dma-pl330.1" ,"pdma1" ,"aclk133" , +GATE_DA (CLK_PDMA1 ,"dma-pl330.1" ,"pdma1" ,"aclk133" ,GATE_IP_FSYS ,1 ,0 ,0 ,"dma" ), -GATE_DA (sdmmc0,"exynos4-sdhci.0" ,"sdmmc0" ,"aclk133" , +GATE_DA (CLK_SDMMC0 ,"exynos4-sdhci.0" ,"sdmmc0" ,"aclk133" ,GATE_IP_FSYS ,5 ,0 ,0 ,"hsmmc" ), -GATE_DA (sdmmc1,"exynos4-sdhci.1" ,"sdmmc1" ,"aclk133" , +GATE_DA (CLK_SDMMC1 ,"exynos4-sdhci.1" ,"sdmmc1" ,"aclk133" ,GATE_IP_FSYS ,6 ,0 ,0 ,"hsmmc" ), -GATE_DA (sdmmc2,"exynos4-sdhci.2" ,"sdmmc2" ,"aclk133" , +GATE_DA (CLK_SDMMC2 ,"exynos4-sdhci.2" ,"sdmmc2" ,"aclk133" ,GATE_IP_FSYS ,7 ,0 ,0 ,"hsmmc" ), -GATE_DA (sdmmc3,"exynos4-sdhci.3" ,"sdmmc3" ,"aclk133" , +GATE_DA (CLK_SDMMC3 ,"exynos4-sdhci.3" ,"sdmmc3" ,"aclk133" ,GATE_IP_FSYS ,8 ,0 ,0 ,"hsmmc" ), -GATE_DA (uart0,"exynos4210-uart.0" ,"uart0" ,"aclk100" , +GATE_DA (CLK_UART0 ,"exynos4210-uart.0" ,"uart0" ,"aclk100" ,GATE_IP_PERIL ,0 ,0 ,0 ,"uart" ), -GATE_DA (uart1,"exynos4210-uart.1" ,"uart1" ,"aclk100" , +GATE_DA (CLK_UART1 ,"exynos4210-uart.1" ,"uart1" ,"aclk100" ,GATE_IP_PERIL ,1 ,0 ,0 ,"uart" ), -GATE_DA (uart2,"exynos4210-uart.2" ,"uart2" ,"aclk100" , +GATE_DA (CLK_UART2 ,"exynos4210-uart.2" ,"uart2" ,"aclk100" ,GATE_IP_PERIL ,2 ,0 ,0 ,"uart" ), -GATE_DA (uart3,"exynos4210-uart.3" ,"uart3" ,"aclk100" , +GATE_DA (CLK_UART3 ,"exynos4210-uart.3" ,"uart3" ,"aclk100" ,GATE_IP_PERIL ,3 ,0 ,0 ,"uart" ), -GATE_DA (uart4,"exynos4210-uart.4" ,"uart4" ,"aclk100" , +GATE_DA (CLK_UART4 ,"exynos4210-uart.4" ,"uart4" ,"aclk100" ,GATE_IP_PERIL ,4 ,0 ,0 ,"uart" ), -GATE_DA (i2c0,"s3c2440-i2c.0" ,"i2c0" ,"aclk100" , +GATE_DA (CLK_I2C0 ,"s3c2440-i2c.0" ,"i2c0" ,"aclk100" ,GATE_IP_PERIL ,6 ,0 ,0 ,"i2c" ), -GATE_DA (i2c1,"s3c2440-i2c.1" ,"i2c1" ,"aclk100" , +GATE_DA (CLK_I2C1 ,"s3c2440-i2c.1" ,"i2c1" ,"aclk100" ,GATE_IP_PERIL ,7 ,0 ,0 ,"i2c" ), -GATE_DA (i2c2,"s3c2440-i2c.2" ,"i2c2" ,"aclk100" , +GATE_DA (CLK_I2C2 ,"s3c2440-i2c.2" ,"i2c2" ,"aclk100" ,GATE_IP_PERIL ,8 ,0 ,0 ,"i2c" ), -GATE_DA (i2c3,"s3c2440-i2c.3" ,"i2c3" ,"aclk100" , +GATE_DA (CLK_I2C3 ,"s3c2440-i2c.3" ,"i2c3" ,"aclk100" ,GATE_IP_PERIL ,9 ,0 ,0 ,"i2c" ), -GATE_DA (i2c4,"s3c2440-i2c.4" ,"i2c4" ,"aclk100" , +GATE_DA (CLK_I2C4 ,"s3c2440-i2c.4" ,"i2c4" ,"aclk100" ,GATE_IP_PERIL ,10 ,0 ,0 ,"i2c" ), -GATE_DA (i2c5,"s3c2440-i2c.5" ,"i2c5" ,"aclk100" , +GATE_DA (CLK_I2C5 ,"s3c2440-i2c.5" ,"i2c5" ,"aclk100" ,GATE_IP_PERIL ,11 ,0 ,0 ,"i2c" ), -GATE_DA (i2c6,"s3c2440-i2c.6" ,"i2c6" ,"aclk100" , +GATE_DA (CLK_I2C6 ,"s3c2440-i2c.6" ,"i2c6" ,"aclk100" ,GATE_IP_PERIL ,12 ,0 ,0 ,"i2c" ), -GATE_DA (i2c7,"s3c2440-i2c.7" ,"i2c7" ,"aclk100" , +GATE_DA (CLK_I2C7 ,"s3c2440-i2c.7" ,"i2c7" ,"aclk100" ,GATE_IP_PERIL ,13 ,0 ,0 ,"i2c" ), -GATE_DA (i2c_hdmi,"s3c2440-hdmiphy-i2c" ,"i2c-hdmi" ,"aclk100" , +GATE_DA (CLK_I2C_HDMI ,"s3c2440-hdmiphy-i2c" ,"i2c-hdmi" ,"aclk100" ,GATE_IP_PERIL ,14 ,0 ,0 ,"i2c" ), -GATE_DA (spi0,"exynos4210-spi.0" ,"spi0" ,"aclk100" , +GATE_DA (CLK_SPI0 ,"exynos4210-spi.0" ,"spi0" ,"aclk100" ,GATE_IP_PERIL ,16 ,0 ,0 ,"spi" ), -GATE_DA (spi1,"exynos4210-spi.1" ,"spi1" ,"aclk100" , +GATE_DA (CLK_SPI1 ,"exynos4210-spi.1" ,"spi1" ,"aclk100" ,GATE_IP_PERIL ,17 ,0 ,0 ,"spi" ), -GATE_DA (spi2,"exynos4210-spi.2" ,"spi2" ,"aclk100" , +GATE_DA (CLK_SPI2 ,"exynos4210-spi.2" ,"spi2" ,"aclk100" ,GATE_IP_PERIL ,18 ,0 ,0 ,"spi" ), -GATE_DA (i2s1,"samsung-i2s.1" ,"i2s1" ,"aclk100" , +GATE_DA (CLK_I2S1 ,"samsung-i2s.1" ,"i2s1" ,"aclk100" ,GATE_IP_PERIL ,20 ,0 ,0 ,"iis" ), -GATE_DA (i2s2,"samsung-i2s.2" ,"i2s2" ,"aclk100" , +GATE_DA (CLK_I2S2 ,"samsung-i2s.2" ,"i2s2" ,"aclk100" ,GATE_IP_PERIL ,21 ,0 ,0 ,"iis" ), -GATE_DA (pcm1,"samsung-pcm.1" ,"pcm1" ,"aclk100" , +GATE_DA (CLK_PCM1 ,"samsung-pcm.1" ,"pcm1" ,"aclk100" ,GATE_IP_PERIL ,22 ,0 ,0 ,"pcm" ), -GATE_DA (pcm2,"samsung-pcm.2" ,"pcm2" ,"aclk100" , +GATE_DA (CLK_PCM2 ,"samsung-pcm.2" ,"pcm2" ,"aclk100" ,GATE_IP_PERIL ,23 ,0 ,0 ,"pcm" ), -GATE_DA (spdif,"samsung-spdif" ,"spdif" ,"aclk100" , +GATE_DA (CLK_SPDIF ,"samsung-spdif" ,"spdif" ,"aclk100" ,GATE_IP_PERIL ,26 ,0 ,0 ,"spdif" ), -GATE_DA (ac97,"samsung-ac97" ,"ac97" ,"aclk100" , +GATE_DA (CLK_AC97 ,"samsung-ac97" ,"ac97" ,"aclk100" , GATE_IP_PERIL, 27, 0, 0, "ac97"), };/* list of gate clocks supported in exynos4210 soc */ static struct samsung_gate_clock exynos4210_gate_clks[]__initdata = { -GATE (tvenc,"tvenc" ,"aclk160" ,GATE_IP_TV ,2 ,0 ,0 ), -GATE (g2d,"g2d" ,"aclk200" ,E4210_GATE_IP_IMAGE ,0 ,0 ,0 ), -GATE (rotator,"rotator" ,"aclk200" ,E4210_GATE_IP_IMAGE ,1 ,0 ,0 ), -GATE (mdma,"mdma" ,"aclk200" ,E4210_GATE_IP_IMAGE ,2 ,0 ,0 ), -GATE (smmu_g2d,"smmu_g2d" ,"aclk200" ,E4210_GATE_IP_IMAGE ,3 ,0 ,0 ), -GATE (smmu_mdma,"smmu_mdma" ,"aclk200" ,E4210_GATE_IP_IMAGE ,5 ,0 ,0 ), -GATE (pcie_phy,"pcie_phy" ,"aclk133" ,GATE_IP_FSYS ,2 ,0 ,0 ), -GATE (sata_phy,"sata_phy" ,"aclk133" ,GATE_IP_FSYS ,3 ,0 ,0 ), -GATE (sata,"sata" ,"aclk133" ,GATE_IP_FSYS ,10 ,0 ,0 ), -GATE (pcie,"pcie" ,"aclk133" ,GATE_IP_FSYS ,14 ,0 ,0 ), -GATE (smmu_pcie,"smmu_pcie" ,"aclk133" ,GATE_IP_FSYS ,18 ,0 ,0 ), -GATE (modemif,"modemif" ,"aclk100" ,GATE_IP_PERIL ,28 ,0 ,0 ), -GATE (chipid,"chipid" ,"aclk100" ,E4210_GATE_IP_PERIR ,0 ,0 ,0 ), -GATE (sysreg,"sysreg" ,"aclk100" ,E4210_GATE_IP_PERIR ,0 , +GATE (CLK_TVENC ,"tvenc" ,"aclk160" ,GATE_IP_TV ,2 ,0 ,0 ), +GATE (CLK_G2D ,"g2d" ,"aclk200" ,E4210_GATE_IP_IMAGE ,0 ,0 ,0 ), +GATE (CLK_ROTATOR ,"rotator" ,"aclk200" ,E4210_GATE_IP_IMAGE ,1 ,0 ,0 ), +GATE (CLK_MDMA ,"mdma" ,"aclk200" ,E4210_GATE_IP_IMAGE ,2 ,0 ,0 ), +GATE (CLK_SMMU_G2D ,"smmu_g2d" ,"aclk200" ,E4210_GATE_IP_IMAGE ,3 ,0 ,0 ), +GATE (CLK_SMMU_MDMA ,"smmu_mdma" ,"aclk200" ,E4210_GATE_IP_IMAGE ,5 ,0 , +0 ), +GATE (CLK_PCIE_PHY ,"pcie_phy" ,"aclk133" ,GATE_IP_FSYS ,2 ,0 ,0 ), +GATE (CLK_SATA_PHY ,"sata_phy" ,"aclk133" ,GATE_IP_FSYS ,3 ,0 ,0 ), +GATE (CLK_SATA ,"sata" ,"aclk133" ,GATE_IP_FSYS ,10 ,0 ,0 ), +GATE (CLK_PCIE ,"pcie" ,"aclk133" ,GATE_IP_FSYS ,14 ,0 ,0 ), +GATE (CLK_SMMU_PCIE ,"smmu_pcie" ,"aclk133" ,GATE_IP_FSYS ,18 ,0 ,0 ), +GATE (CLK_MODEMIF ,"modemif" ,"aclk100" ,GATE_IP_PERIL ,28 ,0 ,0 ), +GATE (CLK_CHIPID ,"chipid" ,"aclk100" ,E4210_GATE_IP_PERIR ,0 ,0 ,0 ), +GATE (CLK_SYSREG ,"sysreg" ,"aclk100" ,E4210_GATE_IP_PERIR ,0 ,CLK_IGNORE_UNUSED ,0 ), -GATE (hdmi_cec,"hdmi_cec" ,"aclk100" ,E4210_GATE_IP_PERIR ,11 ,0 ,0 ), -GATE (smmu_rotator,"smmu_rotator" ,"aclk200" , +GATE (CLK_HDMI_CEC ,"hdmi_cec" ,"aclk100" ,E4210_GATE_IP_PERIR ,11 ,0 , +0 ), +GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"aclk200" ,E4210_GATE_IP_IMAGE ,4 ,0 ,0 ), -GATE (sclk_mipi1,"sclk_mipi1" ,"div_mipi_pre1" , +GATE (CLK_SCLK_MIPI1 ,"sclk_mipi1" ,"div_mipi_pre1" ,E4210_SRC_MASK_LCD1 ,12 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_sata,"sclk_sata" ,"div_sata" , +GATE (CLK_SCLK_SATA ,"sclk_sata" ,"div_sata" ,SRC_MASK_FSYS ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mixer,"sclk_mixer" ,"mout_mixer" ,SRC_MASK_TV ,4 ,0 ,0 ), -GATE (sclk_dac,"sclk_dac" ,"mout_dac" ,SRC_MASK_TV ,8 ,0 ,0 ), -GATE_A (tsadc,"tsadc" ,"aclk100" ,GATE_IP_PERIL ,15 ,0 ,0 ,"adc" ), -GATE_A (mct,"mct" ,"aclk100" ,E4210_GATE_IP_PERIR ,13 ,0 ,0 ,"mct" ), -GATE_A (wdt,"watchdog" ,"aclk100" ,E4210_GATE_IP_PERIR ,14 ,0 ,0 ,"watchdog" ), -GATE_A (rtc,"rtc" ,"aclk100" ,E4210_GATE_IP_PERIR ,15 ,0 ,0 ,"rtc" ), -GATE_A (keyif,"keyif" ,"aclk100" ,E4210_GATE_IP_PERIR ,16 ,0 ,0 ,"keypad" ), -GATE_DA (sclk_fimd1,"exynos4-fb.1" ,"sclk_fimd1" ,"div_fimd1" , +GATE (CLK_SCLK_MIXER ,"sclk_mixer" ,"mout_mixer" ,SRC_MASK_TV ,4 ,0 ,0 ), +GATE (CLK_SCLK_DAC ,"sclk_dac" ,"mout_dac" ,SRC_MASK_TV ,8 ,0 ,0 ), +GATE_A (CLK_TSADC ,"tsadc" ,"aclk100" ,GATE_IP_PERIL ,15 ,0 ,0 ,"adc" ), +GATE_A (CLK_MCT ,"mct" ,"aclk100" ,E4210_GATE_IP_PERIR ,13 ,0 ,0 ,"mct" ), +GATE_A (CLK_WDT ,"watchdog" ,"aclk100" ,E4210_GATE_IP_PERIR ,14 ,0 ,0 , +"watchdog" ), +GATE_A (CLK_RTC ,"rtc" ,"aclk100" ,E4210_GATE_IP_PERIR ,15 ,0 ,0 ,"rtc" ), +GATE_A (CLK_KEYIF ,"keyif" ,"aclk100" ,E4210_GATE_IP_PERIR ,16 ,0 ,0 , +"keypad" ), +GATE_DA (CLK_SCLK_FIMD1 ,"exynos4-fb.1" ,"sclk_fimd1" ,"div_fimd1" ,E4210_SRC_MASK_LCD1 ,0 ,CLK_SET_RATE_PARENT ,0 ,"sclk_fimd" ), -GATE (tmu_apbif,"tmu_apbif" ,"aclk100" ,E4210_GATE_IP_PERIR ,17 ,0 ,0 ), +GATE (CLK_TMU_APBIF ,"tmu_apbif" ,"aclk100" ,E4210_GATE_IP_PERIR ,17 ,0 , +0 ), };/* list of gate clocks supported in exynos4x12 soc */ static struct samsung_gate_clock exynos4x12_gate_clks[]__initdata = { -GATE (audss,"audss" ,"sclk_epll" ,E4X12_GATE_IP_MAUDIO ,0 ,0 ,0 ), -GATE (mdnie0,"mdnie0" ,"aclk160" ,GATE_IP_LCD0 ,2 ,0 ,0 ), -GATE (rotator,"rotator" ,"aclk200" ,E4X12_GATE_IP_IMAGE ,1 ,0 ,0 ), -GATE (mdma2,"mdma2" ,"aclk200" ,E4X12_GATE_IP_IMAGE ,2 ,0 ,0 ), -GATE (smmu_mdma,"smmu_mdma" ,"aclk200" ,E4X12_GATE_IP_IMAGE ,5 ,0 ,0 ), -GATE (mipi_hsi,"mipi_hsi" ,"aclk133" ,GATE_IP_FSYS ,10 ,0 ,0 ), -GATE (chipid,"chipid" ,"aclk100" ,E4X12_GATE_IP_PERIR ,0 ,0 ,0 ), -GATE (sysreg,"sysreg" ,"aclk100" ,E4X12_GATE_IP_PERIR ,1 , +GATE (CLK_AUDSS ,"audss" ,"sclk_epll" ,E4X12_GATE_IP_MAUDIO ,0 ,0 ,0 ), +GATE (CLK_MDNIE0 ,"mdnie0" ,"aclk160" ,GATE_IP_LCD0 ,2 ,0 ,0 ), +GATE (CLK_ROTATOR ,"rotator" ,"aclk200" ,E4X12_GATE_IP_IMAGE ,1 ,0 ,0 ), +GATE (CLK_MDMA2 ,"mdma2" ,"aclk200" ,E4X12_GATE_IP_IMAGE ,2 ,0 ,0 ), +GATE (CLK_SMMU_MDMA ,"smmu_mdma" ,"aclk200" ,E4X12_GATE_IP_IMAGE ,5 ,0 , +0 ), +GATE (CLK_MIPI_HSI ,"mipi_hsi" ,"aclk133" ,GATE_IP_FSYS ,10 ,0 ,0 ), +GATE (CLK_CHIPID ,"chipid" ,"aclk100" ,E4X12_GATE_IP_PERIR ,0 ,0 ,0 ), +GATE (CLK_SYSREG ,"sysreg" ,"aclk100" ,E4X12_GATE_IP_PERIR ,1 ,CLK_IGNORE_UNUSED ,0 ), -GATE (hdmi_cec,"hdmi_cec" ,"aclk100" ,E4X12_GATE_IP_PERIR ,11 ,0 ,0 ), -GATE (sclk_mdnie0,"sclk_mdnie0" ,"div_mdnie0" , +GATE (CLK_HDMI_CEC ,"hdmi_cec" ,"aclk100" ,E4X12_GATE_IP_PERIR ,11 ,0 , +0 ), +GATE (CLK_SCLK_MDNIE0 ,"sclk_mdnie0" ,"div_mdnie0" ,SRC_MASK_LCD0 ,4 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mdnie_pwm0,"sclk_mdnie_pwm0" ,"div_mdnie_pwm_pre0" , +GATE (CLK_SCLK_MDNIE_PWM0 ,"sclk_mdnie_pwm0" ,"div_mdnie_pwm_pre0" ,SRC_MASK_LCD0 ,8 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mipihsi,"sclk_mipihsi" ,"div_mipihsi" , +GATE (CLK_SCLK_MIPIHSI ,"sclk_mipihsi" ,"div_mipihsi" ,SRC_MASK_FSYS ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (smmu_rotator,"smmu_rotator" ,"aclk200" , +GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"aclk200" ,E4X12_GATE_IP_IMAGE ,4 ,0 ,0 ), -GATE_A (mct,"mct" ,"aclk100" ,E4X12_GATE_IP_PERIR ,13 ,0 ,0 ,"mct" ), -GATE_A (rtc,"rtc" ,"aclk100" ,E4X12_GATE_IP_PERIR ,15 ,0 ,0 ,"rtc" ), -GATE_A (keyif,"keyif" ,"aclk100" , +GATE_A (CLK_MCT ,"mct" ,"aclk100" ,E4X12_GATE_IP_PERIR ,13 ,0 ,0 ,"mct" ), +GATE_A (CLK_RTC ,"rtc" ,"aclk100" ,E4X12_GATE_IP_PERIR ,15 ,0 ,0 ,"rtc" ), +GATE_A (CLK_KEYIF ,"keyif" ,"aclk100" ,E4X12_GATE_IP_PERIR ,16 ,0 ,0 ,"keypad" ), -GATE (sclk_pwm_isp,"sclk_pwm_isp" ,"div_pwm_isp" , +GATE (CLK_SCLK_PWM_ISP ,"sclk_pwm_isp" ,"div_pwm_isp" ,E4X12_SRC_MASK_ISP ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_spi0_isp,"sclk_spi0_isp" ,"div_spi0_isp_pre" , +GATE (CLK_SCLK_SPI0_ISP ,"sclk_spi0_isp" ,"div_spi0_isp_pre" ,E4X12_SRC_MASK_ISP ,4 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_spi1_isp,"sclk_spi1_isp" ,"div_spi1_isp_pre" , +GATE (CLK_SCLK_SPI1_ISP ,"sclk_spi1_isp" ,"div_spi1_isp_pre" ,E4X12_SRC_MASK_ISP ,8 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_uart_isp,"sclk_uart_isp" ,"div_uart_isp" , +GATE (CLK_SCLK_UART_ISP ,"sclk_uart_isp" ,"div_uart_isp" ,E4X12_SRC_MASK_ISP ,12 ,CLK_SET_RATE_PARENT ,0 ), -GATE (pwm_isp_sclk,"pwm_isp_sclk" ,"sclk_pwm_isp" , +GATE (CLK_PWM_ISP_SCLK ,"pwm_isp_sclk" ,"sclk_pwm_isp" ,E4X12_GATE_IP_ISP ,0 ,0 ,0 ), -GATE (spi0_isp_sclk,"spi0_isp_sclk" ,"sclk_spi0_isp" , +GATE (CLK_SPI0_ISP_SCLK ,"spi0_isp_sclk" ,"sclk_spi0_isp" ,E4X12_GATE_IP_ISP ,1 ,0 ,0 ), -GATE (spi1_isp_sclk,"spi1_isp_sclk" ,"sclk_spi1_isp" , +GATE (CLK_SPI1_ISP_SCLK ,"spi1_isp_sclk" ,"sclk_spi1_isp" ,E4X12_GATE_IP_ISP ,2 ,0 ,0 ), -GATE (uart_isp_sclk,"uart_isp_sclk" ,"sclk_uart_isp" , +GATE (CLK_UART_ISP_SCLK ,"uart_isp_sclk" ,"sclk_uart_isp" ,E4X12_GATE_IP_ISP ,3 ,0 ,0 ), -GATE_A (wdt,"watchdog" ,"aclk100" , +GATE_A (CLK_WDT ,"watchdog" ,"aclk100" ,E4X12_GATE_IP_PERIR ,14 ,0 ,0 ,"watchdog" ), -GATE_DA (pcm0,"samsung-pcm.0" ,"pcm0" ,"aclk100" , +GATE_DA (CLK_PCM0 ,"samsung-pcm.0" ,"pcm0" ,"aclk100" ,E4X12_GATE_IP_MAUDIO ,2 ,0 ,0 ,"pcm" ), -GATE_DA (i2s0,"samsung-i2s.0" ,"i2s0" ,"aclk100" , +GATE_DA (CLK_I2S0 ,"samsung-i2s.0" ,"i2s0" ,"aclk100" ,E4X12_GATE_IP_MAUDIO ,3 ,0 ,0 ,"iis" ), -GATE (fimc_isp,"isp" ,"aclk200" ,E4X12_GATE_ISP0 ,0 , +GATE (CLK_FIMC_ISP ,"isp" ,"aclk200" ,E4X12_GATE_ISP0 ,0 ,CLK_IGNORE_UNUSED ,0 ), -GATE (fimc_drc,"drc" ,"aclk200" ,E4X12_GATE_ISP0 ,1 , +GATE (CLK_FIMC_DRC ,"drc" ,"aclk200" ,E4X12_GATE_ISP0 ,1 ,CLK_IGNORE_UNUSED ,0 ), -GATE (fimc_fd,"fd" ,"aclk200" ,E4X12_GATE_ISP0 ,2 , +GATE (CLK_FIMC_FD ,"fd" ,"aclk200" ,E4X12_GATE_ISP0 ,2 ,CLK_IGNORE_UNUSED ,0 ), -GATE (fimc_lite0,"lite0" ,"aclk200" ,E4X12_GATE_ISP0 ,3 , +GATE (CLK_FIMC_LITE0 ,"lite0" ,"aclk200" ,E4X12_GATE_ISP0 ,3 ,CLK_IGNORE_UNUSED ,0 ), -GATE (fimc_lite1,"lite1" ,"aclk200" ,E4X12_GATE_ISP0 ,4 , +GATE (CLK_FIMC_LITE1 ,"lite1" ,"aclk200" ,E4X12_GATE_ISP0 ,4 ,CLK_IGNORE_UNUSED ,0 ), -GATE (mcuisp,"mcuisp" ,"aclk200" ,E4X12_GATE_ISP0 ,5 , +GATE (CLK_MCUISP ,"mcuisp" ,"aclk200" ,E4X12_GATE_ISP0 ,5 ,CLK_IGNORE_UNUSED ,0 ), -GATE (gicisp,"gicisp" ,"aclk200" ,E4X12_GATE_ISP0 ,7 , +GATE (CLK_GICISP ,"gicisp" ,"aclk200" ,E4X12_GATE_ISP0 ,7 ,CLK_IGNORE_UNUSED ,0 ), -GATE (smmu_isp,"smmu_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,8 , +GATE (CLK_SMMU_ISP ,"smmu_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,8 ,CLK_IGNORE_UNUSED ,0 ), -GATE (smmu_drc,"smmu_drc" ,"aclk200" ,E4X12_GATE_ISP0 ,9 , +GATE (CLK_SMMU_DRC ,"smmu_drc" ,"aclk200" ,E4X12_GATE_ISP0 ,9 ,CLK_IGNORE_UNUSED ,0 ), -GATE (smmu_fd,"smmu_fd" ,"aclk200" ,E4X12_GATE_ISP0 ,10 , +GATE (CLK_SMMU_FD ,"smmu_fd" ,"aclk200" ,E4X12_GATE_ISP0 ,10 ,CLK_IGNORE_UNUSED ,0 ), -GATE (smmu_lite0,"smmu_lite0" ,"aclk200" ,E4X12_GATE_ISP0 ,11 , +GATE (CLK_SMMU_LITE0 ,"smmu_lite0" ,"aclk200" ,E4X12_GATE_ISP0 ,11 ,CLK_IGNORE_UNUSED ,0 ), -GATE (smmu_lite1,"smmu_lite1" ,"aclk200" ,E4X12_GATE_ISP0 ,12 , +GATE (CLK_SMMU_LITE1 ,"smmu_lite1" ,"aclk200" ,E4X12_GATE_ISP0 ,12 ,CLK_IGNORE_UNUSED ,0 ), -GATE (ppmuispmx,"ppmuispmx" ,"aclk200" ,E4X12_GATE_ISP0 ,20 , +GATE (CLK_PPMUISPMX ,"ppmuispmx" ,"aclk200" ,E4X12_GATE_ISP0 ,20 ,CLK_IGNORE_UNUSED ,0 ), -GATE (ppmuispx,"ppmuispx" ,"aclk200" ,E4X12_GATE_ISP0 ,21 , +GATE (CLK_PPMUISPX ,"ppmuispx" ,"aclk200" ,E4X12_GATE_ISP0 ,21 ,CLK_IGNORE_UNUSED ,0 ), -GATE (mcuctl_isp,"mcuctl_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,23 , +GATE (CLK_MCUCTL_ISP ,"mcuctl_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,23 ,CLK_IGNORE_UNUSED ,0 ), -GATE (mpwm_isp,"mpwm_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,24 , +GATE (CLK_MPWM_ISP ,"mpwm_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,24 ,CLK_IGNORE_UNUSED ,0 ), -GATE (i2c0_isp,"i2c0_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,25 , +GATE (CLK_I2C0_ISP ,"i2c0_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,25 ,CLK_IGNORE_UNUSED ,0 ), -GATE (i2c1_isp,"i2c1_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,26 , +GATE (CLK_I2C1_ISP ,"i2c1_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,26 ,CLK_IGNORE_UNUSED ,0 ), -GATE (mtcadc_isp,"mtcadc_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,27 , +GATE (CLK_MTCADC_ISP ,"mtcadc_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,27 ,CLK_IGNORE_UNUSED ,0 ), -GATE (pwm_isp,"pwm_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,28 , +GATE (CLK_PWM_ISP ,"pwm_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,28 ,CLK_IGNORE_UNUSED ,0 ), -GATE (wdt_isp,"wdt_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,30 , +GATE (CLK_WDT_ISP ,"wdt_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,30 ,CLK_IGNORE_UNUSED ,0 ), -GATE (uart_isp,"uart_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,31 , +GATE (CLK_UART_ISP ,"uart_isp" ,"aclk200" ,E4X12_GATE_ISP0 ,31 ,CLK_IGNORE_UNUSED ,0 ), -GATE (asyncaxim,"asyncaxim" ,"aclk200" ,E4X12_GATE_ISP1 ,0 , +GATE (CLK_ASYNCAXIM ,"asyncaxim" ,"aclk200" ,E4X12_GATE_ISP1 ,0 ,CLK_IGNORE_UNUSED ,0 ), -GATE (smmu_ispcx,"smmu_ispcx" ,"aclk200" ,E4X12_GATE_ISP1 ,4 , +GATE (CLK_SMMU_ISPCX ,"smmu_ispcx" ,"aclk200" ,E4X12_GATE_ISP1 ,4 ,CLK_IGNORE_UNUSED ,0 ), -GATE (spi0_isp,"spi0_isp" ,"aclk200" ,E4X12_GATE_ISP1 ,12 , +GATE (CLK_SPI0_ISP ,"spi0_isp" ,"aclk200" ,E4X12_GATE_ISP1 ,12 ,CLK_IGNORE_UNUSED ,0 ), -GATE (spi1_isp,"spi1_isp" ,"aclk200" ,E4X12_GATE_ISP1 ,13 , +GATE (CLK_SPI1_ISP ,"spi1_isp" ,"aclk200" ,E4X12_GATE_ISP1 ,13 ,CLK_IGNORE_UNUSED ,0 ), -GATE (g2d,"g2d" ,"aclk200" ,GATE_IP_DMC ,23 ,0 ,0 ), -GATE (tmu_apbif,"tmu_apbif" ,"aclk100" ,E4X12_GATE_IP_PERIR ,17 ,0 ,0 ), +GATE (CLK_G2D ,"g2d" ,"aclk200" ,GATE_IP_DMC ,23 ,0 ,0 ), +GATE (CLK_TMU_APBIF ,"tmu_apbif" ,"aclk100" ,E4X12_GATE_IP_PERIR ,17 ,0 , +0 ), };/*
@@ -969,7 +924,7 @@ static void __init exynos4_clk_register_finpll(unsigned long xom) finpll_f =clk_get_rate (clk); } - fclk.id = fin_pll; + fclk.id =CLK_FIN_PLL ; fclk.name ="fin_pll" ; fclk.parent_name =NULL ; fclk.flags =CLK_IS_ROOT ;
@@ -985,14 +940,14 @@ static struct of_device_id ext_clk_match[] __initdata = { };static struct samsung_pll_clock exynos4_plls[nr_plls]__initdata = { - [apll] =PLL_A (pll_35xx, fout_apll,"fout_apll" ,"fin_pll" ,APLL_LOCK , -APLL_CON0 ,"fout_apll" ,NULL ), - [mpll] =PLL_A (pll_35xx, fout_mpll,"fout_mpll" ,"fin_pll" , + [apll] =PLL_A (pll_35xx,CLK_FOUT_APLL ,"fout_apll" ,"fin_pll" , +APLL_LOCK ,APLL_CON0 ,"fout_apll" ,NULL ), + [mpll] =PLL_A (pll_35xx,CLK_FOUT_MPLL ,"fout_mpll" ,"fin_pll" ,E4X12_MPLL_LOCK ,E4X12_MPLL_CON0 ,"fout_mpll" ,NULL ), - [epll] =PLL_A (pll_36xx, fout_epll,"fout_epll" ,"fin_pll" ,EPLL_LOCK , -EPLL_CON0 ,"fout_epll" ,NULL ), - [vpll] =PLL_A (pll_36xx, fout_vpll,"fout_vpll" ,"fin_pll" ,VPLL_LOCK , -VPLL_CON0 ,"fout_vpll" ,NULL ), + [epll] =PLL_A (pll_36xx,CLK_FOUT_EPLL ,"fout_epll" ,"fin_pll" , +EPLL_LOCK ,EPLL_CON0 ,"fout_epll" ,NULL ), + [vpll] =PLL_A (pll_36xx,CLK_FOUT_VPLL ,"fout_vpll" ,"fin_pll" , +VPLL_LOCK ,VPLL_CON0 ,"fout_vpll" ,NULL ), };/* register exynos4 clocks */
@@ -1009,11 +964,11 @@ static void __init exynos4_clk_init(struct device_node *np, }if (exynos4_soc ==EXYNOS4210 ) -samsung_clk_init (np, reg_base, nr_clks, +samsung_clk_init (np, reg_base,CLK_NR_CLKS , exynos4_clk_regs,ARRAY_SIZE (exynos4_clk_regs), exynos4210_clk_save,ARRAY_SIZE (exynos4210_clk_save));else -samsung_clk_init (np, reg_base, nr_clks, +samsung_clk_init (np, reg_base,CLK_NR_CLKS , exynos4_clk_regs,ARRAY_SIZE (exynos4_clk_regs), exynos4x12_clk_save,ARRAY_SIZE (exynos4x12_clk_save));
@@ -1034,10 +989,10 @@ static void __init exynos4_clk_init(struct device_node *np, vpll =samsung_clk_register_pll46xx ("fout_vpll" ,"mout_vpllsrc" , reg_base +VPLL_CON0 , pll_4650c); -samsung_clk_add_lookup (apll, fout_apll); -samsung_clk_add_lookup (mpll, fout_mpll); -samsung_clk_add_lookup (epll, fout_epll); -samsung_clk_add_lookup (vpll, fout_vpll); +samsung_clk_add_lookup (apll,CLK_FOUT_APLL ); +samsung_clk_add_lookup (mpll,CLK_FOUT_MPLL ); +samsung_clk_add_lookup (epll,CLK_FOUT_EPLL ); +samsung_clk_add_lookup (vpll,CLK_FOUT_VPLL ); }else {samsung_clk_register_pll (exynos4_plls,ARRAY_SIZE (exynos4_plls), reg_base);
Signature · 1 line
1.8.1.2
PATCH v2 4/12 ARM: exynos5250: create a DT header defining CLK IDs
In reply to Andrzej HajdaThe patch adds header file defining clock IDs.
This allows to use macros instead of magic numbers in DT bindings.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- include/dt-bindings/clock/exynos5250.h | 157 +++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 include/dt-bindings/clock/exynos5250.h
include/dt-bindings/clock/exynos5250.h new file +157 -0
@@ -0,0 +1,157 @@ +/* +* Copyright (c) 2013 Samsung Electronics Co., Ltd. +* Author: Andrzej Haja <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* Device Tree binding constants for Exynos5250 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H + +/* core clocks */ +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_MPLL 3 +#define CLK_FOUT_BPLL 4 +#define CLK_FOUT_GPLL 5 +#define CLK_FOUT_CPLL 6 +#define CLK_FOUT_EPLL 7 +#define CLK_FOUT_VPLL 8 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_CAM_BAYER 128 +#define CLK_SCLK_CAM0 129 +#define CLK_SCLK_CAM1 130 +#define CLK_SCLK_GSCL_WA 131 +#define CLK_SCLK_GSCL_WB 132 +#define CLK_SCLK_FIMD1 133 +#define CLK_SCLK_MIPI1 134 +#define CLK_SCLK_DP 135 +#define CLK_SCLK_HDMI 136 +#define CLK_SCLK_PIXEL 137 +#define CLK_SCLK_AUDIO0 138 +#define CLK_SCLK_MMC0 139 +#define CLK_SCLK_MMC1 140 +#define CLK_SCLK_MMC2 141 +#define CLK_SCLK_MMC3 142 +#define CLK_SCLK_SATA 143 +#define CLK_SCLK_USB3 144 +#define CLK_SCLK_JPEG 145 +#define CLK_SCLK_UART0 146 +#define CLK_SCLK_UART1 147 +#define CLK_SCLK_UART2 148 +#define CLK_SCLK_UART3 149 +#define CLK_SCLK_PWM 150 +#define CLK_SCLK_AUDIO1 151 +#define CLK_SCLK_AUDIO2 152 +#define CLK_SCLK_SPDIF 153 +#define CLK_SCLK_SPI0 154 +#define CLK_SCLK_SPI1 155 +#define CLK_SCLK_SPI2 156 +#define CLK_DIV_I2S1 157 +#define CLK_DIV_I2S2 158 +#define CLK_SCLK_HDMIPHY 159 + +/* gate clocks */ +#define CLK_GSCL0 256 +#define CLK_GSCL1 257 +#define CLK_GSCL2 258 +#define CLK_GSCL3 259 +#define CLK_GSCL_WA 260 +#define CLK_GSCL_WB 261 +#define CLK_SMMU_GSCL0 262 +#define CLK_SMMU_GSCL1 263 +#define CLK_SMMU_GSCL2 264 +#define CLK_SMMU_GSCL3 265 +#define CLK_MFC 266 +#define CLK_SMMU_MFCL 267 +#define CLK_SMMU_MFCR 268 +#define CLK_ROTATOR 269 +#define CLK_JPEG 270 +#define CLK_MDMA1 271 +#define CLK_SMMU_ROTATOR 272 +#define CLK_SMMU_JPEG 273 +#define CLK_SMMU_MDMA1 274 +#define CLK_PDMA0 275 +#define CLK_PDMA1 276 +#define CLK_SATA 277 +#define CLK_USBOTG 278 +#define CLK_MIPI_HSI 279 +#define CLK_SDMMC0 280 +#define CLK_SDMMC1 281 +#define CLK_SDMMC2 282 +#define CLK_SDMMC3 283 +#define CLK_SROMC 284 +#define CLK_USB2 285 +#define CLK_USB3 286 +#define CLK_SATA_PHYCTRL 287 +#define CLK_SATA_PHYI2C 288 +#define CLK_UART0 289 +#define CLK_UART1 290 +#define CLK_UART2 291 +#define CLK_UART3 292 +#define CLK_UART4 293 +#define CLK_I2C0 294 +#define CLK_I2C1 295 +#define CLK_I2C2 296 +#define CLK_I2C3 297 +#define CLK_I2C4 298 +#define CLK_I2C5 299 +#define CLK_I2C6 300 +#define CLK_I2C7 301 +#define CLK_I2C_HDMI 302 +#define CLK_ADC 303 +#define CLK_SPI0 304 +#define CLK_SPI1 305 +#define CLK_SPI2 306 +#define CLK_I2S1 307 +#define CLK_I2S2 308 +#define CLK_PCM1 309 +#define CLK_PCM2 310 +#define CLK_PWM 311 +#define CLK_SPDIF 312 +#define CLK_AC97 313 +#define CLK_HSI2C0 314 +#define CLK_HSI2C1 315 +#define CLK_HSI2C2 316 +#define CLK_HSI2C3 317 +#define CLK_CHIPID 318 +#define CLK_SYSREG 319 +#define CLK_PMU 320 +#define CLK_CMU_TOP 321 +#define CLK_CMU_CORE 322 +#define CLK_CMU_MEM 323 +#define CLK_TZPC0 324 +#define CLK_TZPC1 325 +#define CLK_TZPC2 326 +#define CLK_TZPC3 327 +#define CLK_TZPC4 328 +#define CLK_TZPC5 329 +#define CLK_TZPC6 330 +#define CLK_TZPC7 331 +#define CLK_TZPC8 332 +#define CLK_TZPC9 333 +#define CLK_HDMI_CEC 334 +#define CLK_MCT 335 +#define CLK_WDT 336 +#define CLK_RTC 337 +#define CLK_TMU 338 +#define CLK_FIMD1 339 +#define CLK_MIE1 340 +#define CLK_DSIM0 341 +#define CLK_DP 342 +#define CLK_MIXER 343 +#define CLK_HDMI 344 +#define CLK_G2D 345 + +/* mux clocks */ +#define CLK_MOUT_HDMI 1024 + +/* must be greater than maximal clock id */ +#define CLK_NR_CLKS 1025 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
Signature · 1 line
1.8.1.2
PATCH v2 5/12 ARM: dts: exynos5250: convert magic numbers to macros in clock bindings
In reply to Andrzej HajdaThe patch replaces magic numbers with macros defined in DT header in exynos5250 clock bindings.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- .../devicetree/bindings/clock/exynos5250-clock.txt | 160 +-------------------- arch/arm/boot/dts/exynos5250.dtsi | 92 ++++++------ 2 files changed, 53 insertions(+), 199 deletions(-)
Documentation/devicetree/bindings/clock/exynos5250-clock.txt +6 -154
@@ -13,160 +13,12 @@ Required Properties: - #clock-cells: should be 1. -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. - - - [Core Clocks] - - Clock ID - ---------------------------- - - fin_pll 1 - - [Clock Gate for Special Clocks] - - Clock ID - ---------------------------- - - sclk_cam_bayer 128 - sclk_cam0 129 - sclk_cam1 130 - sclk_gscl_wa 131 - sclk_gscl_wb 132 - sclk_fimd1 133 - sclk_mipi1 134 - sclk_dp 135 - sclk_hdmi 136 - sclk_pixel 137 - sclk_audio0 138 - sclk_mmc0 139 - sclk_mmc1 140 - sclk_mmc2 141 - sclk_mmc3 142 - sclk_sata 143 - sclk_usb3 144 - sclk_jpeg 145 - sclk_uart0 146 - sclk_uart1 147 - sclk_uart2 148 - sclk_uart3 149 - sclk_pwm 150 - sclk_audio1 151 - sclk_audio2 152 - sclk_spdif 153 - sclk_spi0 154 - sclk_spi1 155 - sclk_spi2 156 - div_i2s1 157 - div_i2s2 158 - sclk_hdmiphy 159 - - - [Peripheral Clock Gates] - - Clock ID - ---------------------------- - - gscl0 256 - gscl1 257 - gscl2 258 - gscl3 259 - gscl_wa 260 - gscl_wb 261 - smmu_gscl0 262 - smmu_gscl1 263 - smmu_gscl2 264 - smmu_gscl3 265 - mfc 266 - smmu_mfcl 267 - smmu_mfcr 268 - rotator 269 - jpeg 270 - mdma1 271 - smmu_rotator 272 - smmu_jpeg 273 - smmu_mdma1 274 - pdma0 275 - pdma1 276 - sata 277 - usbotg 278 - mipi_hsi 279 - sdmmc0 280 - sdmmc1 281 - sdmmc2 282 - sdmmc3 283 - sromc 284 - usb2 285 - usb3 286 - sata_phyctrl 287 - sata_phyi2c 288 - uart0 289 - uart1 290 - uart2 291 - uart3 292 - uart4 293 - i2c0 294 - i2c1 295 - i2c2 296 - i2c3 297 - i2c4 298 - i2c5 299 - i2c6 300 - i2c7 301 - i2c_hdmi 302 - adc 303 - spi0 304 - spi1 305 - spi2 306 - i2s1 307 - i2s2 308 - pcm1 309 - pcm2 310 - pwm 311 - spdif 312 - ac97 313 - hsi2c0 314 - hsi2c1 315 - hs12c2 316 - hs12c3 317 - chipid 318 - sysreg 319 - pmu 320 - cmu_top 321 - cmu_core 322 - cmu_mem 323 - tzpc0 324 - tzpc1 325 - tzpc2 326 - tzpc3 327 - tzpc4 328 - tzpc5 329 - tzpc6 330 - tzpc7 331 - tzpc8 332 - tzpc9 333 - hdmi_cec 334 - mct 335 - wdt 336 - rtc 337 - tmu 338 - fimd1 339 - mie1 340 - dsim0 341 - dp 342 - mixer 343 - hdmi 344 - g2d 345 - - - [Clock Muxes] - - Clock ID - ---------------------------- - mout_hdmi 1024 +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5250.h header and can be used in device +tree sources. Example 1: An example of a clock controller node is listed below.
@@ -184,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; interrupts = <0 54 0>; - clocks = <&clock 314>, <&clock 153>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; };
arch/arm/boot/dts/exynos5250.dtsi +47 -45
352 lines not on this page · raw message
Signature · 1 line
1.8.1.2
PATCH v2 6/12 clk: exynos5250: replace clock ID private enums with IDs from DT header
In reply to Andrzej HajdaThe patch replaces private enum clock IDs in the driver with macros provided by the DT header.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- drivers/clk/samsung/clk-exynos5250.c | 501 ++++++++++++++++------------------- 1 file changed, 229 insertions(+), 272 deletions(-)
drivers/clk/samsung/clk-exynos5250.c +229 -272
@@ -10,6 +10,7 @@* Common Clock Framework support for Exynos5250 SoC. */ +#include <dt-bindings/clock/exynos5250.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h>
@@ -84,51 +85,6 @@ enum exynos5250_plls { };/* -* Let each supported clock get a unique id. This id is used to lookup the clock -* for device tree based platforms. The clocks are categorized into three -* sections: core, sclk gate and bus interface gate clocks. -* -* When adding a new clock to this list, it is advised to choose a clock -* category and add it to the end of that category. That is because the the -* device tree source file is referring to these ids and any change in the -* sequence number of existing clocks will require corresponding change in the -* device tree files. This limitation would go away when pre-processor support -* for dtc would be available. -*/ -enum exynos5250_clks { - none, - -/* core clocks */ - fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll, - fout_epll, fout_vpll, - -/* gate for special clocks (sclk) */ - sclk_cam_bayer =128 , sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb, - sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0, - sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3, - sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm, - sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, - div_i2s1, div_i2s2, sclk_hdmiphy, - -/* gate clocks */ - gscl0 =256 , gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0, - smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator, - jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata, - usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3, - sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0, - i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1, - spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2, - hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1, - tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct, - wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, - -/* mux clocks */ - mout_hdmi =1024 , - - nr_clks, -}; - -/* * list of controller registers to be saved and restored during a * suspend/resume cycle. */
@@ -217,281 +173,282 @@ PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[]__initdata = { -FRATE (fin_pll,"fin_pll" ,NULL ,CLK_IS_ROOT ,0 ), +FRATE (CLK_FIN_PLL ,"fin_pll" ,NULL ,CLK_IS_ROOT ,0 ), };/* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[]__initdata = { -FRATE (sclk_hdmiphy,"sclk_hdmiphy" ,NULL ,CLK_IS_ROOT ,24000000 ), -FRATE (none,"sclk_hdmi27m" ,NULL ,CLK_IS_ROOT ,27000000 ), -FRATE (none,"sclk_dptxphy" ,NULL ,CLK_IS_ROOT ,24000000 ), -FRATE (none,"sclk_uhostphy" ,NULL ,CLK_IS_ROOT ,48000000 ), +FRATE (CLK_SCLK_HDMIPHY ,"sclk_hdmiphy" ,NULL ,CLK_IS_ROOT ,24000000 ), +FRATE (0 ,"sclk_hdmi27m" ,NULL ,CLK_IS_ROOT ,27000000 ), +FRATE (0 ,"sclk_dptxphy" ,NULL ,CLK_IS_ROOT ,24000000 ), +FRATE (0 ,"sclk_uhostphy" ,NULL ,CLK_IS_ROOT ,48000000 ), };static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[]__initdata = { -FFACTOR (none,"fout_mplldiv2" ,"fout_mpll" ,1 ,2 ,0 ), -FFACTOR (none,"fout_bplldiv2" ,"fout_bpll" ,1 ,2 ,0 ), +FFACTOR (0 ,"fout_mplldiv2" ,"fout_mpll" ,1 ,2 ,0 ), +FFACTOR (0 ,"fout_bplldiv2" ,"fout_bpll" ,1 ,2 ,0 ), };static struct samsung_mux_clock exynos5250_pll_pmux_clks[]__initdata = { -MUX (none,"mout_vpllsrc" , mout_vpllsrc_p,SRC_TOP2 ,0 ,1 ), +MUX (0 ,"mout_vpllsrc" , mout_vpllsrc_p,SRC_TOP2 ,0 ,1 ), };static struct samsung_mux_clock exynos5250_mux_clks[]__initdata = { -MUX_A (none,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 ,"mout_apll" ), -MUX_A (none,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ,"mout_cpu" ), -MUX (none,"mout_mpll_fout" , mout_mpll_fout_p,PLL_DIV2_SEL ,4 ,1 ), -MUX_A (none,"sclk_mpll" , mout_mpll_p,SRC_CORE1 ,8 ,1 ,"mout_mpll" ), -MUX (none,"mout_bpll_fout" , mout_bpll_fout_p,PLL_DIV2_SEL ,0 ,1 ), -MUX (none,"sclk_bpll" , mout_bpll_p,SRC_CDREX ,0 ,1 ), -MUX (none,"sclk_vpll" , mout_vpll_p,SRC_TOP2 ,16 ,1 ), -MUX (none,"sclk_epll" , mout_epll_p,SRC_TOP2 ,12 ,1 ), -MUX (none,"sclk_cpll" , mout_cpll_p,SRC_TOP2 ,8 ,1 ), -MUX (none,"sclk_mpll_user" , mout_mpll_user_p,SRC_TOP2 ,20 ,1 ), -MUX (none,"sclk_bpll_user" , mout_bpll_user_p,SRC_TOP2 ,24 ,1 ), -MUX (none,"mout_aclk166" , mout_aclk166_p,SRC_TOP0 ,8 ,1 ), -MUX (none,"mout_aclk333" , mout_aclk166_p,SRC_TOP0 ,16 ,1 ), -MUX (none,"mout_aclk200" , mout_aclk200_p,SRC_TOP0 ,12 ,1 ), -MUX (none,"mout_cam_bayer" , mout_group1_p,SRC_GSCL ,12 ,4 ), -MUX (none,"mout_cam0" , mout_group1_p,SRC_GSCL ,16 ,4 ), -MUX (none,"mout_cam1" , mout_group1_p,SRC_GSCL ,20 ,4 ), -MUX (none,"mout_gscl_wa" , mout_group1_p,SRC_GSCL ,24 ,4 ), -MUX (none,"mout_gscl_wb" , mout_group1_p,SRC_GSCL ,28 ,4 ), -MUX (none,"mout_fimd1" , mout_group1_p,SRC_DISP1_0 ,0 ,4 ), -MUX (none,"mout_mipi1" , mout_group1_p,SRC_DISP1_0 ,12 ,4 ), -MUX (none,"mout_dp" , mout_group1_p,SRC_DISP1_0 ,16 ,4 ), -MUX (mout_hdmi,"mout_hdmi" , mout_hdmi_p,SRC_DISP1_0 ,20 ,1 ), -MUX (none,"mout_audio0" , mout_audio0_p,SRC_MAU ,0 ,4 ), -MUX (none,"mout_mmc0" , mout_group1_p,SRC_FSYS ,0 ,4 ), -MUX (none,"mout_mmc1" , mout_group1_p,SRC_FSYS ,4 ,4 ), -MUX (none,"mout_mmc2" , mout_group1_p,SRC_FSYS ,8 ,4 ), -MUX (none,"mout_mmc3" , mout_group1_p,SRC_FSYS ,12 ,4 ), -MUX (none,"mout_sata" , mout_aclk200_p,SRC_FSYS ,24 ,1 ), -MUX (none,"mout_usb3" , mout_usb3_p,SRC_FSYS ,28 ,1 ), -MUX (none,"mout_jpeg" , mout_group1_p,SRC_GEN ,0 ,4 ), -MUX (none,"mout_uart0" , mout_group1_p,SRC_PERIC0 ,0 ,4 ), -MUX (none,"mout_uart1" , mout_group1_p,SRC_PERIC0 ,4 ,4 ), -MUX (none,"mout_uart2" , mout_group1_p,SRC_PERIC0 ,8 ,4 ), -MUX (none,"mout_uart3" , mout_group1_p,SRC_PERIC0 ,12 ,4 ), -MUX (none,"mout_pwm" , mout_group1_p,SRC_PERIC0 ,24 ,4 ), -MUX (none,"mout_audio1" , mout_audio1_p,SRC_PERIC1 ,0 ,4 ), -MUX (none,"mout_audio2" , mout_audio2_p,SRC_PERIC1 ,4 ,4 ), -MUX (none,"mout_spdif" , mout_spdif_p,SRC_PERIC1 ,8 ,2 ), -MUX (none,"mout_spi0" , mout_group1_p,SRC_PERIC1 ,16 ,4 ), -MUX (none,"mout_spi1" , mout_group1_p,SRC_PERIC1 ,20 ,4 ), -MUX (none,"mout_spi2" , mout_group1_p,SRC_PERIC1 ,24 ,4 ), +MUX_A (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 ,"mout_apll" ), +MUX_A (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ,"mout_cpu" ), +MUX (0 ,"mout_mpll_fout" , mout_mpll_fout_p,PLL_DIV2_SEL ,4 ,1 ), +MUX_A (0 ,"sclk_mpll" , mout_mpll_p,SRC_CORE1 ,8 ,1 ,"mout_mpll" ), +MUX (0 ,"mout_bpll_fout" , mout_bpll_fout_p,PLL_DIV2_SEL ,0 ,1 ), +MUX (0 ,"sclk_bpll" , mout_bpll_p,SRC_CDREX ,0 ,1 ), +MUX (0 ,"sclk_vpll" , mout_vpll_p,SRC_TOP2 ,16 ,1 ), +MUX (0 ,"sclk_epll" , mout_epll_p,SRC_TOP2 ,12 ,1 ), +MUX (0 ,"sclk_cpll" , mout_cpll_p,SRC_TOP2 ,8 ,1 ), +MUX (0 ,"sclk_mpll_user" , mout_mpll_user_p,SRC_TOP2 ,20 ,1 ), +MUX (0 ,"sclk_bpll_user" , mout_bpll_user_p,SRC_TOP2 ,24 ,1 ), +MUX (0 ,"mout_aclk166" , mout_aclk166_p,SRC_TOP0 ,8 ,1 ), +MUX (0 ,"mout_aclk333" , mout_aclk166_p,SRC_TOP0 ,16 ,1 ), +MUX (0 ,"mout_aclk200" , mout_aclk200_p,SRC_TOP0 ,12 ,1 ), +MUX (0 ,"mout_cam_bayer" , mout_group1_p,SRC_GSCL ,12 ,4 ), +MUX (0 ,"mout_cam0" , mout_group1_p,SRC_GSCL ,16 ,4 ), +MUX (0 ,"mout_cam1" , mout_group1_p,SRC_GSCL ,20 ,4 ), +MUX (0 ,"mout_gscl_wa" , mout_group1_p,SRC_GSCL ,24 ,4 ), +MUX (0 ,"mout_gscl_wb" , mout_group1_p,SRC_GSCL ,28 ,4 ), +MUX (0 ,"mout_fimd1" , mout_group1_p,SRC_DISP1_0 ,0 ,4 ), +MUX (0 ,"mout_mipi1" , mout_group1_p,SRC_DISP1_0 ,12 ,4 ), +MUX (0 ,"mout_dp" , mout_group1_p,SRC_DISP1_0 ,16 ,4 ), +MUX (CLK_MOUT_HDMI ,"mout_hdmi" , mout_hdmi_p,SRC_DISP1_0 ,20 ,1 ), +MUX (0 ,"mout_audio0" , mout_audio0_p,SRC_MAU ,0 ,4 ), +MUX (0 ,"mout_mmc0" , mout_group1_p,SRC_FSYS ,0 ,4 ), +MUX (0 ,"mout_mmc1" , mout_group1_p,SRC_FSYS ,4 ,4 ), +MUX (0 ,"mout_mmc2" , mout_group1_p,SRC_FSYS ,8 ,4 ), +MUX (0 ,"mout_mmc3" , mout_group1_p,SRC_FSYS ,12 ,4 ), +MUX (0 ,"mout_sata" , mout_aclk200_p,SRC_FSYS ,24 ,1 ), +MUX (0 ,"mout_usb3" , mout_usb3_p,SRC_FSYS ,28 ,1 ), +MUX (0 ,"mout_jpeg" , mout_group1_p,SRC_GEN ,0 ,4 ), +MUX (0 ,"mout_uart0" , mout_group1_p,SRC_PERIC0 ,0 ,4 ), +MUX (0 ,"mout_uart1" , mout_group1_p,SRC_PERIC0 ,4 ,4 ), +MUX (0 ,"mout_uart2" , mout_group1_p,SRC_PERIC0 ,8 ,4 ), +MUX (0 ,"mout_uart3" , mout_group1_p,SRC_PERIC0 ,12 ,4 ), +MUX (0 ,"mout_pwm" , mout_group1_p,SRC_PERIC0 ,24 ,4 ), +MUX (0 ,"mout_audio1" , mout_audio1_p,SRC_PERIC1 ,0 ,4 ), +MUX (0 ,"mout_audio2" , mout_audio2_p,SRC_PERIC1 ,4 ,4 ), +MUX (0 ,"mout_spdif" , mout_spdif_p,SRC_PERIC1 ,8 ,2 ), +MUX (0 ,"mout_spi0" , mout_group1_p,SRC_PERIC1 ,16 ,4 ), +MUX (0 ,"mout_spi1" , mout_group1_p,SRC_PERIC1 ,20 ,4 ), +MUX (0 ,"mout_spi2" , mout_group1_p,SRC_PERIC1 ,24 ,4 ), };static struct samsung_div_clock exynos5250_div_clks[]__initdata = { -DIV (none,"div_arm" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 ), -DIV (none,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 ), -DIV (none,"aclk66_pre" ,"sclk_mpll_user" ,DIV_TOP1 ,24 ,3 ), -DIV (none,"aclk66" ,"aclk66_pre" ,DIV_TOP0 ,0 ,3 ), -DIV (none,"aclk266" ,"sclk_mpll_user" ,DIV_TOP0 ,16 ,3 ), -DIV (none,"aclk166" ,"mout_aclk166" ,DIV_TOP0 ,8 ,3 ), -DIV (none,"aclk333" ,"mout_aclk333" ,DIV_TOP0 ,20 ,3 ), -DIV (none,"aclk200" ,"mout_aclk200" ,DIV_TOP0 ,12 ,3 ), -DIV (none,"div_cam_bayer" ,"mout_cam_bayer" ,DIV_GSCL ,12 ,4 ), -DIV (none,"div_cam0" ,"mout_cam0" ,DIV_GSCL ,16 ,4 ), -DIV (none,"div_cam1" ,"mout_cam1" ,DIV_GSCL ,20 ,4 ), -DIV (none,"div_gscl_wa" ,"mout_gscl_wa" ,DIV_GSCL ,24 ,4 ), -DIV (none,"div_gscl_wb" ,"mout_gscl_wb" ,DIV_GSCL ,28 ,4 ), -DIV (none,"div_fimd1" ,"mout_fimd1" ,DIV_DISP1_0 ,0 ,4 ), -DIV (none,"div_mipi1" ,"mout_mipi1" ,DIV_DISP1_0 ,16 ,4 ), -DIV (none,"div_dp" ,"mout_dp" ,DIV_DISP1_0 ,24 ,4 ), -DIV (none,"div_jpeg" ,"mout_jpeg" ,DIV_GEN ,4 ,4 ), -DIV (none,"div_audio0" ,"mout_audio0" ,DIV_MAU ,0 ,4 ), -DIV (none,"div_pcm0" ,"sclk_audio0" ,DIV_MAU ,4 ,8 ), -DIV (none,"div_sata" ,"mout_sata" ,DIV_FSYS0 ,20 ,4 ), -DIV (none,"div_usb3" ,"mout_usb3" ,DIV_FSYS0 ,24 ,4 ), -DIV (none,"div_mmc0" ,"mout_mmc0" ,DIV_FSYS1 ,0 ,4 ), -DIV (none,"div_mmc1" ,"mout_mmc1" ,DIV_FSYS1 ,16 ,4 ), -DIV (none,"div_mmc2" ,"mout_mmc2" ,DIV_FSYS2 ,0 ,4 ), -DIV (none,"div_mmc3" ,"mout_mmc3" ,DIV_FSYS2 ,16 ,4 ), -DIV (none,"div_uart0" ,"mout_uart0" ,DIV_PERIC0 ,0 ,4 ), -DIV (none,"div_uart1" ,"mout_uart1" ,DIV_PERIC0 ,4 ,4 ), -DIV (none,"div_uart2" ,"mout_uart2" ,DIV_PERIC0 ,8 ,4 ), -DIV (none,"div_uart3" ,"mout_uart3" ,DIV_PERIC0 ,12 ,4 ), -DIV (none,"div_spi0" ,"mout_spi0" ,DIV_PERIC1 ,0 ,4 ), -DIV (none,"div_spi1" ,"mout_spi1" ,DIV_PERIC1 ,16 ,4 ), -DIV (none,"div_spi2" ,"mout_spi2" ,DIV_PERIC2 ,0 ,4 ), -DIV (none,"div_pwm" ,"mout_pwm" ,DIV_PERIC3 ,0 ,4 ), -DIV (none,"div_audio1" ,"mout_audio1" ,DIV_PERIC4 ,0 ,4 ), -DIV (none,"div_pcm1" ,"sclk_audio1" ,DIV_PERIC4 ,4 ,8 ), -DIV (none,"div_audio2" ,"mout_audio2" ,DIV_PERIC4 ,16 ,4 ), -DIV (none,"div_pcm2" ,"sclk_audio2" ,DIV_PERIC4 ,20 ,8 ), -DIV (div_i2s1,"div_i2s1" ,"sclk_audio1" ,DIV_PERIC5 ,0 ,6 ), -DIV (div_i2s2,"div_i2s2" ,"sclk_audio2" ,DIV_PERIC5 ,8 ,6 ), -DIV (sclk_pixel,"div_hdmi_pixel" ,"sclk_vpll" ,DIV_DISP1_0 ,28 ,4 ), -DIV_A (none,"armclk" ,"div_arm" ,DIV_CPU0 ,28 ,3 ,"armclk" ), -DIV_F (none,"div_mipi1_pre" ,"div_mipi1" , +DIV (0 ,"div_arm" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 ), +DIV (0 ,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 ), +DIV (0 ,"aclk66_pre" ,"sclk_mpll_user" ,DIV_TOP1 ,24 ,3 ), +DIV (0 ,"aclk66" ,"aclk66_pre" ,DIV_TOP0 ,0 ,3 ), +DIV (0 ,"aclk266" ,"sclk_mpll_user" ,DIV_TOP0 ,16 ,3 ), +DIV (0 ,"aclk166" ,"mout_aclk166" ,DIV_TOP0 ,8 ,3 ), +DIV (0 ,"aclk333" ,"mout_aclk333" ,DIV_TOP0 ,20 ,3 ), +DIV (0 ,"aclk200" ,"mout_aclk200" ,DIV_TOP0 ,12 ,3 ), +DIV (0 ,"div_cam_bayer" ,"mout_cam_bayer" ,DIV_GSCL ,12 ,4 ), +DIV (0 ,"div_cam0" ,"mout_cam0" ,DIV_GSCL ,16 ,4 ), +DIV (0 ,"div_cam1" ,"mout_cam1" ,DIV_GSCL ,20 ,4 ), +DIV (0 ,"div_gscl_wa" ,"mout_gscl_wa" ,DIV_GSCL ,24 ,4 ), +DIV (0 ,"div_gscl_wb" ,"mout_gscl_wb" ,DIV_GSCL ,28 ,4 ), +DIV (0 ,"div_fimd1" ,"mout_fimd1" ,DIV_DISP1_0 ,0 ,4 ), +DIV (0 ,"div_mipi1" ,"mout_mipi1" ,DIV_DISP1_0 ,16 ,4 ), +DIV (0 ,"div_dp" ,"mout_dp" ,DIV_DISP1_0 ,24 ,4 ), +DIV (0 ,"div_jpeg" ,"mout_jpeg" ,DIV_GEN ,4 ,4 ), +DIV (0 ,"div_audio0" ,"mout_audio0" ,DIV_MAU ,0 ,4 ), +DIV (0 ,"div_pcm0" ,"sclk_audio0" ,DIV_MAU ,4 ,8 ), +DIV (0 ,"div_sata" ,"mout_sata" ,DIV_FSYS0 ,20 ,4 ), +DIV (0 ,"div_usb3" ,"mout_usb3" ,DIV_FSYS0 ,24 ,4 ), +DIV (0 ,"div_mmc0" ,"mout_mmc0" ,DIV_FSYS1 ,0 ,4 ), +DIV (0 ,"div_mmc1" ,"mout_mmc1" ,DIV_FSYS1 ,16 ,4 ), +DIV (0 ,"div_mmc2" ,"mout_mmc2" ,DIV_FSYS2 ,0 ,4 ), +DIV (0 ,"div_mmc3" ,"mout_mmc3" ,DIV_FSYS2 ,16 ,4 ), +DIV (0 ,"div_uart0" ,"mout_uart0" ,DIV_PERIC0 ,0 ,4 ), +DIV (0 ,"div_uart1" ,"mout_uart1" ,DIV_PERIC0 ,4 ,4 ), +DIV (0 ,"div_uart2" ,"mout_uart2" ,DIV_PERIC0 ,8 ,4 ), +DIV (0 ,"div_uart3" ,"mout_uart3" ,DIV_PERIC0 ,12 ,4 ), +DIV (0 ,"div_spi0" ,"mout_spi0" ,DIV_PERIC1 ,0 ,4 ), +DIV (0 ,"div_spi1" ,"mout_spi1" ,DIV_PERIC1 ,16 ,4 ), +DIV (0 ,"div_spi2" ,"mout_spi2" ,DIV_PERIC2 ,0 ,4 ), +DIV (0 ,"div_pwm" ,"mout_pwm" ,DIV_PERIC3 ,0 ,4 ), +DIV (0 ,"div_audio1" ,"mout_audio1" ,DIV_PERIC4 ,0 ,4 ), +DIV (0 ,"div_pcm1" ,"sclk_audio1" ,DIV_PERIC4 ,4 ,8 ), +DIV (0 ,"div_audio2" ,"mout_audio2" ,DIV_PERIC4 ,16 ,4 ), +DIV (0 ,"div_pcm2" ,"sclk_audio2" ,DIV_PERIC4 ,20 ,8 ), +DIV (CLK_DIV_I2S1 ,"div_i2s1" ,"sclk_audio1" ,DIV_PERIC5 ,0 ,6 ), +DIV (CLK_DIV_I2S2 ,"div_i2s2" ,"sclk_audio2" ,DIV_PERIC5 ,8 ,6 ), +DIV (CLK_SCLK_PIXEL ,"div_hdmi_pixel" ,"sclk_vpll" ,DIV_DISP1_0 ,28 ,4 ), +DIV_A (0 ,"armclk" ,"div_arm" ,DIV_CPU0 ,28 ,3 ,"armclk" ), +DIV_F (0 ,"div_mipi1_pre" ,"div_mipi1" ,DIV_DISP1_0 ,20 ,4 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_mmc_pre0" ,"div_mmc0" , +DIV_F (0 ,"div_mmc_pre0" ,"div_mmc0" ,DIV_FSYS1 ,8 ,8 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_mmc_pre1" ,"div_mmc1" , +DIV_F (0 ,"div_mmc_pre1" ,"div_mmc1" ,DIV_FSYS1 ,24 ,8 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_mmc_pre2" ,"div_mmc2" , +DIV_F (0 ,"div_mmc_pre2" ,"div_mmc2" ,DIV_FSYS2 ,8 ,8 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_mmc_pre3" ,"div_mmc3" , +DIV_F (0 ,"div_mmc_pre3" ,"div_mmc3" ,DIV_FSYS2 ,24 ,8 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_spi_pre0" ,"div_spi0" , +DIV_F (0 ,"div_spi_pre0" ,"div_spi0" ,DIV_PERIC1 ,8 ,8 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_spi_pre1" ,"div_spi1" , +DIV_F (0 ,"div_spi_pre1" ,"div_spi1" ,DIV_PERIC1 ,24 ,8 ,CLK_SET_RATE_PARENT ,0 ), -DIV_F (none,"div_spi_pre2" ,"div_spi2" , +DIV_F (0 ,"div_spi_pre2" ,"div_spi2" ,DIV_PERIC2 ,8 ,8 ,CLK_SET_RATE_PARENT ,0 ), };static struct samsung_gate_clock exynos5250_gate_clks[]__initdata = { -GATE (gscl0,"gscl0" ,"none" ,GATE_IP_GSCL ,0 ,0 ,0 ), -GATE (gscl1,"gscl1" ,"none" ,GATE_IP_GSCL ,1 ,0 ,0 ), -GATE (gscl2,"gscl2" ,"aclk266" ,GATE_IP_GSCL ,2 ,0 ,0 ), -GATE (gscl3,"gscl3" ,"aclk266" ,GATE_IP_GSCL ,3 ,0 ,0 ), -GATE (gscl_wa,"gscl_wa" ,"div_gscl_wa" ,GATE_IP_GSCL ,5 ,0 ,0 ), -GATE (gscl_wb,"gscl_wb" ,"div_gscl_wb" ,GATE_IP_GSCL ,6 ,0 ,0 ), -GATE (smmu_gscl0,"smmu_gscl0" ,"aclk266" ,GATE_IP_GSCL ,7 ,0 ,0 ), -GATE (smmu_gscl1,"smmu_gscl1" ,"aclk266" ,GATE_IP_GSCL ,8 ,0 ,0 ), -GATE (smmu_gscl2,"smmu_gscl2" ,"aclk266" ,GATE_IP_GSCL ,9 ,0 ,0 ), -GATE (smmu_gscl3,"smmu_gscl3" ,"aclk266" ,GATE_IP_GSCL ,10 ,0 ,0 ), -GATE (mfc,"mfc" ,"aclk333" ,GATE_IP_MFC ,0 ,0 ,0 ), -GATE (smmu_mfcl,"smmu_mfcl" ,"aclk333" ,GATE_IP_MFC ,1 ,0 ,0 ), -GATE (smmu_mfcr,"smmu_mfcr" ,"aclk333" ,GATE_IP_MFC ,2 ,0 ,0 ), -GATE (rotator,"rotator" ,"aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ), -GATE (jpeg,"jpeg" ,"aclk166" ,GATE_IP_GEN ,2 ,0 ,0 ), -GATE (mdma1,"mdma1" ,"aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ), -GATE (smmu_rotator,"smmu_rotator" ,"aclk266" ,GATE_IP_GEN ,6 ,0 ,0 ), -GATE (smmu_jpeg,"smmu_jpeg" ,"aclk166" ,GATE_IP_GEN ,7 ,0 ,0 ), -GATE (smmu_mdma1,"smmu_mdma1" ,"aclk266" ,GATE_IP_GEN ,9 ,0 ,0 ), -GATE (pdma0,"pdma0" ,"aclk200" ,GATE_IP_FSYS ,1 ,0 ,0 ), -GATE (pdma1,"pdma1" ,"aclk200" ,GATE_IP_FSYS ,2 ,0 ,0 ), -GATE (sata,"sata" ,"aclk200" ,GATE_IP_FSYS ,6 ,0 ,0 ), -GATE (usbotg,"usbotg" ,"aclk200" ,GATE_IP_FSYS ,7 ,0 ,0 ), -GATE (mipi_hsi,"mipi_hsi" ,"aclk200" ,GATE_IP_FSYS ,8 ,0 ,0 ), -GATE (sdmmc0,"sdmmc0" ,"aclk200" ,GATE_IP_FSYS ,12 ,0 ,0 ), -GATE (sdmmc1,"sdmmc1" ,"aclk200" ,GATE_IP_FSYS ,13 ,0 ,0 ), -GATE (sdmmc2,"sdmmc2" ,"aclk200" ,GATE_IP_FSYS ,14 ,0 ,0 ), -GATE (sdmmc3,"sdmmc3" ,"aclk200" ,GATE_IP_FSYS ,15 ,0 ,0 ), -GATE (sromc,"sromc" ,"aclk200" ,GATE_IP_FSYS ,17 ,0 ,0 ), -GATE (usb2,"usb2" ,"aclk200" ,GATE_IP_FSYS ,18 ,0 ,0 ), -GATE (usb3,"usb3" ,"aclk200" ,GATE_IP_FSYS ,19 ,0 ,0 ), -GATE (sata_phyctrl,"sata_phyctrl" ,"aclk200" ,GATE_IP_FSYS ,24 ,0 ,0 ), -GATE (sata_phyi2c,"sata_phyi2c" ,"aclk200" ,GATE_IP_FSYS ,25 ,0 ,0 ), -GATE (uart0,"uart0" ,"aclk66" ,GATE_IP_PERIC ,0 ,0 ,0 ), -GATE (uart1,"uart1" ,"aclk66" ,GATE_IP_PERIC ,1 ,0 ,0 ), -GATE (uart2,"uart2" ,"aclk66" ,GATE_IP_PERIC ,2 ,0 ,0 ), -GATE (uart3,"uart3" ,"aclk66" ,GATE_IP_PERIC ,3 ,0 ,0 ), -GATE (uart4,"uart4" ,"aclk66" ,GATE_IP_PERIC ,4 ,0 ,0 ), -GATE (i2c0,"i2c0" ,"aclk66" ,GATE_IP_PERIC ,6 ,0 ,0 ), -GATE (i2c1,"i2c1" ,"aclk66" ,GATE_IP_PERIC ,7 ,0 ,0 ), -GATE (i2c2,"i2c2" ,"aclk66" ,GATE_IP_PERIC ,8 ,0 ,0 ), -GATE (i2c3,"i2c3" ,"aclk66" ,GATE_IP_PERIC ,9 ,0 ,0 ), -GATE (i2c4,"i2c4" ,"aclk66" ,GATE_IP_PERIC ,10 ,0 ,0 ), -GATE (i2c5,"i2c5" ,"aclk66" ,GATE_IP_PERIC ,11 ,0 ,0 ), -GATE (i2c6,"i2c6" ,"aclk66" ,GATE_IP_PERIC ,12 ,0 ,0 ), -GATE (i2c7,"i2c7" ,"aclk66" ,GATE_IP_PERIC ,13 ,0 ,0 ), -GATE (i2c_hdmi,"i2c_hdmi" ,"aclk66" ,GATE_IP_PERIC ,14 ,0 ,0 ), -GATE (adc,"adc" ,"aclk66" ,GATE_IP_PERIC ,15 ,0 ,0 ), -GATE (spi0,"spi0" ,"aclk66" ,GATE_IP_PERIC ,16 ,0 ,0 ), -GATE (spi1,"spi1" ,"aclk66" ,GATE_IP_PERIC ,17 ,0 ,0 ), -GATE (spi2,"spi2" ,"aclk66" ,GATE_IP_PERIC ,18 ,0 ,0 ), -GATE (i2s1,"i2s1" ,"aclk66" ,GATE_IP_PERIC ,20 ,0 ,0 ), -GATE (i2s2,"i2s2" ,"aclk66" ,GATE_IP_PERIC ,21 ,0 ,0 ), -GATE (pcm1,"pcm1" ,"aclk66" ,GATE_IP_PERIC ,22 ,0 ,0 ), -GATE (pcm2,"pcm2" ,"aclk66" ,GATE_IP_PERIC ,23 ,0 ,0 ), -GATE (pwm,"pwm" ,"aclk66" ,GATE_IP_PERIC ,24 ,0 ,0 ), -GATE (spdif,"spdif" ,"aclk66" ,GATE_IP_PERIC ,26 ,0 ,0 ), -GATE (ac97,"ac97" ,"aclk66" ,GATE_IP_PERIC ,27 ,0 ,0 ), -GATE (hsi2c0,"hsi2c0" ,"aclk66" ,GATE_IP_PERIC ,28 ,0 ,0 ), -GATE (hsi2c1,"hsi2c1" ,"aclk66" ,GATE_IP_PERIC ,29 ,0 ,0 ), -GATE (hsi2c2,"hsi2c2" ,"aclk66" ,GATE_IP_PERIC ,30 ,0 ,0 ), -GATE (hsi2c3,"hsi2c3" ,"aclk66" ,GATE_IP_PERIC ,31 ,0 ,0 ), -GATE (chipid,"chipid" ,"aclk66" ,GATE_IP_PERIS ,0 ,0 ,0 ), -GATE (sysreg,"sysreg" ,"aclk66" ,GATE_IP_PERIS ,1 ,0 ,0 ), -GATE (pmu,"pmu" ,"aclk66" ,GATE_IP_PERIS ,2 ,CLK_IGNORE_UNUSED ,0 ), -GATE (tzpc0,"tzpc0" ,"aclk66" ,GATE_IP_PERIS ,6 ,0 ,0 ), -GATE (tzpc1,"tzpc1" ,"aclk66" ,GATE_IP_PERIS ,7 ,0 ,0 ), -GATE (tzpc2,"tzpc2" ,"aclk66" ,GATE_IP_PERIS ,8 ,0 ,0 ), -GATE (tzpc3,"tzpc3" ,"aclk66" ,GATE_IP_PERIS ,9 ,0 ,0 ), -GATE (tzpc4,"tzpc4" ,"aclk66" ,GATE_IP_PERIS ,10 ,0 ,0 ), -GATE (tzpc5,"tzpc5" ,"aclk66" ,GATE_IP_PERIS ,11 ,0 ,0 ), -GATE (tzpc6,"tzpc6" ,"aclk66" ,GATE_IP_PERIS ,12 ,0 ,0 ), -GATE (tzpc7,"tzpc7" ,"aclk66" ,GATE_IP_PERIS ,13 ,0 ,0 ), -GATE (tzpc8,"tzpc8" ,"aclk66" ,GATE_IP_PERIS ,14 ,0 ,0 ), -GATE (tzpc9,"tzpc9" ,"aclk66" ,GATE_IP_PERIS ,15 ,0 ,0 ), -GATE (hdmi_cec,"hdmi_cec" ,"aclk66" ,GATE_IP_PERIS ,16 ,0 ,0 ), -GATE (mct,"mct" ,"aclk66" ,GATE_IP_PERIS ,18 ,0 ,0 ), -GATE (wdt,"wdt" ,"aclk66" ,GATE_IP_PERIS ,19 ,0 ,0 ), -GATE (rtc,"rtc" ,"aclk66" ,GATE_IP_PERIS ,20 ,0 ,0 ), -GATE (tmu,"tmu" ,"aclk66" ,GATE_IP_PERIS ,21 ,0 ,0 ), -GATE (cmu_top,"cmu_top" ,"aclk66" , +GATE (CLK_GSCL0 ,"gscl0" ,"none" ,GATE_IP_GSCL ,0 ,0 ,0 ), +GATE (CLK_GSCL1 ,"gscl1" ,"none" ,GATE_IP_GSCL ,1 ,0 ,0 ), +GATE (CLK_GSCL2 ,"gscl2" ,"aclk266" ,GATE_IP_GSCL ,2 ,0 ,0 ), +GATE (CLK_GSCL3 ,"gscl3" ,"aclk266" ,GATE_IP_GSCL ,3 ,0 ,0 ), +GATE (CLK_GSCL_WA ,"gscl_wa" ,"div_gscl_wa" ,GATE_IP_GSCL ,5 ,0 ,0 ), +GATE (CLK_GSCL_WB ,"gscl_wb" ,"div_gscl_wb" ,GATE_IP_GSCL ,6 ,0 ,0 ), +GATE (CLK_SMMU_GSCL0 ,"smmu_gscl0" ,"aclk266" ,GATE_IP_GSCL ,7 ,0 ,0 ), +GATE (CLK_SMMU_GSCL1 ,"smmu_gscl1" ,"aclk266" ,GATE_IP_GSCL ,8 ,0 ,0 ), +GATE (CLK_SMMU_GSCL2 ,"smmu_gscl2" ,"aclk266" ,GATE_IP_GSCL ,9 ,0 ,0 ), +GATE (CLK_SMMU_GSCL3 ,"smmu_gscl3" ,"aclk266" ,GATE_IP_GSCL ,10 ,0 ,0 ), +GATE (CLK_MFC ,"mfc" ,"aclk333" ,GATE_IP_MFC ,0 ,0 ,0 ), +GATE (CLK_SMMU_MFCL ,"smmu_mfcl" ,"aclk333" ,GATE_IP_MFC ,1 ,0 ,0 ), +GATE (CLK_SMMU_MFCR ,"smmu_mfcr" ,"aclk333" ,GATE_IP_MFC ,2 ,0 ,0 ), +GATE (CLK_ROTATOR ,"rotator" ,"aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ), +GATE (CLK_JPEG ,"jpeg" ,"aclk166" ,GATE_IP_GEN ,2 ,0 ,0 ), +GATE (CLK_MDMA1 ,"mdma1" ,"aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ), +GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"aclk266" ,GATE_IP_GEN ,6 ,0 ,0 ), +GATE (CLK_SMMU_JPEG ,"smmu_jpeg" ,"aclk166" ,GATE_IP_GEN ,7 ,0 ,0 ), +GATE (CLK_SMMU_MDMA1 ,"smmu_mdma1" ,"aclk266" ,GATE_IP_GEN ,9 ,0 ,0 ), +GATE (CLK_PDMA0 ,"pdma0" ,"aclk200" ,GATE_IP_FSYS ,1 ,0 ,0 ), +GATE (CLK_PDMA1 ,"pdma1" ,"aclk200" ,GATE_IP_FSYS ,2 ,0 ,0 ), +GATE (CLK_SATA ,"sata" ,"aclk200" ,GATE_IP_FSYS ,6 ,0 ,0 ), +GATE (CLK_USBOTG ,"usbotg" ,"aclk200" ,GATE_IP_FSYS ,7 ,0 ,0 ), +GATE (CLK_MIPI_HSI ,"mipi_hsi" ,"aclk200" ,GATE_IP_FSYS ,8 ,0 ,0 ), +GATE (CLK_SDMMC0 ,"sdmmc0" ,"aclk200" ,GATE_IP_FSYS ,12 ,0 ,0 ), +GATE (CLK_SDMMC1 ,"sdmmc1" ,"aclk200" ,GATE_IP_FSYS ,13 ,0 ,0 ), +GATE (CLK_SDMMC2 ,"sdmmc2" ,"aclk200" ,GATE_IP_FSYS ,14 ,0 ,0 ), +GATE (CLK_SDMMC3 ,"sdmmc3" ,"aclk200" ,GATE_IP_FSYS ,15 ,0 ,0 ), +GATE (CLK_SROMC ,"sromc" ,"aclk200" ,GATE_IP_FSYS ,17 ,0 ,0 ), +GATE (CLK_USB2 ,"usb2" ,"aclk200" ,GATE_IP_FSYS ,18 ,0 ,0 ), +GATE (CLK_USB3 ,"usb3" ,"aclk200" ,GATE_IP_FSYS ,19 ,0 ,0 ), +GATE (CLK_SATA_PHYCTRL ,"sata_phyctrl" ,"aclk200" ,GATE_IP_FSYS ,24 ,0 , +0 ), +GATE (CLK_SATA_PHYI2C ,"sata_phyi2c" ,"aclk200" ,GATE_IP_FSYS ,25 ,0 ,0 ), +GATE (CLK_UART0 ,"uart0" ,"aclk66" ,GATE_IP_PERIC ,0 ,0 ,0 ), +GATE (CLK_UART1 ,"uart1" ,"aclk66" ,GATE_IP_PERIC ,1 ,0 ,0 ), +GATE (CLK_UART2 ,"uart2" ,"aclk66" ,GATE_IP_PERIC ,2 ,0 ,0 ), +GATE (CLK_UART3 ,"uart3" ,"aclk66" ,GATE_IP_PERIC ,3 ,0 ,0 ), +GATE (CLK_UART4 ,"uart4" ,"aclk66" ,GATE_IP_PERIC ,4 ,0 ,0 ), +GATE (CLK_I2C0 ,"i2c0" ,"aclk66" ,GATE_IP_PERIC ,6 ,0 ,0 ), +GATE (CLK_I2C1 ,"i2c1" ,"aclk66" ,GATE_IP_PERIC ,7 ,0 ,0 ), +GATE (CLK_I2C2 ,"i2c2" ,"aclk66" ,GATE_IP_PERIC ,8 ,0 ,0 ), +GATE (CLK_I2C3 ,"i2c3" ,"aclk66" ,GATE_IP_PERIC ,9 ,0 ,0 ), +GATE (CLK_I2C4 ,"i2c4" ,"aclk66" ,GATE_IP_PERIC ,10 ,0 ,0 ), +GATE (CLK_I2C5 ,"i2c5" ,"aclk66" ,GATE_IP_PERIC ,11 ,0 ,0 ), +GATE (CLK_I2C6 ,"i2c6" ,"aclk66" ,GATE_IP_PERIC ,12 ,0 ,0 ), +GATE (CLK_I2C7 ,"i2c7" ,"aclk66" ,GATE_IP_PERIC ,13 ,0 ,0 ), +GATE (CLK_I2C_HDMI ,"i2c_hdmi" ,"aclk66" ,GATE_IP_PERIC ,14 ,0 ,0 ), +GATE (CLK_ADC ,"adc" ,"aclk66" ,GATE_IP_PERIC ,15 ,0 ,0 ), +GATE (CLK_SPI0 ,"spi0" ,"aclk66" ,GATE_IP_PERIC ,16 ,0 ,0 ), +GATE (CLK_SPI1 ,"spi1" ,"aclk66" ,GATE_IP_PERIC ,17 ,0 ,0 ), +GATE (CLK_SPI2 ,"spi2" ,"aclk66" ,GATE_IP_PERIC ,18 ,0 ,0 ), +GATE (CLK_I2S1 ,"i2s1" ,"aclk66" ,GATE_IP_PERIC ,20 ,0 ,0 ), +GATE (CLK_I2S2 ,"i2s2" ,"aclk66" ,GATE_IP_PERIC ,21 ,0 ,0 ), +GATE (CLK_PCM1 ,"pcm1" ,"aclk66" ,GATE_IP_PERIC ,22 ,0 ,0 ), +GATE (CLK_PCM2 ,"pcm2" ,"aclk66" ,GATE_IP_PERIC ,23 ,0 ,0 ), +GATE (CLK_PWM ,"pwm" ,"aclk66" ,GATE_IP_PERIC ,24 ,0 ,0 ), +GATE (CLK_SPDIF ,"spdif" ,"aclk66" ,GATE_IP_PERIC ,26 ,0 ,0 ), +GATE (CLK_AC97 ,"ac97" ,"aclk66" ,GATE_IP_PERIC ,27 ,0 ,0 ), +GATE (CLK_HSI2C0 ,"hsi2c0" ,"aclk66" ,GATE_IP_PERIC ,28 ,0 ,0 ), +GATE (CLK_HSI2C1 ,"hsi2c1" ,"aclk66" ,GATE_IP_PERIC ,29 ,0 ,0 ), +GATE (CLK_HSI2C2 ,"hsi2c2" ,"aclk66" ,GATE_IP_PERIC ,30 ,0 ,0 ), +GATE (CLK_HSI2C3 ,"hsi2c3" ,"aclk66" ,GATE_IP_PERIC ,31 ,0 ,0 ), +GATE (CLK_CHIPID ,"chipid" ,"aclk66" ,GATE_IP_PERIS ,0 ,0 ,0 ), +GATE (CLK_SYSREG ,"sysreg" ,"aclk66" ,GATE_IP_PERIS ,1 ,0 ,0 ), +GATE (CLK_PMU ,"pmu" ,"aclk66" ,GATE_IP_PERIS ,2 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_TZPC0 ,"tzpc0" ,"aclk66" ,GATE_IP_PERIS ,6 ,0 ,0 ), +GATE (CLK_TZPC1 ,"tzpc1" ,"aclk66" ,GATE_IP_PERIS ,7 ,0 ,0 ), +GATE (CLK_TZPC2 ,"tzpc2" ,"aclk66" ,GATE_IP_PERIS ,8 ,0 ,0 ), +GATE (CLK_TZPC3 ,"tzpc3" ,"aclk66" ,GATE_IP_PERIS ,9 ,0 ,0 ), +GATE (CLK_TZPC4 ,"tzpc4" ,"aclk66" ,GATE_IP_PERIS ,10 ,0 ,0 ), +GATE (CLK_TZPC5 ,"tzpc5" ,"aclk66" ,GATE_IP_PERIS ,11 ,0 ,0 ), +GATE (CLK_TZPC6 ,"tzpc6" ,"aclk66" ,GATE_IP_PERIS ,12 ,0 ,0 ), +GATE (CLK_TZPC7 ,"tzpc7" ,"aclk66" ,GATE_IP_PERIS ,13 ,0 ,0 ), +GATE (CLK_TZPC8 ,"tzpc8" ,"aclk66" ,GATE_IP_PERIS ,14 ,0 ,0 ), +GATE (CLK_TZPC9 ,"tzpc9" ,"aclk66" ,GATE_IP_PERIS ,15 ,0 ,0 ), +GATE (CLK_HDMI_CEC ,"hdmi_cec" ,"aclk66" ,GATE_IP_PERIS ,16 ,0 ,0 ), +GATE (CLK_MCT ,"mct" ,"aclk66" ,GATE_IP_PERIS ,18 ,0 ,0 ), +GATE (CLK_WDT ,"wdt" ,"aclk66" ,GATE_IP_PERIS ,19 ,0 ,0 ), +GATE (CLK_RTC ,"rtc" ,"aclk66" ,GATE_IP_PERIS ,20 ,0 ,0 ), +GATE (CLK_TMU ,"tmu" ,"aclk66" ,GATE_IP_PERIS ,21 ,0 ,0 ), +GATE (CLK_CMU_TOP ,"cmu_top" ,"aclk66" ,GATE_IP_PERIS ,3 ,CLK_IGNORE_UNUSED ,0 ), -GATE (cmu_core,"cmu_core" ,"aclk66" , +GATE (CLK_CMU_CORE ,"cmu_core" ,"aclk66" ,GATE_IP_PERIS ,4 ,CLK_IGNORE_UNUSED ,0 ), -GATE (cmu_mem,"cmu_mem" ,"aclk66" , +GATE (CLK_CMU_MEM ,"cmu_mem" ,"aclk66" ,GATE_IP_PERIS ,5 ,CLK_IGNORE_UNUSED ,0 ), -GATE (sclk_cam_bayer,"sclk_cam_bayer" ,"div_cam_bayer" , +GATE (CLK_SCLK_CAM_BAYER ,"sclk_cam_bayer" ,"div_cam_bayer" ,SRC_MASK_GSCL ,12 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_cam0,"sclk_cam0" ,"div_cam0" , +GATE (CLK_SCLK_CAM0 ,"sclk_cam0" ,"div_cam0" ,SRC_MASK_GSCL ,16 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_cam1,"sclk_cam1" ,"div_cam1" , +GATE (CLK_SCLK_CAM1 ,"sclk_cam1" ,"div_cam1" ,SRC_MASK_GSCL ,20 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_gscl_wa,"sclk_gscl_wa" ,"div_gscl_wa" , +GATE (CLK_SCLK_GSCL_WA ,"sclk_gscl_wa" ,"div_gscl_wa" ,SRC_MASK_GSCL ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_gscl_wb,"sclk_gscl_wb" ,"div_gscl_wb" , +GATE (CLK_SCLK_GSCL_WB ,"sclk_gscl_wb" ,"div_gscl_wb" ,SRC_MASK_GSCL ,28 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_fimd1,"sclk_fimd1" ,"div_fimd1" , +GATE (CLK_SCLK_FIMD1 ,"sclk_fimd1" ,"div_fimd1" ,SRC_MASK_DISP1_0 ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mipi1,"sclk_mipi1" ,"div_mipi1" , +GATE (CLK_SCLK_MIPI1 ,"sclk_mipi1" ,"div_mipi1" ,SRC_MASK_DISP1_0 ,12 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_dp,"sclk_dp" ,"div_dp" , +GATE (CLK_SCLK_DP ,"sclk_dp" ,"div_dp" ,SRC_MASK_DISP1_0 ,16 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_hdmi,"sclk_hdmi" ,"mout_hdmi" , +GATE (CLK_SCLK_HDMI ,"sclk_hdmi" ,"mout_hdmi" ,SRC_MASK_DISP1_0 ,20 ,0 ,0 ), -GATE (sclk_audio0,"sclk_audio0" ,"div_audio0" , +GATE (CLK_SCLK_AUDIO0 ,"sclk_audio0" ,"div_audio0" ,SRC_MASK_MAU ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mmc0,"sclk_mmc0" ,"div_mmc_pre0" , +GATE (CLK_SCLK_MMC0 ,"sclk_mmc0" ,"div_mmc_pre0" ,SRC_MASK_FSYS ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mmc1,"sclk_mmc1" ,"div_mmc_pre1" , +GATE (CLK_SCLK_MMC1 ,"sclk_mmc1" ,"div_mmc_pre1" ,SRC_MASK_FSYS ,4 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mmc2,"sclk_mmc2" ,"div_mmc_pre2" , +GATE (CLK_SCLK_MMC2 ,"sclk_mmc2" ,"div_mmc_pre2" ,SRC_MASK_FSYS ,8 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mmc3,"sclk_mmc3" ,"div_mmc_pre3" , +GATE (CLK_SCLK_MMC3 ,"sclk_mmc3" ,"div_mmc_pre3" ,SRC_MASK_FSYS ,12 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_sata,"sclk_sata" ,"div_sata" , +GATE (CLK_SCLK_SATA ,"sclk_sata" ,"div_sata" ,SRC_MASK_FSYS ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_usb3,"sclk_usb3" ,"div_usb3" , +GATE (CLK_SCLK_USB3 ,"sclk_usb3" ,"div_usb3" ,SRC_MASK_FSYS ,28 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_jpeg,"sclk_jpeg" ,"div_jpeg" , +GATE (CLK_SCLK_JPEG ,"sclk_jpeg" ,"div_jpeg" ,SRC_MASK_GEN ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_uart0,"sclk_uart0" ,"div_uart0" , +GATE (CLK_SCLK_UART0 ,"sclk_uart0" ,"div_uart0" ,SRC_MASK_PERIC0 ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_uart1,"sclk_uart1" ,"div_uart1" , +GATE (CLK_SCLK_UART1 ,"sclk_uart1" ,"div_uart1" ,SRC_MASK_PERIC0 ,4 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_uart2,"sclk_uart2" ,"div_uart2" , +GATE (CLK_SCLK_UART2 ,"sclk_uart2" ,"div_uart2" ,SRC_MASK_PERIC0 ,8 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_uart3,"sclk_uart3" ,"div_uart3" , +GATE (CLK_SCLK_UART3 ,"sclk_uart3" ,"div_uart3" ,SRC_MASK_PERIC0 ,12 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_pwm,"sclk_pwm" ,"div_pwm" , +GATE (CLK_SCLK_PWM ,"sclk_pwm" ,"div_pwm" ,SRC_MASK_PERIC0 ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_audio1,"sclk_audio1" ,"div_audio1" , +GATE (CLK_SCLK_AUDIO1 ,"sclk_audio1" ,"div_audio1" ,SRC_MASK_PERIC1 ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_audio2,"sclk_audio2" ,"div_audio2" , +GATE (CLK_SCLK_AUDIO2 ,"sclk_audio2" ,"div_audio2" ,SRC_MASK_PERIC1 ,4 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_spdif,"sclk_spdif" ,"mout_spdif" , +GATE (CLK_SCLK_SPDIF ,"sclk_spdif" ,"mout_spdif" ,SRC_MASK_PERIC1 ,4 ,0 ,0 ), -GATE (sclk_spi0,"sclk_spi0" ,"div_spi_pre0" , +GATE (CLK_SCLK_SPI0 ,"sclk_spi0" ,"div_spi_pre0" ,SRC_MASK_PERIC1 ,16 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_spi1,"sclk_spi1" ,"div_spi_pre1" , +GATE (CLK_SCLK_SPI1 ,"sclk_spi1" ,"div_spi_pre1" ,SRC_MASK_PERIC1 ,20 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_spi2,"sclk_spi2" ,"div_spi_pre2" , +GATE (CLK_SCLK_SPI2 ,"sclk_spi2" ,"div_spi_pre2" ,SRC_MASK_PERIC1 ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (fimd1,"fimd1" ,"aclk200" ,GATE_IP_DISP1 ,0 ,0 ,0 ), -GATE (mie1,"mie1" ,"aclk200" ,GATE_IP_DISP1 ,1 ,0 ,0 ), -GATE (dsim0,"dsim0" ,"aclk200" ,GATE_IP_DISP1 ,3 ,0 ,0 ), -GATE (dp,"dp" ,"aclk200" ,GATE_IP_DISP1 ,4 ,0 ,0 ), -GATE (mixer,"mixer" ,"mout_aclk200_disp1" ,GATE_IP_DISP1 ,5 ,0 ,0 ), -GATE (hdmi,"hdmi" ,"mout_aclk200_disp1" ,GATE_IP_DISP1 ,6 ,0 ,0 ), -GATE (g2d,"g2d" ,"aclk200" ,GATE_IP_ACP ,3 ,0 ,0 ), +GATE (CLK_FIMD1 ,"fimd1" ,"aclk200" ,GATE_IP_DISP1 ,0 ,0 ,0 ), +GATE (CLK_MIE1 ,"mie1" ,"aclk200" ,GATE_IP_DISP1 ,1 ,0 ,0 ), +GATE (CLK_DSIM0 ,"dsim0" ,"aclk200" ,GATE_IP_DISP1 ,3 ,0 ,0 ), +GATE (CLK_DP ,"dp" ,"aclk200" ,GATE_IP_DISP1 ,4 ,0 ,0 ), +GATE (CLK_MIXER ,"mixer" ,"mout_aclk200_disp1" ,GATE_IP_DISP1 ,5 ,0 ,0 ), +GATE (CLK_HDMI ,"hdmi" ,"mout_aclk200_disp1" ,GATE_IP_DISP1 ,6 ,0 ,0 ), +GATE (CLK_G2D ,"g2d" ,"aclk200" ,GATE_IP_ACP ,3 ,0 ,0 ), };static struct samsung_pll_rate_table vpll_24mhz_tbl[]__initdata = {
@@ -518,19 +475,19 @@ static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { };static struct samsung_pll_clock exynos5250_plls[nr_plls]__initdata = { - [apll] =PLL_A (pll_35xx, fout_apll,"fout_apll" ,"fin_pll" ,APLL_LOCK , -APLL_CON0 ,"fout_apll" ,NULL ), - [mpll] =PLL_A (pll_35xx, fout_mpll,"fout_mpll" ,"fin_pll" ,MPLL_LOCK , -MPLL_CON0 ,"fout_mpll" ,NULL ), - [bpll] =PLL (pll_35xx, fout_bpll,"fout_bpll" ,"fin_pll" ,BPLL_LOCK , + [apll] =PLL_A (pll_35xx,CLK_FOUT_APLL ,"fout_apll" ,"fin_pll" , +APLL_LOCK ,APLL_CON0 ,"fout_apll" ,NULL ), + [mpll] =PLL_A (pll_35xx,CLK_FOUT_MPLL ,"fout_mpll" ,"fin_pll" , +MPLL_LOCK ,MPLL_CON0 ,"fout_mpll" ,NULL ), + [bpll] =PLL (pll_35xx,CLK_FOUT_BPLL ,"fout_bpll" ,"fin_pll" ,BPLL_LOCK ,BPLL_CON0 ,NULL ), - [gpll] =PLL (pll_35xx, fout_gpll,"fout_gpll" ,"fin_pll" ,GPLL_LOCK , + [gpll] =PLL (pll_35xx,CLK_FOUT_GPLL ,"fout_gpll" ,"fin_pll" ,GPLL_LOCK ,GPLL_CON0 ,NULL ), - [cpll] =PLL (pll_35xx, fout_cpll,"fout_cpll" ,"fin_pll" ,CPLL_LOCK , + [cpll] =PLL (pll_35xx,CLK_FOUT_CPLL ,"fout_cpll" ,"fin_pll" ,CPLL_LOCK ,CPLL_CON0 ,NULL ), - [epll] =PLL (pll_36xx, fout_epll,"fout_epll" ,"fin_pll" ,EPLL_LOCK , + [epll] =PLL (pll_36xx,CLK_FOUT_EPLL ,"fout_epll" ,"fin_pll" ,EPLL_LOCK ,EPLL_CON0 ,NULL ), - [vpll] =PLL (pll_36xx, fout_vpll,"fout_vpll" ,"mout_vpllsrc" , + [vpll] =PLL (pll_36xx,CLK_FOUT_VPLL ,"fout_vpll" ,"mout_vpllsrc" ,VPLL_LOCK ,VPLL_CON0 ,NULL ), };
@@ -554,7 +511,7 @@ static void __init exynos5250_clk_init(struct device_node *np)panic ("%s: unable to determine soc\n" , __func__); } -samsung_clk_init (np, reg_base, nr_clks, +samsung_clk_init (np, reg_base,CLK_NR_CLKS , exynos5250_clk_regs,ARRAY_SIZE (exynos5250_clk_regs),NULL ,0 ); samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
Signature · 1 line
1.8.1.2
PATCH v2 7/12 ARM: exynos5420: create a DT header defining CLK IDs
In reply to Andrzej HajdaThe patch adds header file defining clock IDs.
This allows to use macros instead of magic numbers in DT bindings.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- include/dt-bindings/clock/exynos5420.h | 188 +++++++++++++++++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 include/dt-bindings/clock/exynos5420.h
include/dt-bindings/clock/exynos5420.h new file +188 -0
@@ -0,0 +1,188 @@ +/* +* Copyright (c) 2013 Samsung Electronics Co., Ltd. +* Author: Andrzej Haja <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* Device Tree binding constants for Exynos5420 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H + +/* core clocks */ +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_CPLL 3 +#define CLK_FOUT_DPLL 4 +#define CLK_FOUT_EPLL 5 +#define CLK_FOUT_RPLL 6 +#define CLK_FOUT_IPLL 7 +#define CLK_FOUT_SPLL 8 +#define CLK_FOUT_VPLL 9 +#define CLK_FOUT_MPLL 10 +#define CLK_FOUT_BPLL 11 +#define CLK_FOUT_KPLL 12 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_UART0 128 +#define CLK_SCLK_UART1 129 +#define CLK_SCLK_UART2 130 +#define CLK_SCLK_UART3 131 +#define CLK_SCLK_MMC0 132 +#define CLK_SCLK_MMC1 133 +#define CLK_SCLK_MMC2 134 +#define CLK_SCLK_SPI0 135 +#define CLK_SCLK_SPI1 136 +#define CLK_SCLK_SPI2 137 +#define CLK_SCLK_I2S1 138 +#define CLK_SCLK_I2S2 139 +#define CLK_SCLK_PCM1 140 +#define CLK_SCLK_PCM2 141 +#define CLK_SCLK_SPDIF 142 +#define CLK_SCLK_HDMI 143 +#define CLK_SCLK_PIXEL 144 +#define CLK_SCLK_DP1 145 +#define CLK_SCLK_MIPI1 146 +#define CLK_SCLK_FIMD1 147 +#define CLK_SCLK_MAUDIO0 148 +#define CLK_SCLK_MAUPCM0 149 +#define CLK_SCLK_USBD300 150 +#define CLK_SCLK_USBD301 151 +#define CLK_SCLK_USBPHY300 152 +#define CLK_SCLK_USBPHY301 153 +#define CLK_SCLK_UNIPRO 154 +#define CLK_SCLK_PWM 155 +#define CLK_SCLK_GSCL_WA 156 +#define CLK_SCLK_GSCL_WB 157 +#define CLK_SCLK_HDMIPHY 158 + +/* gate clocks */ +#define CLK_ACLK66_PERIC 256 +#define CLK_UART0 257 +#define CLK_UART1 258 +#define CLK_UART2 259 +#define CLK_UART3 260 +#define CLK_I2C0 261 +#define CLK_I2C1 262 +#define CLK_I2C2 263 +#define CLK_I2C3 264 +#define CLK_I2C4 265 +#define CLK_I2C5 266 +#define CLK_I2C6 267 +#define CLK_I2C7 268 +#define CLK_I2C_HDMI 269 +#define CLK_TSADC 270 +#define CLK_SPI0 271 +#define CLK_SPI1 272 +#define CLK_SPI2 273 +#define CLK_KEYIF 274 +#define CLK_I2S1 275 +#define CLK_I2S2 276 +#define CLK_PCM1 277 +#define CLK_PCM2 278 +#define CLK_PWM 279 +#define CLK_SPDIF 280 +#define CLK_I2C8 281 +#define CLK_I2C9 282 +#define CLK_I2C10 283 +#define CLK_ACLK66_PSGEN 300 +#define CLK_CHIPID 301 +#define CLK_SYSREG 302 +#define CLK_TZPC0 303 +#define CLK_TZPC1 304 +#define CLK_TZPC2 305 +#define CLK_TZPC3 306 +#define CLK_TZPC4 307 +#define CLK_TZPC5 308 +#define CLK_TZPC6 309 +#define CLK_TZPC7 310 +#define CLK_TZPC8 311 +#define CLK_TZPC9 312 +#define CLK_HDMI_CEC 313 +#define CLK_SECKEY 314 +#define CLK_MCT 315 +#define CLK_WDT 316 +#define CLK_RTC 317 +#define CLK_TMU 318 +#define CLK_TMU_GPU 319 +#define CLK_PCLK66_GPIO 330 +#define CLK_ACLK200_FSYS2 350 +#define CLK_MMC0 351 +#define CLK_MMC1 352 +#define CLK_MMC2 353 +#define CLK_SROMC 354 +#define CLK_UFS 355 +#define CLK_ACLK200_FSYS 360 +#define CLK_TSI 361 +#define CLK_PDMA0 362 +#define CLK_PDMA1 363 +#define CLK_RTIC 364 +#define CLK_USBH20 365 +#define CLK_USBD300 366 +#define CLK_USBD301 367 +#define CLK_ACLK400_MSCL 380 +#define CLK_MSCL0 381 +#define CLK_MSCL1 382 +#define CLK_MSCL2 383 +#define CLK_SMMU_MSCL0 384 +#define CLK_SMMU_MSCL1 385 +#define CLK_SMMU_MSCL2 386 +#define CLK_ACLK333 400 +#define CLK_MFC 401 +#define CLK_SMMU_MFCL 402 +#define CLK_SMMU_MFCR 403 +#define CLK_ACLK200_DISP1 410 +#define CLK_DSIM1 411 +#define CLK_DP1 412 +#define CLK_HDMI 413 +#define CLK_ACLK300_DISP1 420 +#define CLK_FIMD1 421 +#define CLK_SMMU_FIMD1 422 +#define CLK_ACLK166 430 +#define CLK_MIXER 431 +#define CLK_ACLK266 440 +#define CLK_ROTATOR 441 +#define CLK_MDMA1 442 +#define CLK_SMMU_ROTATOR 443 +#define CLK_SMMU_MDMA1 444 +#define CLK_ACLK300_JPEG 450 +#define CLK_JPEG 451 +#define CLK_JPEG2 452 +#define CLK_SMMU_JPEG 453 +#define CLK_ACLK300_GSCL 460 +#define CLK_SMMU_GSCL0 461 +#define CLK_SMMU_GSCL1 462 +#define CLK_GSCL_WA 463 +#define CLK_GSCL_WB 464 +#define CLK_GSCL0 465 +#define CLK_GSCL1 466 +#define CLK_CLK_3AA 467 +#define CLK_ACLK266_G2D 470 +#define CLK_SSS 471 +#define CLK_SLIM_SSS 472 +#define CLK_MDMA0 473 +#define CLK_ACLK333_G2D 480 +#define CLK_G2D 481 +#define CLK_ACLK333_432_GSCL 490 +#define CLK_SMMU_3AA 491 +#define CLK_SMMU_FIMCL0 492 +#define CLK_SMMU_FIMCL1 493 +#define CLK_SMMU_FIMCL3 494 +#define CLK_FIMC_LITE3 495 +#define CLK_ACLK_G3D 500 +#define CLK_G3D 501 +#define CLK_SMMU_MIXER 502 + +/* mux clocks */ +#define CLK_MOUT_HDMI 640 + +/* divider clocks */ +#define CLK_DOUT_PIXEL 768 + +/* must be greater than maximal clock id */ +#define CLK_NR_CLKS 769 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
Signature · 1 line
1.8.1.2
PATCH v2 8/12 ARM: dts: exynos5420: convert magic numbers to macros in clock bindings
In reply to Andrzej HajdaThe patch replaces magic numbers with macros defined in DT header in exynos5420 clock bindings.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- .../devicetree/bindings/clock/exynos5420-clock.txt | 184 +-------------------- arch/arm/boot/dts/exynos5420.dtsi | 13 +- 2 files changed, 13 insertions(+), 184 deletions(-)
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +6 -178
@@ -13,184 +13,12 @@ Required Properties: - #clock-cells: should be 1. -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. - - [Core Clocks] - - Clock ID - ---------------------------- - - fin_pll 1 - - [Clock Gate for Special Clocks] - - Clock ID - ---------------------------- - sclk_uart0 128 - sclk_uart1 129 - sclk_uart2 130 - sclk_uart3 131 - sclk_mmc0 132 - sclk_mmc1 133 - sclk_mmc2 134 - sclk_spi0 135 - sclk_spi1 136 - sclk_spi2 137 - sclk_i2s1 138 - sclk_i2s2 139 - sclk_pcm1 140 - sclk_pcm2 141 - sclk_spdif 142 - sclk_hdmi 143 - sclk_pixel 144 - sclk_dp1 145 - sclk_mipi1 146 - sclk_fimd1 147 - sclk_maudio0 148 - sclk_maupcm0 149 - sclk_usbd300 150 - sclk_usbd301 151 - sclk_usbphy300 152 - sclk_usbphy301 153 - sclk_unipro 154 - sclk_pwm 155 - sclk_gscl_wa 156 - sclk_gscl_wb 157 - sclk_hdmiphy 158 - - [Peripheral Clock Gates] - - Clock ID - ---------------------------- - - aclk66_peric 256 - uart0 257 - uart1 258 - uart2 259 - uart3 260 - i2c0 261 - i2c1 262 - i2c2 263 - i2c3 264 - i2c4 265 - i2c5 266 - i2c6 267 - i2c7 268 - i2c_hdmi 269 - tsadc 270 - spi0 271 - spi1 272 - spi2 273 - keyif 274 - i2s1 275 - i2s2 276 - pcm1 277 - pcm2 278 - pwm 279 - spdif 280 - i2c8 281 - i2c9 282 - i2c10 283 - aclk66_psgen 300 - chipid 301 - sysreg 302 - tzpc0 303 - tzpc1 304 - tzpc2 305 - tzpc3 306 - tzpc4 307 - tzpc5 308 - tzpc6 309 - tzpc7 310 - tzpc8 311 - tzpc9 312 - hdmi_cec 313 - seckey 314 - mct 315 - wdt 316 - rtc 317 - tmu 318 - tmu_gpu 319 - pclk66_gpio 330 - aclk200_fsys2 350 - mmc0 351 - mmc1 352 - mmc2 353 - sromc 354 - ufs 355 - aclk200_fsys 360 - tsi 361 - pdma0 362 - pdma1 363 - rtic 364 - usbh20 365 - usbd300 366 - usbd301 377 - aclk400_mscl 380 - mscl0 381 - mscl1 382 - mscl2 383 - smmu_mscl0 384 - smmu_mscl1 385 - smmu_mscl2 386 - aclk333 400 - mfc 401 - smmu_mfcl 402 - smmu_mfcr 403 - aclk200_disp1 410 - dsim1 411 - dp1 412 - hdmi 413 - aclk300_disp1 420 - fimd1 421 - smmu_fimd1 422 - aclk166 430 - mixer 431 - aclk266 440 - rotator 441 - mdma1 442 - smmu_rotator 443 - smmu_mdma1 444 - aclk300_jpeg 450 - jpeg 451 - jpeg2 452 - smmu_jpeg 453 - aclk300_gscl 460 - smmu_gscl0 461 - smmu_gscl1 462 - gscl_wa 463 - gscl_wb 464 - gscl0 465 - gscl1 466 - clk_3aa 467 - aclk266_g2d 470 - sss 471 - slim_sss 472 - mdma0 473 - aclk333_g2d 480 - g2d 481 - aclk333_432_gscl 490 - smmu_3aa 491 - smmu_fimcl0 492 - smmu_fimcl1 493 - smmu_fimcl3 494 - fimc_lite3 495 - aclk_g3d 500 - g3d 501 - smmu_mixer 502 - - Mux ID - ---------------------------- - - mout_hdmi 640 - - Divider ID - ---------------------------- - - dout_pixel 768 +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5420.h header and can be used in device +tree sources. Example 1: An example of a clock controller node is listed below.
@@ -208,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; interrupts = <0 54 0>; - clocks = <&clock 259>, <&clock 130>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; };
arch/arm/boot/dts/exynos5420.dtsi +7 -6
@@ -13,8 +13,9 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/clock/exynos5420.h> #include "exynos5.dtsi" -/include/ "exynos5420-pinctrl.dtsi" +#include "exynos5420-pinctrl.dtsi" / { compatible = "samsung,exynos5420";
@@ -72,7 +73,7 @@ #interrups-cells = <1>; interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; - clocks = <&clock 1>, <&clock 315>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; mct_map: mct-map {
@@ -127,22 +128,22 @@ }; serial at 12C00000 { - clocks = <&clock 257>, <&clock 128>; + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; }; serial at 12C10000 { - clocks = <&clock 258>, <&clock 129>; + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; }; serial at 12C20000 { - clocks = <&clock 259>, <&clock 130>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; }; serial at 12C30000 { - clocks = <&clock 260>, <&clock 131>; + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; }; };
Signature · 1 line
1.8.1.2
PATCH v2 9/12 clk: exynos5420: replace clock ID private enums with IDs from DT header
In reply to Andrzej HajdaThe patch replaces private enum clock IDs in the driver with macros provided by the DT header.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 648 +++++++++++++++++------------------ 1 file changed, 309 insertions(+), 339 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +309 -339
@@ -10,6 +10,7 @@* Common Clock Framework support for Exynos5420 SoC. */ +#include <dt-bindings/clock/exynos5420.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h>
@@ -107,48 +108,6 @@ enum exynos5420_plls { nr_plls /* number of PLLs */ }; -enum exynos5420_clks { - none, - -/* core clocks */ - fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll, - fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll, - -/* gate for special clocks (sclk) */ - sclk_uart0 =128 , sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0, - sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1, - sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel, - sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0, - sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro, - sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy, - -/* gate clocks */ - aclk66_peric =256 , uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3, - i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1, - i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen =300 , - chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, - tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu, - pclk66_gpio =330 , aclk200_fsys2 =350 , mmc0, mmc1, mmc2, sromc, ufs, - aclk200_fsys =360 , tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301, - aclk400_mscl =380 , mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1, - smmu_mscl2, aclk333 =400 , mfc, smmu_mfcl, smmu_mfcr, - aclk200_disp1 =410 , dsim1, dp1, hdmi, aclk300_disp1 =420 , fimd1, - smmu_fimd1, aclk166 =430 , mixer, aclk266 =440 , rotator, mdma1, - smmu_rotator, smmu_mdma1, aclk300_jpeg =450 , jpeg, jpeg2, smmu_jpeg, - aclk300_gscl =460 , smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0, - gscl1, clk_3aa, aclk266_g2d =470 , sss, slim_sss, mdma0, - aclk333_g2d =480 , g2d, aclk333_432_gscl =490 , smmu_3aa, smmu_fimcl0, - smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d =500 , g3d, smmu_mixer, - -/* mux clocks */ - mout_hdmi =640 , - -/* divider clocks */ - dout_pixel =768 , - - nr_clks, -}; -/* * list of controller registers to be saved and restored during a * suspend/resume cycle.
@@ -298,225 +257,226 @@ PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[]__initdata = { -FRATE (fin_pll,"fin_pll" ,NULL ,CLK_IS_ROOT ,0 ), +FRATE (CLK_FIN_PLL ,"fin_pll" ,NULL ,CLK_IS_ROOT ,0 ), };/* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[]__initdata = { -FRATE (sclk_hdmiphy,"sclk_hdmiphy" ,NULL ,CLK_IS_ROOT ,24000000 ), -FRATE (none,"sclk_pwi" ,NULL ,CLK_IS_ROOT ,24000000 ), -FRATE (none,"sclk_usbh20" ,NULL ,CLK_IS_ROOT ,48000000 ), -FRATE (none,"mphy_refclk_ixtal24" ,NULL ,CLK_IS_ROOT ,48000000 ), -FRATE (none,"sclk_usbh20_scan_clk" ,NULL ,CLK_IS_ROOT ,480000000 ), +FRATE (CLK_SCLK_HDMIPHY ,"sclk_hdmiphy" ,NULL ,CLK_IS_ROOT ,24000000 ), +FRATE (0 ,"sclk_pwi" ,NULL ,CLK_IS_ROOT ,24000000 ), +FRATE (0 ,"sclk_usbh20" ,NULL ,CLK_IS_ROOT ,48000000 ), +FRATE (0 ,"mphy_refclk_ixtal24" ,NULL ,CLK_IS_ROOT ,48000000 ), +FRATE (0 ,"sclk_usbh20_scan_clk" ,NULL ,CLK_IS_ROOT ,480000000 ), };static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[]__initdata = { -FFACTOR (none,"sclk_hsic_12m" ,"fin_pll" ,1 ,2 ,0 ), +FFACTOR (0 ,"sclk_hsic_12m" ,"fin_pll" ,1 ,2 ,0 ), };static struct samsung_mux_clock exynos5420_mux_clks[]__initdata = { -MUX (none,"mout_mspll_kfc" , mspll_cpu_p,SRC_TOP7 ,8 ,2 ), -MUX (none,"mout_mspll_cpu" , mspll_cpu_p,SRC_TOP7 ,12 ,2 ), -MUX (none,"mout_apll" , apll_p,SRC_CPU ,0 ,1 ), -MUX (none,"mout_cpu" , cpu_p,SRC_CPU ,16 ,1 ), -MUX (none,"mout_kpll" , kpll_p,SRC_KFC ,0 ,1 ), -MUX (none,"mout_cpu_kfc" , kfc_p,SRC_KFC ,16 ,1 ), +MUX (0 ,"mout_mspll_kfc" , mspll_cpu_p,SRC_TOP7 ,8 ,2 ), +MUX (0 ,"mout_mspll_cpu" , mspll_cpu_p,SRC_TOP7 ,12 ,2 ), +MUX (0 ,"mout_apll" , apll_p,SRC_CPU ,0 ,1 ), +MUX (0 ,"mout_cpu" , cpu_p,SRC_CPU ,16 ,1 ), +MUX (0 ,"mout_kpll" , kpll_p,SRC_KFC ,0 ,1 ), +MUX (0 ,"mout_cpu_kfc" , kfc_p,SRC_KFC ,16 ,1 ), -MUX (none,"sclk_bpll" , bpll_p,SRC_CDREX ,0 ,1 ), +MUX (0 ,"sclk_bpll" , bpll_p,SRC_CDREX ,0 ,1 ), -MUX_A (none,"mout_aclk400_mscl" , group1_p, +MUX_A (0 ,"mout_aclk400_mscl" , group1_p,SRC_TOP0 ,4 ,2 ,"aclk400_mscl" ), -MUX (none,"mout_aclk200" , group1_p,SRC_TOP0 ,8 ,2 ), -MUX (none,"mout_aclk200_fsys2" , group1_p,SRC_TOP0 ,12 ,2 ), -MUX (none,"mout_aclk200_fsys" , group1_p,SRC_TOP0 ,28 ,2 ), - -MUX (none,"mout_aclk333_432_gscl" , group4_p,SRC_TOP1 ,0 ,2 ), -MUX (none,"mout_aclk66" , group1_p,SRC_TOP1 ,8 ,2 ), -MUX (none,"mout_aclk266" , group1_p,SRC_TOP1 ,20 ,2 ), -MUX (none,"mout_aclk166" , group1_p,SRC_TOP1 ,24 ,2 ), -MUX (none,"mout_aclk333" , group1_p,SRC_TOP1 ,28 ,2 ), - -MUX (none,"mout_aclk333_g2d" , group1_p,SRC_TOP2 ,8 ,2 ), -MUX (none,"mout_aclk266_g2d" , group1_p,SRC_TOP2 ,12 ,2 ), -MUX (none,"mout_aclk_g3d" , group5_p,SRC_TOP2 ,16 ,1 ), -MUX (none,"mout_aclk300_jpeg" , group1_p,SRC_TOP2 ,20 ,2 ), -MUX (none,"mout_aclk300_disp1" , group1_p,SRC_TOP2 ,24 ,2 ), -MUX (none,"mout_aclk300_gscl" , group1_p,SRC_TOP2 ,28 ,2 ), - -MUX (none,"mout_user_aclk400_mscl" , user_aclk400_mscl_p, +MUX (0 ,"mout_aclk200" , group1_p,SRC_TOP0 ,8 ,2 ), +MUX (0 ,"mout_aclk200_fsys2" , group1_p,SRC_TOP0 ,12 ,2 ), +MUX (0 ,"mout_aclk200_fsys" , group1_p,SRC_TOP0 ,28 ,2 ), + +MUX (0 ,"mout_aclk333_432_gscl" , group4_p,SRC_TOP1 ,0 ,2 ), +MUX (0 ,"mout_aclk66" , group1_p,SRC_TOP1 ,8 ,2 ), +MUX (0 ,"mout_aclk266" , group1_p,SRC_TOP1 ,20 ,2 ), +MUX (0 ,"mout_aclk166" , group1_p,SRC_TOP1 ,24 ,2 ), +MUX (0 ,"mout_aclk333" , group1_p,SRC_TOP1 ,28 ,2 ), + +MUX (0 ,"mout_aclk333_g2d" , group1_p,SRC_TOP2 ,8 ,2 ), +MUX (0 ,"mout_aclk266_g2d" , group1_p,SRC_TOP2 ,12 ,2 ), +MUX (0 ,"mout_aclk_g3d" , group5_p,SRC_TOP2 ,16 ,1 ), +MUX (0 ,"mout_aclk300_jpeg" , group1_p,SRC_TOP2 ,20 ,2 ), +MUX (0 ,"mout_aclk300_disp1" , group1_p,SRC_TOP2 ,24 ,2 ), +MUX (0 ,"mout_aclk300_gscl" , group1_p,SRC_TOP2 ,28 ,2 ), + +MUX (0 ,"mout_user_aclk400_mscl" , user_aclk400_mscl_p,SRC_TOP3 ,4 ,1 ), -MUX_A (none,"mout_aclk200_disp1" , aclk200_disp1_p, +MUX_A (0 ,"mout_aclk200_disp1" , aclk200_disp1_p,SRC_TOP3 ,8 ,1 ,"aclk200_disp1" ), -MUX (none,"mout_user_aclk200_fsys2" , user_aclk200_fsys2_p, +MUX (0 ,"mout_user_aclk200_fsys2" , user_aclk200_fsys2_p,SRC_TOP3 ,12 ,1 ), -MUX (none,"mout_user_aclk200_fsys" , user_aclk200_fsys_p, +MUX (0 ,"mout_user_aclk200_fsys" , user_aclk200_fsys_p,SRC_TOP3 ,28 ,1 ), -MUX (none,"mout_user_aclk333_432_gscl" , user_aclk333_432_gscl_p, +MUX (0 ,"mout_user_aclk333_432_gscl" , user_aclk333_432_gscl_p,SRC_TOP4 ,0 ,1 ), -MUX (none,"mout_aclk66_peric" , aclk66_peric_p,SRC_TOP4 ,8 ,1 ), -MUX (none,"mout_user_aclk266" , user_aclk266_p,SRC_TOP4 ,20 ,1 ), -MUX (none,"mout_user_aclk166" , user_aclk166_p,SRC_TOP4 ,24 ,1 ), -MUX (none,"mout_user_aclk333" , user_aclk333_p,SRC_TOP4 ,28 ,1 ), - -MUX (none,"mout_aclk66_psgen" , aclk66_peric_p,SRC_TOP5 ,4 ,1 ), -MUX (none,"mout_user_aclk333_g2d" , user_aclk333_g2d_p,SRC_TOP5 ,8 ,1 ), -MUX (none,"mout_user_aclk266_g2d" , user_aclk266_g2d_p,SRC_TOP5 ,12 ,1 ), -MUX_A (none,"mout_user_aclk_g3d" , user_aclk_g3d_p, +MUX (0 ,"mout_aclk66_peric" , aclk66_peric_p,SRC_TOP4 ,8 ,1 ), +MUX (0 ,"mout_user_aclk266" , user_aclk266_p,SRC_TOP4 ,20 ,1 ), +MUX (0 ,"mout_user_aclk166" , user_aclk166_p,SRC_TOP4 ,24 ,1 ), +MUX (0 ,"mout_user_aclk333" , user_aclk333_p,SRC_TOP4 ,28 ,1 ), + +MUX (0 ,"mout_aclk66_psgen" , aclk66_peric_p,SRC_TOP5 ,4 ,1 ), +MUX (0 ,"mout_user_aclk333_g2d" , user_aclk333_g2d_p,SRC_TOP5 ,8 ,1 ), +MUX (0 ,"mout_user_aclk266_g2d" , user_aclk266_g2d_p,SRC_TOP5 ,12 ,1 ), +MUX_A (0 ,"mout_user_aclk_g3d" , user_aclk_g3d_p,SRC_TOP5 ,16 ,1 ,"aclkg3d" ), -MUX (none,"mout_user_aclk300_jpeg" , user_aclk300_jpeg_p, +MUX (0 ,"mout_user_aclk300_jpeg" , user_aclk300_jpeg_p,SRC_TOP5 ,20 ,1 ), -MUX (none,"mout_user_aclk300_disp1" , user_aclk300_disp1_p, +MUX (0 ,"mout_user_aclk300_disp1" , user_aclk300_disp1_p,SRC_TOP5 ,24 ,1 ), -MUX (none,"mout_user_aclk300_gscl" , user_aclk300_gscl_p, +MUX (0 ,"mout_user_aclk300_gscl" , user_aclk300_gscl_p,SRC_TOP5 ,28 ,1 ), -MUX (none,"sclk_mpll" , mpll_p,SRC_TOP6 ,0 ,1 ), -MUX (none,"sclk_vpll" , vpll_p,SRC_TOP6 ,4 ,1 ), -MUX (none,"sclk_spll" , spll_p,SRC_TOP6 ,8 ,1 ), -MUX (none,"sclk_ipll" , ipll_p,SRC_TOP6 ,12 ,1 ), -MUX (none,"sclk_rpll" , rpll_p,SRC_TOP6 ,16 ,1 ), -MUX (none,"sclk_epll" , epll_p,SRC_TOP6 ,20 ,1 ), -MUX (none,"sclk_dpll" , dpll_p,SRC_TOP6 ,24 ,1 ), -MUX (none,"sclk_cpll" , cpll_p,SRC_TOP6 ,28 ,1 ), - -MUX (none,"mout_sw_aclk400_mscl" , sw_aclk400_mscl_p,SRC_TOP10 ,4 ,1 ), -MUX (none,"mout_sw_aclk200" , sw_aclk200_p,SRC_TOP10 ,8 ,1 ), -MUX (none,"mout_sw_aclk200_fsys2" , sw_aclk200_fsys2_p, +MUX (0 ,"sclk_mpll" , mpll_p,SRC_TOP6 ,0 ,1 ), +MUX (0 ,"sclk_vpll" , vpll_p,SRC_TOP6 ,4 ,1 ), +MUX (0 ,"sclk_spll" , spll_p,SRC_TOP6 ,8 ,1 ), +MUX (0 ,"sclk_ipll" , ipll_p,SRC_TOP6 ,12 ,1 ), +MUX (0 ,"sclk_rpll" , rpll_p,SRC_TOP6 ,16 ,1 ), +MUX (0 ,"sclk_epll" , epll_p,SRC_TOP6 ,20 ,1 ), +MUX (0 ,"sclk_dpll" , dpll_p,SRC_TOP6 ,24 ,1 ), +MUX (0 ,"sclk_cpll" , cpll_p,SRC_TOP6 ,28 ,1 ), + +MUX (0 ,"mout_sw_aclk400_mscl" , sw_aclk400_mscl_p,SRC_TOP10 ,4 ,1 ), +MUX (0 ,"mout_sw_aclk200" , sw_aclk200_p,SRC_TOP10 ,8 ,1 ), +MUX (0 ,"mout_sw_aclk200_fsys2" , sw_aclk200_fsys2_p,SRC_TOP10 ,12 ,1 ), -MUX (none,"mout_sw_aclk200_fsys" , sw_aclk200_fsys_p,SRC_TOP10 ,28 ,1 ), +MUX (0 ,"mout_sw_aclk200_fsys" , sw_aclk200_fsys_p,SRC_TOP10 ,28 ,1 ), -MUX (none,"mout_sw_aclk333_432_gscl" , sw_aclk333_432_gscl_p, +MUX (0 ,"mout_sw_aclk333_432_gscl" , sw_aclk333_432_gscl_p,SRC_TOP11 ,0 ,1 ), -MUX (none,"mout_sw_aclk66" , sw_aclk66_p,SRC_TOP11 ,8 ,1 ), -MUX (none,"mout_sw_aclk266" , sw_aclk266_p,SRC_TOP11 ,20 ,1 ), -MUX (none,"mout_sw_aclk166" , sw_aclk166_p,SRC_TOP11 ,24 ,1 ), -MUX (none,"mout_sw_aclk333" , sw_aclk333_p,SRC_TOP11 ,28 ,1 ), - -MUX (none,"mout_sw_aclk333_g2d" , sw_aclk333_g2d_p,SRC_TOP12 ,8 ,1 ), -MUX (none,"mout_sw_aclk266_g2d" , sw_aclk266_g2d_p,SRC_TOP12 ,12 ,1 ), -MUX (none,"mout_sw_aclk_g3d" , sw_aclk_g3d_p,SRC_TOP12 ,16 ,1 ), -MUX (none,"mout_sw_aclk300_jpeg" , sw_aclk300_jpeg_p,SRC_TOP12 ,20 ,1 ), -MUX (none,"mout_sw_aclk300_disp1" , sw_aclk300_disp1_p, +MUX (0 ,"mout_sw_aclk66" , sw_aclk66_p,SRC_TOP11 ,8 ,1 ), +MUX (0 ,"mout_sw_aclk266" , sw_aclk266_p,SRC_TOP11 ,20 ,1 ), +MUX (0 ,"mout_sw_aclk166" , sw_aclk166_p,SRC_TOP11 ,24 ,1 ), +MUX (0 ,"mout_sw_aclk333" , sw_aclk333_p,SRC_TOP11 ,28 ,1 ), + +MUX (0 ,"mout_sw_aclk333_g2d" , sw_aclk333_g2d_p,SRC_TOP12 ,8 ,1 ), +MUX (0 ,"mout_sw_aclk266_g2d" , sw_aclk266_g2d_p,SRC_TOP12 ,12 ,1 ), +MUX (0 ,"mout_sw_aclk_g3d" , sw_aclk_g3d_p,SRC_TOP12 ,16 ,1 ), +MUX (0 ,"mout_sw_aclk300_jpeg" , sw_aclk300_jpeg_p,SRC_TOP12 ,20 ,1 ), +MUX (0 ,"mout_sw_aclk300_disp1" , sw_aclk300_disp1_p,SRC_TOP12 ,24 ,1 ), -MUX (none,"mout_sw_aclk300_gscl" , sw_aclk300_gscl_p,SRC_TOP12 ,28 ,1 ), +MUX (0 ,"mout_sw_aclk300_gscl" , sw_aclk300_gscl_p,SRC_TOP12 ,28 ,1 ),/* DISP1 Block */ -MUX (none,"mout_fimd1" , group3_p,SRC_DISP10 ,4 ,1 ), -MUX (none,"mout_mipi1" , group2_p,SRC_DISP10 ,16 ,3 ), -MUX (none,"mout_dp1" , group2_p,SRC_DISP10 ,20 ,3 ), -MUX (none,"mout_pixel" , group2_p,SRC_DISP10 ,24 ,3 ), -MUX (mout_hdmi,"mout_hdmi" , hdmi_p,SRC_DISP10 ,28 ,1 ), +MUX (0 ,"mout_fimd1" , group3_p,SRC_DISP10 ,4 ,1 ), +MUX (0 ,"mout_mipi1" , group2_p,SRC_DISP10 ,16 ,3 ), +MUX (0 ,"mout_dp1" , group2_p,SRC_DISP10 ,20 ,3 ), +MUX (0 ,"mout_pixel" , group2_p,SRC_DISP10 ,24 ,3 ), +MUX (CLK_MOUT_HDMI ,"mout_hdmi" , hdmi_p,SRC_DISP10 ,28 ,1 ),/* MAU Block */ -MUX (none,"mout_maudio0" , maudio0_p,SRC_MAU ,28 ,3 ), +MUX (0 ,"mout_maudio0" , maudio0_p,SRC_MAU ,28 ,3 ),/* FSYS Block */ -MUX (none,"mout_usbd301" , group2_p,SRC_FSYS ,4 ,3 ), -MUX (none,"mout_mmc0" , group2_p,SRC_FSYS ,8 ,3 ), -MUX (none,"mout_mmc1" , group2_p,SRC_FSYS ,12 ,3 ), -MUX (none,"mout_mmc2" , group2_p,SRC_FSYS ,16 ,3 ), -MUX (none,"mout_usbd300" , group2_p,SRC_FSYS ,20 ,3 ), -MUX (none,"mout_unipro" , group2_p,SRC_FSYS ,24 ,3 ), +MUX (0 ,"mout_usbd301" , group2_p,SRC_FSYS ,4 ,3 ), +MUX (0 ,"mout_mmc0" , group2_p,SRC_FSYS ,8 ,3 ), +MUX (0 ,"mout_mmc1" , group2_p,SRC_FSYS ,12 ,3 ), +MUX (0 ,"mout_mmc2" , group2_p,SRC_FSYS ,16 ,3 ), +MUX (0 ,"mout_usbd300" , group2_p,SRC_FSYS ,20 ,3 ), +MUX (0 ,"mout_unipro" , group2_p,SRC_FSYS ,24 ,3 ),/* PERIC Block */ -MUX (none,"mout_uart0" , group2_p,SRC_PERIC0 ,4 ,3 ), -MUX (none,"mout_uart1" , group2_p,SRC_PERIC0 ,8 ,3 ), -MUX (none,"mout_uart2" , group2_p,SRC_PERIC0 ,12 ,3 ), -MUX (none,"mout_uart3" , group2_p,SRC_PERIC0 ,16 ,3 ), -MUX (none,"mout_pwm" , group2_p,SRC_PERIC0 ,24 ,3 ), -MUX (none,"mout_spdif" , spdif_p,SRC_PERIC0 ,28 ,3 ), -MUX (none,"mout_audio0" , audio0_p,SRC_PERIC1 ,8 ,3 ), -MUX (none,"mout_audio1" , audio1_p,SRC_PERIC1 ,12 ,3 ), -MUX (none,"mout_audio2" , audio2_p,SRC_PERIC1 ,16 ,3 ), -MUX (none,"mout_spi0" , group2_p,SRC_PERIC1 ,20 ,3 ), -MUX (none,"mout_spi1" , group2_p,SRC_PERIC1 ,24 ,3 ), -MUX (none,"mout_spi2" , group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_uart0" , group2_p,SRC_PERIC0 ,4 ,3 ), +MUX (0 ,"mout_uart1" , group2_p,SRC_PERIC0 ,8 ,3 ), +MUX (0 ,"mout_uart2" , group2_p,SRC_PERIC0 ,12 ,3 ), +MUX (0 ,"mout_uart3" , group2_p,SRC_PERIC0 ,16 ,3 ), +MUX (0 ,"mout_pwm" , group2_p,SRC_PERIC0 ,24 ,3 ), +MUX (0 ,"mout_spdif" , spdif_p,SRC_PERIC0 ,28 ,3 ), +MUX (0 ,"mout_audio0" , audio0_p,SRC_PERIC1 ,8 ,3 ), +MUX (0 ,"mout_audio1" , audio1_p,SRC_PERIC1 ,12 ,3 ), +MUX (0 ,"mout_audio2" , audio2_p,SRC_PERIC1 ,16 ,3 ), +MUX (0 ,"mout_spi0" , group2_p,SRC_PERIC1 ,20 ,3 ), +MUX (0 ,"mout_spi1" , group2_p,SRC_PERIC1 ,24 ,3 ), +MUX (0 ,"mout_spi2" , group2_p,SRC_PERIC1 ,28 ,3 ), };static struct samsung_div_clock exynos5420_div_clks[]__initdata = { -DIV (none,"div_arm" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 ), -DIV (none,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 ), -DIV (none,"armclk2" ,"div_arm" ,DIV_CPU0 ,28 ,3 ), -DIV (none,"div_kfc" ,"mout_cpu_kfc" ,DIV_KFC0 ,0 ,3 ), -DIV (none,"sclk_kpll" ,"mout_kpll" ,DIV_KFC0 ,24 ,3 ), - -DIV (none,"dout_aclk400_mscl" ,"mout_aclk400_mscl" ,DIV_TOP0 ,4 ,3 ), -DIV (none,"dout_aclk200" ,"mout_aclk200" ,DIV_TOP0 ,8 ,3 ), -DIV (none,"dout_aclk200_fsys2" ,"mout_aclk200_fsys2" ,DIV_TOP0 ,12 ,3 ), -DIV (none,"dout_pclk200_fsys" ,"mout_pclk200_fsys" ,DIV_TOP0 ,24 ,3 ), -DIV (none,"dout_aclk200_fsys" ,"mout_aclk200_fsys" ,DIV_TOP0 ,28 ,3 ), - -DIV (none,"dout_aclk333_432_gscl" ,"mout_aclk333_432_gscl" , +DIV (0 ,"div_arm" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 ), +DIV (0 ,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 ), +DIV (0 ,"armclk2" ,"div_arm" ,DIV_CPU0 ,28 ,3 ), +DIV (0 ,"div_kfc" ,"mout_cpu_kfc" ,DIV_KFC0 ,0 ,3 ), +DIV (0 ,"sclk_kpll" ,"mout_kpll" ,DIV_KFC0 ,24 ,3 ), + +DIV (0 ,"dout_aclk400_mscl" ,"mout_aclk400_mscl" ,DIV_TOP0 ,4 ,3 ), +DIV (0 ,"dout_aclk200" ,"mout_aclk200" ,DIV_TOP0 ,8 ,3 ), +DIV (0 ,"dout_aclk200_fsys2" ,"mout_aclk200_fsys2" ,DIV_TOP0 ,12 ,3 ), +DIV (0 ,"dout_pclk200_fsys" ,"mout_pclk200_fsys" ,DIV_TOP0 ,24 ,3 ), +DIV (0 ,"dout_aclk200_fsys" ,"mout_aclk200_fsys" ,DIV_TOP0 ,28 ,3 ), + +DIV (0 ,"dout_aclk333_432_gscl" ,"mout_aclk333_432_gscl" ,DIV_TOP1 ,0 ,3 ), -DIV (none,"dout_aclk66" ,"mout_aclk66" ,DIV_TOP1 ,8 ,6 ), -DIV (none,"dout_aclk266" ,"mout_aclk266" ,DIV_TOP1 ,20 ,3 ), -DIV (none,"dout_aclk166" ,"mout_aclk166" ,DIV_TOP1 ,24 ,3 ), -DIV (none,"dout_aclk333" ,"mout_aclk333" ,DIV_TOP1 ,28 ,3 ), - -DIV (none,"dout_aclk333_g2d" ,"mout_aclk333_g2d" ,DIV_TOP2 ,8 ,3 ), -DIV (none,"dout_aclk266_g2d" ,"mout_aclk266_g2d" ,DIV_TOP2 ,12 ,3 ), -DIV (none,"dout_aclk_g3d" ,"mout_aclk_g3d" ,DIV_TOP2 ,16 ,3 ), -DIV (none,"dout_aclk300_jpeg" ,"mout_aclk300_jpeg" ,DIV_TOP2 ,20 ,3 ), -DIV_A (none,"dout_aclk300_disp1" ,"mout_aclk300_disp1" , +DIV (0 ,"dout_aclk66" ,"mout_aclk66" ,DIV_TOP1 ,8 ,6 ), +DIV (0 ,"dout_aclk266" ,"mout_aclk266" ,DIV_TOP1 ,20 ,3 ), +DIV (0 ,"dout_aclk166" ,"mout_aclk166" ,DIV_TOP1 ,24 ,3 ), +DIV (0 ,"dout_aclk333" ,"mout_aclk333" ,DIV_TOP1 ,28 ,3 ), + +DIV (0 ,"dout_aclk333_g2d" ,"mout_aclk333_g2d" ,DIV_TOP2 ,8 ,3 ), +DIV (0 ,"dout_aclk266_g2d" ,"mout_aclk266_g2d" ,DIV_TOP2 ,12 ,3 ), +DIV (0 ,"dout_aclk_g3d" ,"mout_aclk_g3d" ,DIV_TOP2 ,16 ,3 ), +DIV (0 ,"dout_aclk300_jpeg" ,"mout_aclk300_jpeg" ,DIV_TOP2 ,20 ,3 ), +DIV_A (0 ,"dout_aclk300_disp1" ,"mout_aclk300_disp1" ,DIV_TOP2 ,24 ,3 ,"aclk300_disp1" ), -DIV (none,"dout_aclk300_gscl" ,"mout_aclk300_gscl" ,DIV_TOP2 ,28 ,3 ), +DIV (0 ,"dout_aclk300_gscl" ,"mout_aclk300_gscl" ,DIV_TOP2 ,28 ,3 ),/* DISP1 Block */ -DIV (none,"dout_fimd1" ,"mout_fimd1" ,DIV_DISP10 ,0 ,4 ), -DIV (none,"dout_mipi1" ,"mout_mipi1" ,DIV_DISP10 ,16 ,8 ), -DIV (none,"dout_dp1" ,"mout_dp1" ,DIV_DISP10 ,24 ,4 ), -DIV (dout_pixel,"dout_hdmi_pixel" ,"mout_pixel" ,DIV_DISP10 ,28 ,4 ), +DIV (0 ,"dout_fimd1" ,"mout_fimd1" ,DIV_DISP10 ,0 ,4 ), +DIV (0 ,"dout_mipi1" ,"mout_mipi1" ,DIV_DISP10 ,16 ,8 ), +DIV (0 ,"dout_dp1" ,"mout_dp1" ,DIV_DISP10 ,24 ,4 ), +DIV (CLK_DOUT_PIXEL ,"dout_hdmi_pixel" ,"mout_pixel" ,DIV_DISP10 ,28 ,4 ),/* Audio Block */ -DIV (none,"dout_maudio0" ,"mout_maudio0" ,DIV_MAU ,20 ,4 ), -DIV (none,"dout_maupcm0" ,"dout_maudio0" ,DIV_MAU ,24 ,8 ), +DIV (0 ,"dout_maudio0" ,"mout_maudio0" ,DIV_MAU ,20 ,4 ), +DIV (0 ,"dout_maupcm0" ,"dout_maudio0" ,DIV_MAU ,24 ,8 ),/* USB3.0 */ -DIV (none,"dout_usbphy301" ,"mout_usbd301" ,DIV_FSYS0 ,12 ,4 ), -DIV (none,"dout_usbphy300" ,"mout_usbd300" ,DIV_FSYS0 ,16 ,4 ), -DIV (none,"dout_usbd301" ,"mout_usbd301" ,DIV_FSYS0 ,20 ,4 ), -DIV (none,"dout_usbd300" ,"mout_usbd300" ,DIV_FSYS0 ,24 ,4 ), +DIV (0 ,"dout_usbphy301" ,"mout_usbd301" ,DIV_FSYS0 ,12 ,4 ), +DIV (0 ,"dout_usbphy300" ,"mout_usbd300" ,DIV_FSYS0 ,16 ,4 ), +DIV (0 ,"dout_usbd301" ,"mout_usbd301" ,DIV_FSYS0 ,20 ,4 ), +DIV (0 ,"dout_usbd300" ,"mout_usbd300" ,DIV_FSYS0 ,24 ,4 ),/* MMC */ -DIV (none,"dout_mmc0" ,"mout_mmc0" ,DIV_FSYS1 ,0 ,10 ), -DIV (none,"dout_mmc1" ,"mout_mmc1" ,DIV_FSYS1 ,10 ,10 ), -DIV (none,"dout_mmc2" ,"mout_mmc2" ,DIV_FSYS1 ,20 ,10 ), +DIV (0 ,"dout_mmc0" ,"mout_mmc0" ,DIV_FSYS1 ,0 ,10 ), +DIV (0 ,"dout_mmc1" ,"mout_mmc1" ,DIV_FSYS1 ,10 ,10 ), +DIV (0 ,"dout_mmc2" ,"mout_mmc2" ,DIV_FSYS1 ,20 ,10 ), -DIV (none,"dout_unipro" ,"mout_unipro" ,DIV_FSYS2 ,24 ,8 ), +DIV (0 ,"dout_unipro" ,"mout_unipro" ,DIV_FSYS2 ,24 ,8 ),/* UART and PWM */ -DIV (none,"dout_uart0" ,"mout_uart0" ,DIV_PERIC0 ,8 ,4 ), -DIV (none,"dout_uart1" ,"mout_uart1" ,DIV_PERIC0 ,12 ,4 ), -DIV (none,"dout_uart2" ,"mout_uart2" ,DIV_PERIC0 ,16 ,4 ), -DIV (none,"dout_uart3" ,"mout_uart3" ,DIV_PERIC0 ,20 ,4 ), -DIV (none,"dout_pwm" ,"mout_pwm" ,DIV_PERIC0 ,28 ,4 ), +DIV (0 ,"dout_uart0" ,"mout_uart0" ,DIV_PERIC0 ,8 ,4 ), +DIV (0 ,"dout_uart1" ,"mout_uart1" ,DIV_PERIC0 ,12 ,4 ), +DIV (0 ,"dout_uart2" ,"mout_uart2" ,DIV_PERIC0 ,16 ,4 ), +DIV (0 ,"dout_uart3" ,"mout_uart3" ,DIV_PERIC0 ,20 ,4 ), +DIV (0 ,"dout_pwm" ,"mout_pwm" ,DIV_PERIC0 ,28 ,4 ),/* SPI */ -DIV (none,"dout_spi0" ,"mout_spi0" ,DIV_PERIC1 ,20 ,4 ), -DIV (none,"dout_spi1" ,"mout_spi1" ,DIV_PERIC1 ,24 ,4 ), -DIV (none,"dout_spi2" ,"mout_spi2" ,DIV_PERIC1 ,28 ,4 ), +DIV (0 ,"dout_spi0" ,"mout_spi0" ,DIV_PERIC1 ,20 ,4 ), +DIV (0 ,"dout_spi1" ,"mout_spi1" ,DIV_PERIC1 ,24 ,4 ), +DIV (0 ,"dout_spi2" ,"mout_spi2" ,DIV_PERIC1 ,28 ,4 ),/* PCM */ -DIV (none,"dout_pcm1" ,"dout_audio1" ,DIV_PERIC2 ,16 ,8 ), -DIV (none,"dout_pcm2" ,"dout_audio2" ,DIV_PERIC2 ,24 ,8 ), +DIV (0 ,"dout_pcm1" ,"dout_audio1" ,DIV_PERIC2 ,16 ,8 ), +DIV (0 ,"dout_pcm2" ,"dout_audio2" ,DIV_PERIC2 ,24 ,8 ),/* Audio - I2S */ -DIV (none,"dout_i2s1" ,"dout_audio1" ,DIV_PERIC3 ,6 ,6 ), -DIV (none,"dout_i2s2" ,"dout_audio2" ,DIV_PERIC3 ,12 ,6 ), -DIV (none,"dout_audio0" ,"mout_audio0" ,DIV_PERIC3 ,20 ,4 ), -DIV (none,"dout_audio1" ,"mout_audio1" ,DIV_PERIC3 ,24 ,4 ), -DIV (none,"dout_audio2" ,"mout_audio2" ,DIV_PERIC3 ,28 ,4 ), +DIV (0 ,"dout_i2s1" ,"dout_audio1" ,DIV_PERIC3 ,6 ,6 ), +DIV (0 ,"dout_i2s2" ,"dout_audio2" ,DIV_PERIC3 ,12 ,6 ), +DIV (0 ,"dout_audio0" ,"mout_audio0" ,DIV_PERIC3 ,20 ,4 ), +DIV (0 ,"dout_audio1" ,"mout_audio1" ,DIV_PERIC3 ,24 ,4 ), +DIV (0 ,"dout_audio2" ,"mout_audio2" ,DIV_PERIC3 ,28 ,4 ),/* SPI Pre-Ratio */ -DIV (none,"dout_pre_spi0" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ), -DIV (none,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ), -DIV (none,"dout_pre_spi2" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), +DIV (0 ,"dout_pre_spi0" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ), +DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ), +DIV (0 ,"dout_pre_spi2" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), };static struct samsung_gate_clock exynos5420_gate_clks[]__initdata = {/* TODO: Re-verify the CG bits for all the gate clocks */ -GATE_A (mct,"pclk_st" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,2 ,0 ,0 ,"mct" ), +GATE_A (CLK_MCT ,"pclk_st" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,2 ,0 ,0 , +"mct" ),GATE (0 ,"aclk200_fsys" ,"mout_user_aclk200_fsys" ,GATE_BUS_FSYS0 ,9 ,CLK_IGNORE_UNUSED ,0 ),
@@ -545,217 +505,227 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),/* sclk */ -GATE (sclk_uart0,"sclk_uart0" ,"dout_uart0" , +GATE (CLK_SCLK_UART0 ,"sclk_uart0" ,"dout_uart0" ,GATE_TOP_SCLK_PERIC ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_uart1,"sclk_uart1" ,"dout_uart1" , +GATE (CLK_SCLK_UART1 ,"sclk_uart1" ,"dout_uart1" ,GATE_TOP_SCLK_PERIC ,1 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_uart2,"sclk_uart2" ,"dout_uart2" , +GATE (CLK_SCLK_UART2 ,"sclk_uart2" ,"dout_uart2" ,GATE_TOP_SCLK_PERIC ,2 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_uart3,"sclk_uart3" ,"dout_uart3" , +GATE (CLK_SCLK_UART3 ,"sclk_uart3" ,"dout_uart3" ,GATE_TOP_SCLK_PERIC ,3 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_spi0,"sclk_spi0" ,"dout_pre_spi0" , +GATE (CLK_SCLK_SPI0 ,"sclk_spi0" ,"dout_pre_spi0" ,GATE_TOP_SCLK_PERIC ,6 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_spi1,"sclk_spi1" ,"dout_pre_spi1" , +GATE (CLK_SCLK_SPI1 ,"sclk_spi1" ,"dout_pre_spi1" ,GATE_TOP_SCLK_PERIC ,7 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_spi2,"sclk_spi2" ,"dout_pre_spi2" , +GATE (CLK_SCLK_SPI2 ,"sclk_spi2" ,"dout_pre_spi2" ,GATE_TOP_SCLK_PERIC ,8 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_spdif,"sclk_spdif" ,"mout_spdif" , +GATE (CLK_SCLK_SPDIF ,"sclk_spdif" ,"mout_spdif" ,GATE_TOP_SCLK_PERIC ,9 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_pwm,"sclk_pwm" ,"dout_pwm" , +GATE (CLK_SCLK_PWM ,"sclk_pwm" ,"dout_pwm" ,GATE_TOP_SCLK_PERIC ,11 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_pcm1,"sclk_pcm1" ,"dout_pcm1" , +GATE (CLK_SCLK_PCM1 ,"sclk_pcm1" ,"dout_pcm1" ,GATE_TOP_SCLK_PERIC ,15 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_pcm2,"sclk_pcm2" ,"dout_pcm2" , +GATE (CLK_SCLK_PCM2 ,"sclk_pcm2" ,"dout_pcm2" ,GATE_TOP_SCLK_PERIC ,16 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_i2s1,"sclk_i2s1" ,"dout_i2s1" , +GATE (CLK_SCLK_I2S1 ,"sclk_i2s1" ,"dout_i2s1" ,GATE_TOP_SCLK_PERIC ,17 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_i2s2,"sclk_i2s2" ,"dout_i2s2" , +GATE (CLK_SCLK_I2S2 ,"sclk_i2s2" ,"dout_i2s2" ,GATE_TOP_SCLK_PERIC ,18 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mmc0,"sclk_mmc0" ,"dout_mmc0" , +GATE (CLK_SCLK_MMC0 ,"sclk_mmc0" ,"dout_mmc0" ,GATE_TOP_SCLK_FSYS ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mmc1,"sclk_mmc1" ,"dout_mmc1" , +GATE (CLK_SCLK_MMC1 ,"sclk_mmc1" ,"dout_mmc1" ,GATE_TOP_SCLK_FSYS ,1 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mmc2,"sclk_mmc2" ,"dout_mmc2" , +GATE (CLK_SCLK_MMC2 ,"sclk_mmc2" ,"dout_mmc2" ,GATE_TOP_SCLK_FSYS ,2 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_usbphy301,"sclk_usbphy301" ,"dout_usbphy301" , +GATE (CLK_SCLK_USBPHY301 ,"sclk_usbphy301" ,"dout_usbphy301" ,GATE_TOP_SCLK_FSYS ,7 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_usbphy300,"sclk_usbphy300" ,"dout_usbphy300" , +GATE (CLK_SCLK_USBPHY300 ,"sclk_usbphy300" ,"dout_usbphy300" ,GATE_TOP_SCLK_FSYS ,8 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_usbd300,"sclk_usbd300" ,"dout_usbd300" , +GATE (CLK_SCLK_USBD300 ,"sclk_usbd300" ,"dout_usbd300" ,GATE_TOP_SCLK_FSYS ,9 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_usbd301,"sclk_usbd301" ,"dout_usbd301" , +GATE (CLK_SCLK_USBD301 ,"sclk_usbd301" ,"dout_usbd301" ,GATE_TOP_SCLK_FSYS ,10 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_usbd301,"sclk_unipro" ,"dout_unipro" , +GATE (CLK_SCLK_USBD301 ,"sclk_unipro" ,"dout_unipro" ,SRC_MASK_FSYS ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_gscl_wa,"sclk_gscl_wa" ,"aclK333_432_gscl" , +GATE (CLK_SCLK_GSCL_WA ,"sclk_gscl_wa" ,"aclK333_432_gscl" ,GATE_TOP_SCLK_GSCL ,6 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_gscl_wb,"sclk_gscl_wb" ,"aclk333_432_gscl" , +GATE (CLK_SCLK_GSCL_WB ,"sclk_gscl_wb" ,"aclk333_432_gscl" ,GATE_TOP_SCLK_GSCL ,7 ,CLK_SET_RATE_PARENT ,0 ),/* Display */ -GATE (sclk_fimd1,"sclk_fimd1" ,"dout_fimd1" , +GATE (CLK_SCLK_FIMD1 ,"sclk_fimd1" ,"dout_fimd1" ,GATE_TOP_SCLK_DISP1 ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_mipi1,"sclk_mipi1" ,"dout_mipi1" , +GATE (CLK_SCLK_MIPI1 ,"sclk_mipi1" ,"dout_mipi1" ,GATE_TOP_SCLK_DISP1 ,3 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_hdmi,"sclk_hdmi" ,"mout_hdmi" , +GATE (CLK_SCLK_HDMI ,"sclk_hdmi" ,"mout_hdmi" ,GATE_TOP_SCLK_DISP1 ,9 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_pixel,"sclk_pixel" ,"dout_hdmi_pixel" , +GATE (CLK_SCLK_PIXEL ,"sclk_pixel" ,"dout_hdmi_pixel" ,GATE_TOP_SCLK_DISP1 ,10 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_dp1,"sclk_dp1" ,"dout_dp1" , +GATE (CLK_SCLK_DP1 ,"sclk_dp1" ,"dout_dp1" ,GATE_TOP_SCLK_DISP1 ,20 ,CLK_SET_RATE_PARENT ,0 ),/* Maudio Block */ -GATE (sclk_maudio0,"sclk_maudio0" ,"dout_maudio0" , +GATE (CLK_SCLK_MAUDIO0 ,"sclk_maudio0" ,"dout_maudio0" ,GATE_TOP_SCLK_MAU ,0 ,CLK_SET_RATE_PARENT ,0 ), -GATE (sclk_maupcm0,"sclk_maupcm0" ,"dout_maupcm0" , +GATE (CLK_SCLK_MAUPCM0 ,"sclk_maupcm0" ,"dout_maupcm0" ,GATE_TOP_SCLK_MAU ,1 ,CLK_SET_RATE_PARENT ,0 ),/* FSYS */ -GATE (tsi,"tsi" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,0 ,0 ,0 ), -GATE (pdma0,"pdma0" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,1 ,0 ,0 ), -GATE (pdma1,"pdma1" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,2 ,0 ,0 ), -GATE (ufs,"ufs" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,3 ,0 ,0 ), -GATE (rtic,"rtic" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,5 ,0 ,0 ), -GATE (mmc0,"mmc0" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,12 ,0 ,0 ), -GATE (mmc1,"mmc1" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,13 ,0 ,0 ), -GATE (mmc2,"mmc2" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,14 ,0 ,0 ), -GATE (sromc,"sromc" ,"aclk200_fsys2" , +GATE (CLK_TSI ,"tsi" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,0 ,0 ,0 ), +GATE (CLK_PDMA0 ,"pdma0" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,1 ,0 ,0 ), +GATE (CLK_PDMA1 ,"pdma1" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,2 ,0 ,0 ), +GATE (CLK_UFS ,"ufs" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,3 ,0 ,0 ), +GATE (CLK_RTIC ,"rtic" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,5 ,0 ,0 ), +GATE (CLK_MMC0 ,"mmc0" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,12 ,0 ,0 ), +GATE (CLK_MMC1 ,"mmc1" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,13 ,0 ,0 ), +GATE (CLK_MMC2 ,"mmc2" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,14 ,0 ,0 ), +GATE (CLK_SROMC ,"sromc" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,19 ,CLK_IGNORE_UNUSED ,0 ), -GATE (usbh20,"usbh20" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,20 ,0 ,0 ), -GATE (usbd300,"usbd300" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,21 ,0 ,0 ), -GATE (usbd301,"usbd301" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,28 ,0 ,0 ), +GATE (CLK_USBH20 ,"usbh20" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,20 ,0 ,0 ), +GATE (CLK_USBD300 ,"usbd300" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,21 ,0 ,0 ), +GATE (CLK_USBD301 ,"usbd301" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,28 ,0 ,0 ),/* UART */ -GATE (uart0,"uart0" ,"aclk66_peric" ,GATE_BUS_PERIC ,4 ,0 ,0 ), -GATE (uart1,"uart1" ,"aclk66_peric" ,GATE_BUS_PERIC ,5 ,0 ,0 ), -GATE_A (uart2,"uart2" ,"aclk66_peric" , +GATE (CLK_UART0 ,"uart0" ,"aclk66_peric" ,GATE_BUS_PERIC ,4 ,0 ,0 ), +GATE (CLK_UART1 ,"uart1" ,"aclk66_peric" ,GATE_BUS_PERIC ,5 ,0 ,0 ), +GATE_A (CLK_UART2 ,"uart2" ,"aclk66_peric" ,GATE_BUS_PERIC ,6 ,CLK_IGNORE_UNUSED ,0 ,"uart2" ), -GATE (uart3,"uart3" ,"aclk66_peric" ,GATE_BUS_PERIC ,7 ,0 ,0 ), +GATE (CLK_UART3 ,"uart3" ,"aclk66_peric" ,GATE_BUS_PERIC ,7 ,0 ,0 ),/* I2C */ -GATE (i2c0,"i2c0" ,"aclk66_peric" ,GATE_BUS_PERIC ,9 ,0 ,0 ), -GATE (i2c1,"i2c1" ,"aclk66_peric" ,GATE_BUS_PERIC ,10 ,0 ,0 ), -GATE (i2c2,"i2c2" ,"aclk66_peric" ,GATE_BUS_PERIC ,11 ,0 ,0 ), -GATE (i2c3,"i2c3" ,"aclk66_peric" ,GATE_BUS_PERIC ,12 ,0 ,0 ), -GATE (i2c4,"i2c4" ,"aclk66_peric" ,GATE_BUS_PERIC ,13 ,0 ,0 ), -GATE (i2c5,"i2c5" ,"aclk66_peric" ,GATE_BUS_PERIC ,14 ,0 ,0 ), -GATE (i2c6,"i2c6" ,"aclk66_peric" ,GATE_BUS_PERIC ,15 ,0 ,0 ), -GATE (i2c7,"i2c7" ,"aclk66_peric" ,GATE_BUS_PERIC ,16 ,0 ,0 ), -GATE (i2c_hdmi,"i2c_hdmi" ,"aclk66_peric" ,GATE_BUS_PERIC ,17 ,0 ,0 ), -GATE (tsadc,"tsadc" ,"aclk66_peric" ,GATE_BUS_PERIC ,18 ,0 ,0 ), +GATE (CLK_I2C0 ,"i2c0" ,"aclk66_peric" ,GATE_BUS_PERIC ,9 ,0 ,0 ), +GATE (CLK_I2C1 ,"i2c1" ,"aclk66_peric" ,GATE_BUS_PERIC ,10 ,0 ,0 ), +GATE (CLK_I2C2 ,"i2c2" ,"aclk66_peric" ,GATE_BUS_PERIC ,11 ,0 ,0 ), +GATE (CLK_I2C3 ,"i2c3" ,"aclk66_peric" ,GATE_BUS_PERIC ,12 ,0 ,0 ), +GATE (CLK_I2C4 ,"i2c4" ,"aclk66_peric" ,GATE_BUS_PERIC ,13 ,0 ,0 ), +GATE (CLK_I2C5 ,"i2c5" ,"aclk66_peric" ,GATE_BUS_PERIC ,14 ,0 ,0 ), +GATE (CLK_I2C6 ,"i2c6" ,"aclk66_peric" ,GATE_BUS_PERIC ,15 ,0 ,0 ), +GATE (CLK_I2C7 ,"i2c7" ,"aclk66_peric" ,GATE_BUS_PERIC ,16 ,0 ,0 ), +GATE (CLK_I2C_HDMI ,"i2c_hdmi" ,"aclk66_peric" ,GATE_BUS_PERIC ,17 ,0 , +0 ), +GATE (CLK_TSADC ,"tsadc" ,"aclk66_peric" ,GATE_BUS_PERIC ,18 ,0 ,0 ),/* SPI */ -GATE (spi0,"spi0" ,"aclk66_peric" ,GATE_BUS_PERIC ,19 ,0 ,0 ), -GATE (spi1,"spi1" ,"aclk66_peric" ,GATE_BUS_PERIC ,20 ,0 ,0 ), -GATE (spi2,"spi2" ,"aclk66_peric" ,GATE_BUS_PERIC ,21 ,0 ,0 ), -GATE (keyif,"keyif" ,"aclk66_peric" ,GATE_BUS_PERIC ,22 ,0 ,0 ), +GATE (CLK_SPI0 ,"spi0" ,"aclk66_peric" ,GATE_BUS_PERIC ,19 ,0 ,0 ), +GATE (CLK_SPI1 ,"spi1" ,"aclk66_peric" ,GATE_BUS_PERIC ,20 ,0 ,0 ), +GATE (CLK_SPI2 ,"spi2" ,"aclk66_peric" ,GATE_BUS_PERIC ,21 ,0 ,0 ), +GATE (CLK_KEYIF ,"keyif" ,"aclk66_peric" ,GATE_BUS_PERIC ,22 ,0 ,0 ),/* I2S */ -GATE (i2s1,"i2s1" ,"aclk66_peric" ,GATE_BUS_PERIC ,23 ,0 ,0 ), -GATE (i2s2,"i2s2" ,"aclk66_peric" ,GATE_BUS_PERIC ,24 ,0 ,0 ), +GATE (CLK_I2S1 ,"i2s1" ,"aclk66_peric" ,GATE_BUS_PERIC ,23 ,0 ,0 ), +GATE (CLK_I2S2 ,"i2s2" ,"aclk66_peric" ,GATE_BUS_PERIC ,24 ,0 ,0 ),/* PCM */ -GATE (pcm1,"pcm1" ,"aclk66_peric" ,GATE_BUS_PERIC ,25 ,0 ,0 ), -GATE (pcm2,"pcm2" ,"aclk66_peric" ,GATE_BUS_PERIC ,26 ,0 ,0 ), +GATE (CLK_PCM1 ,"pcm1" ,"aclk66_peric" ,GATE_BUS_PERIC ,25 ,0 ,0 ), +GATE (CLK_PCM2 ,"pcm2" ,"aclk66_peric" ,GATE_BUS_PERIC ,26 ,0 ,0 ),/* PWM */ -GATE (pwm,"pwm" ,"aclk66_peric" ,GATE_BUS_PERIC ,27 ,0 ,0 ), +GATE (CLK_PWM ,"pwm" ,"aclk66_peric" ,GATE_BUS_PERIC ,27 ,0 ,0 ),/* SPDIF */ -GATE (spdif,"spdif" ,"aclk66_peric" ,GATE_BUS_PERIC ,29 ,0 ,0 ), +GATE (CLK_SPDIF ,"spdif" ,"aclk66_peric" ,GATE_BUS_PERIC ,29 ,0 ,0 ), -GATE (i2c8,"i2c8" ,"aclk66_peric" ,GATE_BUS_PERIC1 ,0 ,0 ,0 ), -GATE (i2c9,"i2c9" ,"aclk66_peric" ,GATE_BUS_PERIC1 ,1 ,0 ,0 ), -GATE (i2c10,"i2c10" ,"aclk66_peric" ,GATE_BUS_PERIC1 ,2 ,0 ,0 ), +GATE (CLK_I2C8 ,"i2c8" ,"aclk66_peric" ,GATE_BUS_PERIC1 ,0 ,0 ,0 ), +GATE (CLK_I2C9 ,"i2c9" ,"aclk66_peric" ,GATE_BUS_PERIC1 ,1 ,0 ,0 ), +GATE (CLK_I2C10 ,"i2c10" ,"aclk66_peric" ,GATE_BUS_PERIC1 ,2 ,0 ,0 ), -GATE (chipid,"chipid" ,"aclk66_psgen" , +GATE (CLK_CHIPID ,"chipid" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,12 ,CLK_IGNORE_UNUSED ,0 ), -GATE (sysreg,"sysreg" ,"aclk66_psgen" , +GATE (CLK_SYSREG ,"sysreg" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,13 ,CLK_IGNORE_UNUSED ,0 ), -GATE (tzpc0,"tzpc0" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,18 ,0 ,0 ), -GATE (tzpc1,"tzpc1" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,19 ,0 ,0 ), -GATE (tzpc2,"tzpc2" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,20 ,0 ,0 ), -GATE (tzpc3,"tzpc3" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,21 ,0 ,0 ), -GATE (tzpc4,"tzpc4" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,22 ,0 ,0 ), -GATE (tzpc5,"tzpc5" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,23 ,0 ,0 ), -GATE (tzpc6,"tzpc6" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,24 ,0 ,0 ), -GATE (tzpc7,"tzpc7" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,25 ,0 ,0 ), -GATE (tzpc8,"tzpc8" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,26 ,0 ,0 ), -GATE (tzpc9,"tzpc9" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,27 ,0 ,0 ), - -GATE (hdmi_cec,"hdmi_cec" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,0 ,0 ,0 ), -GATE (seckey,"seckey" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,1 ,0 ,0 ), -GATE (wdt,"wdt" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,3 ,0 ,0 ), -GATE (rtc,"rtc" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,4 ,0 ,0 ), -GATE (tmu,"tmu" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,5 ,0 ,0 ), -GATE (tmu_gpu,"tmu_gpu" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,6 ,0 ,0 ), - -GATE (gscl0,"gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,0 ,0 ,0 ), -GATE (gscl1,"gscl1" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,1 ,0 ,0 ), -GATE (clk_3aa,"clk_3aa" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,4 ,0 ,0 ), - -GATE (smmu_3aa,"smmu_3aa" ,"aclk333_432_gscl" ,GATE_IP_GSCL1 ,2 ,0 ,0 ), -GATE (smmu_fimcl0,"smmu_fimcl0" ,"aclk333_432_gscl" , +GATE (CLK_TZPC0 ,"tzpc0" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,18 ,0 ,0 ), +GATE (CLK_TZPC1 ,"tzpc1" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,19 ,0 ,0 ), +GATE (CLK_TZPC2 ,"tzpc2" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,20 ,0 ,0 ), +GATE (CLK_TZPC3 ,"tzpc3" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,21 ,0 ,0 ), +GATE (CLK_TZPC4 ,"tzpc4" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,22 ,0 ,0 ), +GATE (CLK_TZPC5 ,"tzpc5" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,23 ,0 ,0 ), +GATE (CLK_TZPC6 ,"tzpc6" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,24 ,0 ,0 ), +GATE (CLK_TZPC7 ,"tzpc7" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,25 ,0 ,0 ), +GATE (CLK_TZPC8 ,"tzpc8" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,26 ,0 ,0 ), +GATE (CLK_TZPC9 ,"tzpc9" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,27 ,0 ,0 ), + +GATE (CLK_HDMI_CEC ,"hdmi_cec" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,0 ,0 , +0 ), +GATE (CLK_SECKEY ,"seckey" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,1 ,0 ,0 ), +GATE (CLK_WDT ,"wdt" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,3 ,0 ,0 ), +GATE (CLK_RTC ,"rtc" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,4 ,0 ,0 ), +GATE (CLK_TMU ,"tmu" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,5 ,0 ,0 ), +GATE (CLK_TMU_GPU ,"tmu_gpu" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,6 ,0 ,0 ), + +GATE (CLK_GSCL0 ,"gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,0 ,0 ,0 ), +GATE (CLK_GSCL1 ,"gscl1" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,1 ,0 ,0 ), +GATE (CLK_CLK_3AA ,"clk_3aa" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,4 ,0 ,0 ), + +GATE (CLK_SMMU_3AA ,"smmu_3aa" ,"aclk333_432_gscl" ,GATE_IP_GSCL1 ,2 ,0 , +0 ), +GATE (CLK_SMMU_FIMCL0 ,"smmu_fimcl0" ,"aclk333_432_gscl" ,GATE_IP_GSCL1 ,3 ,0 ,0 ), -GATE (smmu_fimcl1,"smmu_fimcl1" ,"aclk333_432_gscl" , +GATE (CLK_SMMU_FIMCL1 ,"smmu_fimcl1" ,"aclk333_432_gscl" ,GATE_IP_GSCL1 ,4 ,0 ,0 ), -GATE (smmu_gscl0,"smmu_gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,6 ,0 ,0 ), -GATE (smmu_gscl1,"smmu_gscl1" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,7 ,0 ,0 ), -GATE (gscl_wa,"gscl_wa" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,12 ,0 ,0 ), -GATE (gscl_wb,"gscl_wb" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,13 ,0 ,0 ), -GATE (smmu_fimcl3,"smmu_fimcl3," ,"aclk333_432_gscl" , +GATE (CLK_SMMU_GSCL0 ,"smmu_gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,6 ,0 , +0 ), +GATE (CLK_SMMU_GSCL1 ,"smmu_gscl1" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,7 ,0 , +0 ), +GATE (CLK_GSCL_WA ,"gscl_wa" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,12 ,0 ,0 ), +GATE (CLK_GSCL_WB ,"gscl_wb" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,13 ,0 ,0 ), +GATE (CLK_SMMU_FIMCL3 ,"smmu_fimcl3," ,"aclk333_432_gscl" ,GATE_IP_GSCL1 ,16 ,0 ,0 ), -GATE (fimc_lite3,"fimc_lite3" ,"aclk333_432_gscl" , +GATE (CLK_FIMC_LITE3 ,"fimc_lite3" ,"aclk333_432_gscl" ,GATE_IP_GSCL1 ,17 ,0 ,0 ), -GATE (fimd1,"fimd1" ,"aclk300_disp1" ,GATE_IP_DISP1 ,0 ,0 ,0 ), -GATE (dsim1,"dsim1" ,"aclk200_disp1" ,GATE_IP_DISP1 ,3 ,0 ,0 ), -GATE (dp1,"dp1" ,"aclk200_disp1" ,GATE_IP_DISP1 ,4 ,0 ,0 ), -GATE (mixer,"mixer" ,"aclk166" ,GATE_IP_DISP1 ,5 ,0 ,0 ), -GATE (hdmi,"hdmi" ,"aclk200_disp1" ,GATE_IP_DISP1 ,6 ,0 ,0 ), -GATE (smmu_fimd1,"smmu_fimd1" ,"aclk300_disp1" ,GATE_IP_DISP1 ,8 ,0 ,0 ), - -GATE (mfc,"mfc" ,"aclk333" ,GATE_IP_MFC ,0 ,0 ,0 ), -GATE (smmu_mfcl,"smmu_mfcl" ,"aclk333" ,GATE_IP_MFC ,1 ,0 ,0 ), -GATE (smmu_mfcr,"smmu_mfcr" ,"aclk333" ,GATE_IP_MFC ,2 ,0 ,0 ), - -GATE (g3d,"g3d" ,"aclkg3d" ,GATE_IP_G3D ,9 ,0 ,0 ), - -GATE (rotator,"rotator" ,"aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ), -GATE (jpeg,"jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,2 ,0 ,0 ), -GATE (jpeg2,"jpeg2" ,"aclk300_jpeg" ,GATE_IP_GEN ,3 ,0 ,0 ), -GATE (mdma1,"mdma1" ,"aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ), -GATE (smmu_rotator,"smmu_rotator" ,"aclk266" ,GATE_IP_GEN ,6 ,0 ,0 ), -GATE (smmu_jpeg,"smmu_jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,7 ,0 ,0 ), -GATE (smmu_mdma1,"smmu_mdma1" ,"aclk266" ,GATE_IP_GEN ,9 ,0 ,0 ), - -GATE (mscl0,"mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,0 ,0 ,0 ), -GATE (mscl1,"mscl1" ,"aclk400_mscl" ,GATE_IP_MSCL ,1 ,0 ,0 ), -GATE (mscl2,"mscl2" ,"aclk400_mscl" ,GATE_IP_MSCL ,2 ,0 ,0 ), -GATE (smmu_mscl0,"smmu_mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,8 ,0 ,0 ), -GATE (smmu_mscl1,"smmu_mscl1" ,"aclk400_mscl" ,GATE_IP_MSCL ,9 ,0 ,0 ), -GATE (smmu_mscl2,"smmu_mscl2" ,"aclk400_mscl" ,GATE_IP_MSCL ,10 ,0 ,0 ), - GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), +GATE (CLK_FIMD1 ,"fimd1" ,"aclk300_disp1" ,GATE_IP_DISP1 ,0 ,0 ,0 ), +GATE (CLK_DSIM1 ,"dsim1" ,"aclk200_disp1" ,GATE_IP_DISP1 ,3 ,0 ,0 ), +GATE (CLK_DP1 ,"dp1" ,"aclk200_disp1" ,GATE_IP_DISP1 ,4 ,0 ,0 ), +GATE (CLK_MIXER ,"mixer" ,"aclk166" ,GATE_IP_DISP1 ,5 ,0 ,0 ), +GATE (CLK_HDMI ,"hdmi" ,"aclk200_disp1" ,GATE_IP_DISP1 ,6 ,0 ,0 ), +GATE (CLK_SMMU_FIMD1 ,"smmu_fimd1" ,"aclk300_disp1" ,GATE_IP_DISP1 ,8 ,0 , +0 ), + +GATE (CLK_MFC ,"mfc" ,"aclk333" ,GATE_IP_MFC ,0 ,0 ,0 ), +GATE (CLK_SMMU_MFCL ,"smmu_mfcl" ,"aclk333" ,GATE_IP_MFC ,1 ,0 ,0 ), +GATE (CLK_SMMU_MFCR ,"smmu_mfcr" ,"aclk333" ,GATE_IP_MFC ,2 ,0 ,0 ), + +GATE (CLK_G3D ,"g3d" ,"aclkg3d" ,GATE_IP_G3D ,9 ,0 ,0 ), + +GATE (CLK_ROTATOR ,"rotator" ,"aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ), +GATE (CLK_JPEG ,"jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,2 ,0 ,0 ), +GATE (CLK_JPEG2 ,"jpeg2" ,"aclk300_jpeg" ,GATE_IP_GEN ,3 ,0 ,0 ), +GATE (CLK_MDMA1 ,"mdma1" ,"aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ), +GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"aclk266" ,GATE_IP_GEN ,6 ,0 ,0 ), +GATE (CLK_SMMU_JPEG ,"smmu_jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,7 ,0 ,0 ), +GATE (CLK_SMMU_MDMA1 ,"smmu_mdma1" ,"aclk266" ,GATE_IP_GEN ,9 ,0 ,0 ), + +GATE (CLK_MSCL0 ,"mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,0 ,0 ,0 ), +GATE (CLK_MSCL1 ,"mscl1" ,"aclk400_mscl" ,GATE_IP_MSCL ,1 ,0 ,0 ), +GATE (CLK_MSCL2 ,"mscl2" ,"aclk400_mscl" ,GATE_IP_MSCL ,2 ,0 ,0 ), +GATE (CLK_SMMU_MSCL0 ,"smmu_mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,8 ,0 , +0 ), +GATE (CLK_SMMU_MSCL1 ,"smmu_mscl1" ,"aclk400_mscl" ,GATE_IP_MSCL ,9 ,0 , +0 ), +GATE (CLK_SMMU_MSCL2 ,"smmu_mscl2" ,"aclk400_mscl" ,GATE_IP_MSCL ,10 ,0 , +0 ), +GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 , + 0), };static struct samsung_pll_clock exynos5420_plls[nr_plls]__initdata = { - [apll] =PLL (pll_2550, fout_apll,"fout_apll" ,"fin_pll" ,APLL_LOCK , + [apll] =PLL (pll_2550,CLK_FOUT_APLL ,"fout_apll" ,"fin_pll" ,APLL_LOCK ,APLL_CON0 ,NULL ), - [cpll] =PLL (pll_2550, fout_mpll,"fout_mpll" ,"fin_pll" ,MPLL_LOCK , + [cpll] =PLL (pll_2550,CLK_FOUT_MPLL ,"fout_mpll" ,"fin_pll" ,MPLL_LOCK ,MPLL_CON0 ,NULL ), - [dpll] =PLL (pll_2550, fout_dpll,"fout_dpll" ,"fin_pll" ,DPLL_LOCK , + [dpll] =PLL (pll_2550,CLK_FOUT_DPLL ,"fout_dpll" ,"fin_pll" ,DPLL_LOCK ,DPLL_CON0 ,NULL ), - [epll] =PLL (pll_2650, fout_epll,"fout_epll" ,"fin_pll" ,EPLL_LOCK , + [epll] =PLL (pll_2650,CLK_FOUT_EPLL ,"fout_epll" ,"fin_pll" ,EPLL_LOCK ,EPLL_CON0 ,NULL ), - [rpll] =PLL (pll_2650, fout_rpll,"fout_rpll" ,"fin_pll" ,RPLL_LOCK , + [rpll] =PLL (pll_2650,CLK_FOUT_RPLL ,"fout_rpll" ,"fin_pll" ,RPLL_LOCK ,RPLL_CON0 ,NULL ), - [ipll] =PLL (pll_2550, fout_ipll,"fout_ipll" ,"fin_pll" ,IPLL_LOCK , + [ipll] =PLL (pll_2550,CLK_FOUT_IPLL ,"fout_ipll" ,"fin_pll" ,IPLL_LOCK ,IPLL_CON0 ,NULL ), - [spll] =PLL (pll_2550, fout_spll,"fout_spll" ,"fin_pll" ,SPLL_LOCK , + [spll] =PLL (pll_2550,CLK_FOUT_SPLL ,"fout_spll" ,"fin_pll" ,SPLL_LOCK ,SPLL_CON0 ,NULL ), - [vpll] =PLL (pll_2550, fout_vpll,"fout_vpll" ,"fin_pll" ,VPLL_LOCK , + [vpll] =PLL (pll_2550,CLK_FOUT_VPLL ,"fout_vpll" ,"fin_pll" ,VPLL_LOCK ,VPLL_CON0 ,NULL ), - [mpll] =PLL (pll_2550, fout_mpll,"fout_mpll" ,"fin_pll" ,MPLL_LOCK , + [mpll] =PLL (pll_2550,CLK_FOUT_MPLL ,"fout_mpll" ,"fin_pll" ,MPLL_LOCK ,MPLL_CON0 ,NULL ), - [bpll] =PLL (pll_2550, fout_bpll,"fout_bpll" ,"fin_pll" ,BPLL_LOCK , + [bpll] =PLL (pll_2550,CLK_FOUT_BPLL ,"fout_bpll" ,"fin_pll" ,BPLL_LOCK ,BPLL_CON0 ,NULL ), - [kpll] =PLL (pll_2550, fout_kpll,"fout_kpll" ,"fin_pll" ,KPLL_LOCK , + [kpll] =PLL (pll_2550,CLK_FOUT_KPLL ,"fout_kpll" ,"fin_pll" ,KPLL_LOCK ,KPLL_CON0 ,NULL ), };
@@ -777,7 +747,7 @@ static void __init exynos5420_clk_init(struct device_node *np)panic ("%s: unable to determine soc\n" , __func__); } -samsung_clk_init (np, reg_base, nr_clks, +samsung_clk_init (np, reg_base,CLK_NR_CLKS , exynos5420_clk_regs,ARRAY_SIZE (exynos5420_clk_regs),NULL ,0 ); samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
Signature · 1 line
1.8.1.2
PATCH v2 10/12 ARM: exynos5440: create a DT header defining CLK IDs
In reply to Andrzej HajdaThe patch adds header file defining clock IDs.
This allows to use macros instead of magic numbers in DT bindings.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- include/dt-bindings/clock/exynos5440.h | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 include/dt-bindings/clock/exynos5440.h
include/dt-bindings/clock/exynos5440.h new file +42 -0
@@ -0,0 +1,42 @@ +/* +* Copyright (c) 2013 Samsung Electronics Co., Ltd. +* Author: Andrzej Haja <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* Device Tree binding constants for Exynos5440 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H + +#define CLK_XTAL 1 +#define CLK_ARM_CLK 2 +#define CLK_SPI_BAUD 16 +#define CLK_PB0_250 17 +#define CLK_PR0_250 18 +#define CLK_PR1_250 19 +#define CLK_B_250 20 +#define CLK_B_125 21 +#define CLK_B_200 22 +#define CLK_SATA 23 +#define CLK_USB 24 +#define CLK_GMAC0 25 +#define CLK_CS250 26 +#define CLK_PB0_250_O 27 +#define CLK_PR0_250_O 28 +#define CLK_PR1_250_O 29 +#define CLK_B_250_O 30 +#define CLK_B_125_O 31 +#define CLK_B_200_O 32 +#define CLK_SATA_O 33 +#define CLK_USB_O 34 +#define CLK_GMAC0_O 35 +#define CLK_CS250_O 36 + +/* must be greater than maximal clock id */ +#define CLK_NR_CLKS 37 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */
Signature · 1 line
1.8.1.2
PATCH v2 11/12 ARM: dts: exynos5440: convert magic numbers to macros in clock bindings
In reply to Andrzej HajdaThe patch replaces magic numbers with macros defined in DT header in exynos5440 clock bindings.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- .../devicetree/bindings/clock/exynos5440-clock.txt | 45 +++------------------- arch/arm/boot/dts/exynos5440.dtsi | 27 ++++++------- 2 files changed, 20 insertions(+), 52 deletions(-)
Documentation/devicetree/bindings/clock/exynos5440-clock.txt +6 -39
@@ -12,45 +12,12 @@ Required Properties: - #clock-cells: should be 1. -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. - - - [Core Clocks] - - Clock ID - ---------------------------- - - xtal 1 - arm_clk 2 - - [Peripheral Clock Gates] - - Clock ID - ---------------------------- - - spi_baud 16 - pb0_250 17 - pr0_250 18 - pr1_250 19 - b_250 20 - b_125 21 - b_200 22 - sata 23 - usb 24 - gmac0 25 - cs250 26 - pb0_250_o 27 - pr0_250_o 28 - pr1_250_o 29 - b_250_o 30 - b_125_o 31 - b_200_o 32 - sata_o 33 - usb_o 34 - gmac0_o 35 - cs250_o 36 +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5440.h header and can be used in device +tree sources. Example: An example of a clock controller node is listed below.
arch/arm/boot/dts/exynos5440.dtsi +14 -13
@@ -9,6 +9,7 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/clock/exynos5440.h> #include "skeleton.dtsi" / {
@@ -102,7 +103,7 @@ compatible = "samsung,exynos4210-uart"; reg = <0xB0000 0x1000>; interrupts = <0 2 0>; - clocks = <&clock 21>, <&clock 21>; + clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; clock-names = "uart", "clk_uart_baud0"; };
@@ -110,7 +111,7 @@ compatible = "samsung,exynos4210-uart"; reg = <0xC0000 0x1000>; interrupts = <0 3 0>; - clocks = <&clock 21>, <&clock 21>; + clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; clock-names = "uart", "clk_uart_baud0"; };
@@ -122,7 +123,7 @@ #size-cells = <0>; samsung,spi-src-clk = <0>; num-cs = <1>; - clocks = <&clock 21>, <&clock 16>; + clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; clock-names = "spi", "spi_busclk0"; };
@@ -158,7 +159,7 @@ interrupts = <0 5 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "i2c"; };
@@ -168,7 +169,7 @@ interrupts = <0 6 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "i2c"; };
@@ -176,7 +177,7 @@ compatible = "samsung,s3c2410-wdt"; reg = <0x110000 0x1000>; interrupts = <0 1 0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "watchdog"; };
@@ -187,7 +188,7 @@ interrupts = <0 31 4>; interrupt-names = "macirq"; phy-mode = "sgmii"; - clocks = <&clock 25>; + clocks = <&clock CLK_GMAC0>; clock-names = "stmmaceth"; };
@@ -203,7 +204,7 @@ compatible = "samsung,s3c6410-rtc"; reg = <0x130000 0x1000>; interrupts = <0 17 0>, <0 16 0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "rtc"; };
@@ -211,7 +212,7 @@ compatible = "snps,exynos5440-ahci"; reg = <0x210000 0x10000>; interrupts = <0 30 0>; - clocks = <&clock 23>; + clocks = <&clock CLK_SATA>; clock-names = "sata"; };
@@ -219,7 +220,7 @@ compatible = "samsung,exynos5440-ohci"; reg = <0x220000 0x1000>; interrupts = <0 29 0>; - clocks = <&clock 24>; + clocks = <&clock CLK_USB>; clock-names = "usbhost"; };
@@ -227,7 +228,7 @@ compatible = "samsung,exynos5440-ehci"; reg = <0x221000 0x1000>; interrupts = <0 29 0>; - clocks = <&clock 24>; + clocks = <&clock CLK_USB>; clock-names = "usbhost"; };
@@ -237,7 +238,7 @@ 0x270000 0x1000 0x271000 0x40>; interrupts = <0 20 0>, <0 21 0>, <0 22 0>; - clocks = <&clock 28>, <&clock 27>; + clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; #size-cells = <2>;
@@ -256,7 +257,7 @@ 0x272000 0x1000 0x271040 0x40>; interrupts = <0 23 0>, <0 24 0>, <0 25 0>; - clocks = <&clock 29>, <&clock 27>; + clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; #size-cells = <2>;
Signature · 1 line
1.8.1.2
PATCH v2 12/12 clk: exynos5440: replace clock ID private enums with IDs from DT header
In reply to Andrzej HajdaThe patch replaces private enum clock IDs in the driver with macros provided by the DT header.
Signed-off-by Andrzej Hajda <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- drivers/clk/samsung/clk-exynos5440.c | 81 +++++++++++++++--------------------- 1 file changed, 34 insertions(+), 47 deletions(-)
drivers/clk/samsung/clk-exynos5440.c +34 -47
@@ -9,6 +9,7 @@* Common Clock Framework support for Exynos5440 SoC. */ +#include <dt-bindings/clock/exynos5440.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h>
@@ -22,79 +23,65 @@#define CPU_CLK_STATUS 0xfc#define MISC_DOUT1 0x558 -/* -* Let each supported clock get a unique id. This id is used to lookup the clock -* for device tree based platforms. -*/ -enum exynos5440_clks { - none, xtal, arm_clk, - - spi_baud =16 , pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata, - usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o, - b_200_o, sata_o, usb_o, gmac0_o, cs250_o, - - nr_clks, -}; -/* parent clock name list */ PNAME (mout_armclk_p) = {"cplla" ,"cpllb" };PNAME (mout_spi_p) = {"div125" ,"div200" };/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[]__initdata = { -FRATE (none,"xtal" ,NULL ,CLK_IS_ROOT ,0 ), +FRATE (0 ,"xtal" ,NULL ,CLK_IS_ROOT ,0 ), };/* fixed rate clocks */ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[]__initdata = { -FRATE (none,"ppll" ,NULL ,CLK_IS_ROOT ,1000000000 ), -FRATE (none,"usb_phy0" ,NULL ,CLK_IS_ROOT ,60000000 ), -FRATE (none,"usb_phy1" ,NULL ,CLK_IS_ROOT ,60000000 ), -FRATE (none,"usb_ohci12" ,NULL ,CLK_IS_ROOT ,12000000 ), -FRATE (none,"usb_ohci48" ,NULL ,CLK_IS_ROOT ,48000000 ), +FRATE (0 ,"ppll" ,NULL ,CLK_IS_ROOT ,1000000000 ), +FRATE (0 ,"usb_phy0" ,NULL ,CLK_IS_ROOT ,60000000 ), +FRATE (0 ,"usb_phy1" ,NULL ,CLK_IS_ROOT ,60000000 ), +FRATE (0 ,"usb_ohci12" ,NULL ,CLK_IS_ROOT ,12000000 ), +FRATE (0 ,"usb_ohci48" ,NULL ,CLK_IS_ROOT ,48000000 ), };/* fixed factor clocks */ static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[]__initdata = { -FFACTOR (none,"div250" ,"ppll" ,1 ,4 ,0 ), -FFACTOR (none,"div200" ,"ppll" ,1 ,5 ,0 ), -FFACTOR (none,"div125" ,"div250" ,1 ,2 ,0 ), +FFACTOR (0 ,"div250" ,"ppll" ,1 ,4 ,0 ), +FFACTOR (0 ,"div200" ,"ppll" ,1 ,5 ,0 ), +FFACTOR (0 ,"div125" ,"div250" ,1 ,2 ,0 ), };/* mux clocks */ static struct samsung_mux_clock exynos5440_mux_clks[]__initdata = { -MUX (none,"mout_spi" , mout_spi_p,MISC_DOUT1 ,5 ,1 ), -MUX_A (arm_clk,"arm_clk" , mout_armclk_p, +MUX (0 ,"mout_spi" , mout_spi_p,MISC_DOUT1 ,5 ,1 ), +MUX_A (CLK_ARM_CLK ,"arm_clk" , mout_armclk_p,CPU_CLK_STATUS ,0 ,1 ,"armclk" ), };/* divider clocks */ static struct samsung_div_clock exynos5440_div_clks[]__initdata = { -DIV (spi_baud,"div_spi" ,"mout_spi" ,MISC_DOUT1 ,3 ,2 ), +DIV (CLK_SPI_BAUD ,"div_spi" ,"mout_spi" ,MISC_DOUT1 ,3 ,2 ), };/* gate clocks */ static struct samsung_gate_clock exynos5440_gate_clks[]__initdata = { -GATE (pb0_250,"pb0_250" ,"div250" ,CLKEN_OV_VAL ,3 ,0 ,0 ), -GATE (pr0_250,"pr0_250" ,"div250" ,CLKEN_OV_VAL ,4 ,0 ,0 ), -GATE (pr1_250,"pr1_250" ,"div250" ,CLKEN_OV_VAL ,5 ,0 ,0 ), -GATE (b_250,"b_250" ,"div250" ,CLKEN_OV_VAL ,9 ,0 ,0 ), -GATE (b_125,"b_125" ,"div125" ,CLKEN_OV_VAL ,10 ,0 ,0 ), -GATE (b_200,"b_200" ,"div200" ,CLKEN_OV_VAL ,11 ,0 ,0 ), -GATE (sata,"sata" ,"div200" ,CLKEN_OV_VAL ,12 ,0 ,0 ), -GATE (usb,"usb" ,"div200" ,CLKEN_OV_VAL ,13 ,0 ,0 ), -GATE (gmac0,"gmac0" ,"div200" ,CLKEN_OV_VAL ,14 ,0 ,0 ), -GATE (cs250,"cs250" ,"div250" ,CLKEN_OV_VAL ,19 ,0 ,0 ), -GATE (pb0_250_o,"pb0_250_o" ,"pb0_250" ,CLKEN_OV_VAL ,3 ,0 ,0 ), -GATE (pr0_250_o,"pr0_250_o" ,"pr0_250" ,CLKEN_OV_VAL ,4 ,0 ,0 ), -GATE (pr1_250_o,"pr1_250_o" ,"pr1_250" ,CLKEN_OV_VAL ,5 ,0 ,0 ), -GATE (b_250_o,"b_250_o" ,"b_250" ,CLKEN_OV_VAL ,9 ,0 ,0 ), -GATE (b_125_o,"b_125_o" ,"b_125" ,CLKEN_OV_VAL ,10 ,0 ,0 ), -GATE (b_200_o,"b_200_o" ,"b_200" ,CLKEN_OV_VAL ,11 ,0 ,0 ), -GATE (sata_o,"sata_o" ,"sata" ,CLKEN_OV_VAL ,12 ,0 ,0 ), -GATE (usb_o,"usb_o" ,"usb" ,CLKEN_OV_VAL ,13 ,0 ,0 ), -GATE (gmac0_o,"gmac0_o" ,"gmac" ,CLKEN_OV_VAL ,14 ,0 ,0 ), -GATE (cs250_o,"cs250_o" ,"cs250" ,CLKEN_OV_VAL ,19 ,0 ,0 ), +GATE (CLK_PB0_250 ,"pb0_250" ,"div250" ,CLKEN_OV_VAL ,3 ,0 ,0 ), +GATE (CLK_PR0_250 ,"pr0_250" ,"div250" ,CLKEN_OV_VAL ,4 ,0 ,0 ), +GATE (CLK_PR1_250 ,"pr1_250" ,"div250" ,CLKEN_OV_VAL ,5 ,0 ,0 ), +GATE (CLK_B_250 ,"b_250" ,"div250" ,CLKEN_OV_VAL ,9 ,0 ,0 ), +GATE (CLK_B_125 ,"b_125" ,"div125" ,CLKEN_OV_VAL ,10 ,0 ,0 ), +GATE (CLK_B_200 ,"b_200" ,"div200" ,CLKEN_OV_VAL ,11 ,0 ,0 ), +GATE (CLK_SATA ,"sata" ,"div200" ,CLKEN_OV_VAL ,12 ,0 ,0 ), +GATE (CLK_USB ,"usb" ,"div200" ,CLKEN_OV_VAL ,13 ,0 ,0 ), +GATE (CLK_GMAC0 ,"gmac0" ,"div200" ,CLKEN_OV_VAL ,14 ,0 ,0 ), +GATE (CLK_CS250 ,"cs250" ,"div250" ,CLKEN_OV_VAL ,19 ,0 ,0 ), +GATE (CLK_PB0_250_O ,"pb0_250_o" ,"pb0_250" ,CLKEN_OV_VAL ,3 ,0 ,0 ), +GATE (CLK_PR0_250_O ,"pr0_250_o" ,"pr0_250" ,CLKEN_OV_VAL ,4 ,0 ,0 ), +GATE (CLK_PR1_250_O ,"pr1_250_o" ,"pr1_250" ,CLKEN_OV_VAL ,5 ,0 ,0 ), +GATE (CLK_B_250_O ,"b_250_o" ,"b_250" ,CLKEN_OV_VAL ,9 ,0 ,0 ), +GATE (CLK_B_125_O ,"b_125_o" ,"b_125" ,CLKEN_OV_VAL ,10 ,0 ,0 ), +GATE (CLK_B_200_O ,"b_200_o" ,"b_200" ,CLKEN_OV_VAL ,11 ,0 ,0 ), +GATE (CLK_SATA_O ,"sata_o" ,"sata" ,CLKEN_OV_VAL ,12 ,0 ,0 ), +GATE (CLK_USB_O ,"usb_o" ,"usb" ,CLKEN_OV_VAL ,13 ,0 ,0 ), +GATE (CLK_GMAC0_O ,"gmac0_o" ,"gmac" ,CLKEN_OV_VAL ,14 ,0 ,0 ), +GATE (CLK_CS250_O ,"cs250_o" ,"cs250" ,CLKEN_OV_VAL ,19 ,0 ,0 ), };static struct of_device_id ext_clk_match[]__initdata = {
@@ -114,7 +101,7 @@ static void __init exynos5440_clk_init(struct device_node *np)return ; } -samsung_clk_init (np, reg_base, nr_clks,NULL ,0 ,NULL ,0 ); +samsung_clk_init (np, reg_base,CLK_NR_CLKS ,NULL ,0 ,NULL ,0 );samsung_clk_of_register_fixed_ext (exynos5440_fixed_rate_ext_clks,ARRAY_SIZE (exynos5440_fixed_rate_ext_clks), ext_clk_match);
Signature · 1 line
1.8.1.2
v2 cover clk/exynos convert clock IDs to macros
In reply to Andrzej HajdaHi Andrzej,
Quoted 64 lines · On Friday 06 of September 2013 12:12:29 Andrzej Hajda wrote:
Hi,
This patch set adds headers with defines of exynos clocks. Then it converts dts files and drivers to use macros instead of magic numbers/enums to describe clock bindings.
The patch set is based on the latest mturquette/clk-next branch.
The patches are generated by script.
I have verified random clocks by hand.
I have also tested it on exynos4 based board.This is the 2nd version of the patchset.
Changes:
- corrected devicetree mailing list,
- added comments toinclude/dt-bindings/clock/exynos4.hfor clocks present only in particular chip,
- added tab alignement in headers,
- added comment toCLK_NR_CLKS,
- added copyright headers,
- split long lines in dts,
- corrected example inbindings/clock/exynos5250-clock.txt, to point appropriate clocks.Regards
AndrzejAndrzej Hajda (12):
ARM: exynos4: create a DT header defining CLK IDs
ARM: dts: exynos4: convert magic numbers to macros in clock bindings
clk: exynos4: replace clock ID private enums with IDs from DT header
ARM: exynos5250: create a DT header defining CLK IDs
ARM: dts: exynos5250: convert magic numbers to macros in clock
bindings
clk: exynos5250: replace clock ID private enums with IDs from DT
header
ARM: exynos5420: create a DT header defining CLK IDs
ARM: dts: exynos5420: convert magic numbers to macros in clock
bindings
clk: exynos5420: replace clock ID private enums with IDs from DT
header
ARM: exynos5440: create a DT header defining CLK IDs
ARM: dts: exynos5440: convert magic numbers to macros in clock
bindings
clk: exynos5440: replace clock ID private enums with IDs from DT
header.../devicetree/bindings/clock/exynos4-clock.txt | 259 +------ .../devicetree/bindings/clock/exynos5250-clock.txt | 160 +--- .../devicetree/bindings/clock/exynos5420-clock.txt | 184 +---- .../devicetree/bindings/clock/exynos5440-clock.txt | 45 +- arch/arm/boot/dts/exynos4.dtsi | 55 +- arch/arm/boot/dts/exynos4210.dtsi | 6 +- arch/arm/boot/dts/exynos4412.dtsi | 2 +- arch/arm/boot/dts/exynos4x12.dtsi | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 92 +-- arch/arm/boot/dts/exynos5420.dtsi | 13 +- arch/arm/boot/dts/exynos5440.dtsi | 27 +- drivers/clk/samsung/clk-exynos4.c | 857 ++++++++++----------- drivers/clk/samsung/clk-exynos5250.c | 501 ++++++------ drivers/clk/samsung/clk-exynos5420.c | 648 ++++++++-------- drivers/clk/samsung/clk-exynos5440.c | 81 +- include/dt-bindings/clock/exynos4.h | 244 ++++++
Quoted 8 lines
include/dt-bindings/clock/exynos5250.h | 157 ++++ include/dt-bindings/clock/exynos5420.h | 188 +++++ include/dt-bindings/clock/exynos5440.h | 42 + 19 files changed, 1734 insertions(+), 1829 deletions(-) create mode 100644 include/dt-bindings/clock/exynos4.h create mode 100644 include/dt-bindings/clock/exynos5250.h create mode 100644 include/dt-bindings/clock/exynos5420.h create mode 100644 include/dt-bindings/clock/exynos5440.h
I believe this series should be rebased on top of my series (and possibly remaining patches touching clock numbers queued on the list):
[PATCH v2 00/16] Exynos clock clean-up for 3.12
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/22514
Otherwise, it's really nice to finally see this being cleaned up, so:
Acked-by Tomasz Figa <[email protected]>
Best regards,
Tomasz
v2 cover clk/exynos convert clock IDs to macros
Quoted 77 lines · Tomasz Figa
Hi Andrzej,
Quoted 63 lines · On Friday 06 of September 2013 12:12:29 Andrzej Hajda wrote:
Hi,
This patch set adds headers with defines of exynos clocks. Then it converts dts files and drivers to use macros instead of magic numbers/enums to describe clock bindings.
The patch set is based on the latest mturquette/clk-next branch.
The patches are generated by script.
I have verified random clocks by hand.
I have also tested it on exynos4 based board.This is the 2nd version of the patchset.
Changes:
- corrected devicetree mailing list,
- added comments toinclude/dt-bindings/clock/exynos4.hfor clocks present only in particular chip,
- added tab alignement in headers,
- added comment toCLK_NR_CLKS,
- added copyright headers,
- split long lines in dts,
- corrected example inbindings/clock/exynos5250-clock.txt, to point appropriate clocks.Regards
AndrzejAndrzej Hajda (12):
ARM: exynos4: create a DT header defining CLK IDs
ARM: dts: exynos4: convert magic numbers to macros in clock bindings
clk: exynos4: replace clock ID private enums with IDs from DT header
ARM: exynos5250: create a DT header defining CLK IDs
ARM: dts: exynos5250: convert magic numbers to macros in clock
bindings
clk: exynos5250: replace clock ID private enums with IDs from DT
header
ARM: exynos5420: create a DT header defining CLK IDs
ARM: dts: exynos5420: convert magic numbers to macros in clock
bindings
clk: exynos5420: replace clock ID private enums with IDs from DT
header
ARM: exynos5440: create a DT header defining CLK IDs
ARM: dts: exynos5440: convert magic numbers to macros in clock
bindings
clk: exynos5440: replace clock ID private enums with IDs from DT
header.../devicetree/bindings/clock/exynos4-clock.txt | 259 +------ .../devicetree/bindings/clock/exynos5250-clock.txt | 160 +--- .../devicetree/bindings/clock/exynos5420-clock.txt | 184 +---- .../devicetree/bindings/clock/exynos5440-clock.txt | 45 +- arch/arm/boot/dts/exynos4.dtsi | 55 +- arch/arm/boot/dts/exynos4210.dtsi | 6 +- arch/arm/boot/dts/exynos4412.dtsi | 2 +- arch/arm/boot/dts/exynos4x12.dtsi | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 92 +-- arch/arm/boot/dts/exynos5420.dtsi | 13 +- arch/arm/boot/dts/exynos5440.dtsi | 27 +- drivers/clk/samsung/clk-exynos4.c | 857++++++++++-----------
drivers/clk/samsung/clk-exynos5250.c
| 501 ++++++------drivers/clk/samsung/clk-exynos5420.c|
648 ++++++++--------drivers/clk/samsung/clk-exynos5440.c| 81 +-Quoted 9 lines
include/dt-bindings/clock/exynos4.h | 244 ++++++ include/dt-bindings/clock/exynos5250.h | 157 ++++ include/dt-bindings/clock/exynos5420.h | 188 +++++ include/dt-bindings/clock/exynos5440.h | 42 + 19 files changed, 1734 insertions(+), 1829 deletions(-) create mode 100644 include/dt-bindings/clock/exynos4.h create mode 100644 include/dt-bindings/clock/exynos5250.h create mode 100644 include/dt-bindings/clock/exynos5420.h create mode 100644 include/dt-bindings/clock/exynos5440.h
Quoted 8 lines
I believe this series should be rebased on top of my series (and possibly remaining patches touching clock numbers queued on the list):
[PATCH v2 00/16] Exynos clock clean-up for 3.12
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/22514Otherwise, it's really nice to finally see this being cleaned up, so:
Acked-by Tomasz Figa <[email protected]>
Well...I'm not sure changing to use macro is better or not at this moment...
- Kukjin
v2 cover clk/exynos convert clock IDs to macros
Hi Kukjin,
Quoted 104 lines · On Thursday 12 of September 2013 19:50:01 Kukjin Kim wrote:
Quoted 103 lines · Tomasz Figa
Hi Andrzej,
Quoted 85 lines · On Friday 06 of September 2013 12:12:29 Andrzej Hajda wrote:
Hi,
This patch set adds headers with defines of exynos clocks. Then it converts dts files and drivers to use macros instead of magic numbers/enums to describe clock bindings.
The patch set is based on the latest mturquette/clk-next branch.
The patches are generated by script.
I have verified random clocks by hand.
I have also tested it on exynos4 based board.This is the 2nd version of the patchset.
Changes:
- corrected devicetree mailing list,
- added comments toinclude/dt-bindings/clock/exynos4.hforclocks present only in particular chip,
- added tab alignement in headers,
- added comment toCLK_NR_CLKS,
- added copyright headers,
- split long lines in dts,
- corrected example inbindings/clock/exynos5250-clock.txt, to pointappropriate clocks.
Regards
AndrzejAndrzej Hajda (12):
ARM: exynos4: create a DT header defining CLK IDs
ARM: dts: exynos4: convert magic numbers to macros in clock bindings
clk: exynos4: replace clock ID private enums with IDs from DT header
ARM: exynos5250: create a DT header defining CLK IDs
ARM: dts: exynos5250: convert magic numbers to macros in clockbindings
clk: exynos5250: replace clock ID private enums with IDs from DT
header
ARM: exynos5420: create a DT header defining CLK IDs
ARM: dts: exynos5420: convert magic numbers to macros in clockbindings
clk: exynos5420: replace clock ID private enums with IDs from DT
header
ARM: exynos5440: create a DT header defining CLK IDs
ARM: dts: exynos5440: convert magic numbers to macros in clockbindings
clk: exynos5440: replace clock ID private enums with IDs from DT
header
.../devicetree/bindings/clock/exynos4-clock.txt | 259 +------ .../devicetree/bindings/clock/exynos5250-clock.txt | 160 +--- .../devicetree/bindings/clock/exynos5420-clock.txt | 184 +---- .../devicetree/bindings/clock/exynos5440-clock.txt | 45 +- arch/arm/boot/dts/exynos4.dtsi | 55 +- arch/arm/boot/dts/exynos4210.dtsi | 6 +- arch/arm/boot/dts/exynos4412.dtsi | 2 +- arch/arm/boot/dts/exynos4x12.dtsi | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 92 +-- arch/arm/boot/dts/exynos5420.dtsi | 13 +- arch/arm/boot/dts/exynos5440.dtsi | 27 +- drivers/clk/samsung/clk-exynos4.c | 857++++++++++-----------
drivers/clk/samsung/clk-exynos5250.c| 501 ++++++------
drivers/clk/samsung/clk-exynos5420.c| |648 ++++++++--------
drivers/clk/samsung/clk-exynos5440.c| 81 +-
Quoted 9 lines
include/dt-bindings/clock/exynos4.h | 244 ++++++ include/dt-bindings/clock/exynos5250.h | 157 ++++ include/dt-bindings/clock/exynos5420.h | 188 +++++ include/dt-bindings/clock/exynos5440.h | 42 + 19 files changed, 1734 insertions(+), 1829 deletions(-) create mode 100644 include/dt-bindings/clock/exynos4.h create mode 100644 include/dt-bindings/clock/exynos5250.h create mode 100644 include/dt-bindings/clock/exynos5420.h create mode 100644 include/dt-bindings/clock/exynos5440.hI believe this series should be rebased on top of my series (and possibly remaining patches touching clock numbers queued on the list):
[PATCH v2 00/16] Exynos clock clean-up for 3.12
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/22514
Quoted 5 lines
Quoted 2 lines
Otherwise, it's really nice to finally see this being cleaned up, so:
Acked-by Tomasz Figa <[email protected]>Well...I'm not sure changing to use macro is better or not at this moment...
It was supposed to work like this from the beginning, but the preprocessing was not available at the time our common clock framework support was merged, so a temporary solution was to use the indices directly, which is far from being easy to use and scalable.
Best regards,
Tomasz
Sylwester Nawrocki
maintainerv2 cover clk/exynos convert clock IDs to macros
In reply to Kukjin KimQuoted 1 line · Kukjin Kim
Well...I'm not sure changing to use macro is better or not at this moment...
I think it is. ;) It's really less error prone to have symbolic names instead of the plain numbers. The clock ids are defined in one place and it is more clear what a clock is by looking at symbolic name. It's especially annoying to use plain numbers where are are many clock in a single node, like 10 or more. What are you main concerns with this ?
--
Regards,
Sylwester
v2 cover clk/exynos convert clock IDs to macros
Quoting Sylwester Nawrocki (2013-09-16 07:33:45)
Quoted 8 lines · Kukjin Kim
Quoted 1 line
Well...I'm not sure changing to use macro is better or not at this moment...
I think it is. ;) It's really less error prone to have symbolic names instead of the plain numbers. The clock ids are defined in one place and it is more clear what a clock is by looking at symbolic name. It's especially annoying to use plain numbers where are are many clock in a single node, like 10 or more. What are you main concerns with this ?
I think having the symbolic names is a win for readability.
Regards,
Mike
Quoted 4 lines
--
Regards,
Sylwester
v2 cover clk/exynos convert clock IDs to macros
Quoted 8 lines · Mike Turquette
Quoting Sylwester Nawrocki (2013-09-16 07:33:45)
Quoted 7 lines · Kukjin Kim
Quoted 1 line
Well...I'm not sure changing to use macro is better or not at this moment...
I think it is. ;) It's really less error prone to have symbolic names instead of the plain numbers. The clock ids are defined in one place and it is more clear what a clock is by looking at symbolic name. It's especially annoying to use plain numbers where are are many clock in a single node, like 10 or more. What are you main concerns with this ?
Quoted 8 lines
I think having the symbolic names is a win for readability.
Regards,
MikeQuoted 3 lines
--
Regards,
Sylwester
Hi Kukjin,
Any thoughts/decisions regarding this patchset ?
Regards
Andrzej
v2 cover clk/exynos convert clock IDs to macros
In reply to Mike TurquetteQuoted 9 lines · Mike Turquette
Quoting Sylwester Nawrocki (2013-09-16 07:33:45)
Quoted 2 lines · Kukjin Kim
Quoted 1 line
Well...I'm not sure changing to use macro is better or not at this
moment...
Quoted 2 lines
I think it is. ;) It's really less error prone to have symbolic names
instead
Quoted 1 line
of the plain numbers. The clock ids are defined in one place and it is
Quoted 9 lines
more
Quoted 1 line
clear what a clock is by looking at symbolic name. It's especially
annoying
Quoted 1 line
to use plain numbers where are are many clock in a single node, like 10
or
Quoted 1 line
more. What are you main concerns with this ?
I think having the symbolic names is a win for readability.
Hmm...since Mike who is a maintainer for ccf agrees with Sylwester's opinion, so I agree. Actually, I had no strong objection on this but still I'm not sure using macro is really better because sometimes the name doesn't give readability really I think though.
Mike, can you give me your ack on clk stuff?
Thanks,
Kukjin
v2 cover clk/exynos convert clock IDs to macros
Quoting Kukjin Kim (2013-09-30 03:11:41)
Quoted 14 lines
Quoted 13 lines · Mike Turquette
Quoting Sylwester Nawrocki (2013-09-16 07:33:45)
Quoted 2 lines · Kukjin Kim
Quoted 1 line
Well...I'm not sure changing to use macro is better or not at this
moment...
Quoted 2 lines
I think it is. ;) It's really less error prone to have symbolic names
instead
Quoted 1 line
of the plain numbers. The clock ids are defined in one place and it is
more
Quoted 1 line
clear what a clock is by looking at symbolic name. It's especially
annoying
Quoted 1 line
to use plain numbers where are are many clock in a single node, like 10
Quoted 8 lines
Quoted 5 lines
or
Quoted 1 line
more. What are you main concerns with this ?
I think having the symbolic names is a win for readability.
Hmm...since Mike who is a maintainer for ccf agrees with Sylwester's opinion, so I agree. Actually, I had no strong objection on this but still I'm not sure using macro is really better because sometimes the name doesn't give readability really I think though.
Mike, can you give me your ack on clk stuff?
Yes, but I was thinking to take this change through the clk tree. The new branch based on -rc3 will be published tonight.
Let me know if it causes problems for you for me to take it.
Regards,
Mike
Quoted 3 lines
Thanks,
Kukjin
v2 cover clk/exynos convert clock IDs to macros
Quoted 29 lines · Mike Turquette
Quoting Kukjin Kim (2013-09-30 03:11:41)
Quoted 8 lines
Quoted 7 lines · Mike Turquette
Quoting Sylwester Nawrocki (2013-09-16 07:33:45)
Quoted 2 lines · Kukjin Kim
Quoted 1 line
Well...I'm not sure changing to use macro is better or not at this
moment...
Quoted 2 lines
I think it is. ;) It's really less error prone to have symbolic
names
Quoted 2 lines
Quoted 2 lines
instead
Quoted 1 line
of the plain numbers. The clock ids are defined in one place and it
is
Quoted 4 lines
Quoted 4 lines
more
Quoted 1 line
clear what a clock is by looking at symbolic name. It's especially
annoying
Quoted 1 line
to use plain numbers where are are many clock in a single node, like
10
Quoted 6 lines
Quoted 5 lines
or
Quoted 1 line
more. What are you main concerns with this ?
I think having the symbolic names is a win for readability.
Hmm...since Mike who is a maintainer for ccf agrees with Sylwester's
opinion, so I agree. Actually, I had no strong objection on this but still I'm not sure using macro is really better because sometimes the name doesn't give readability really I think though.
Quoted 1 line
Quoted 7 lines
Quoted 1 line
Mike, can you give me your ack on clk stuff?
Yes, but I was thinking to take this change through the clk tree. The new branch based on -rc3 will be published tonight.
Let me know if it causes problems for you for me to take it.
Uhm, I think dt changes can make ugly conflicts because of spread dt changing?
- Kukjin
v2 cover clk/exynos convert clock IDs to macros
Quoting Kukjin Kim (2013-10-04 19:16:56)
Quoted 30 lines
Quoted 29 lines · Mike Turquette
Quoting Kukjin Kim (2013-09-30 03:11:41)
Quoted 8 lines
Quoted 7 lines · Mike Turquette
Quoting Sylwester Nawrocki (2013-09-16 07:33:45)
Quoted 2 lines · Kukjin Kim
Quoted 1 line
Well...I'm not sure changing to use macro is better or not at this
moment...
Quoted 2 lines
I think it is. ;) It's really less error prone to have symbolic
names
Quoted 2 lines
Quoted 2 lines
instead
Quoted 1 line
of the plain numbers. The clock ids are defined in one place and it
is
Quoted 4 lines
Quoted 4 lines
more
Quoted 1 line
clear what a clock is by looking at symbolic name. It's especially
annoying
Quoted 1 line
to use plain numbers where are are many clock in a single node, like
10
Quoted 6 lines
Quoted 5 lines
or
Quoted 1 line
more. What are you main concerns with this ?
I think having the symbolic names is a win for readability.
Hmm...since Mike who is a maintainer for ccf agrees with Sylwester's
opinion, so I agree. Actually, I had no strong objection on this but still I'm not sure using macro is really better because sometimes the name doesn't give readability really I think though.
Quoted 1 line
Quoted 8 lines
Quoted 7 lines
Quoted 1 line
Mike, can you give me your ack on clk stuff?
Yes, but I was thinking to take this change through the clk tree. The new branch based on -rc3 will be published tonight.
Let me know if it causes problems for you for me to take it.
Uhm, I think dt changes can make ugly conflicts because of spread dt changing?
Sure, go ahead and take the patches then.
Acked-by Mike Turquette <[email protected]>
Regards,
Mike
Quoted 2 lines
- Kukjin
v2 cover clk/exynos convert clock IDs to macros
Quoted 32 lines · Mike Turquette
Quoting Kukjin Kim (2013-10-04 19:16:56)
Quoted 31 lines
Quoted 30 lines · Mike Turquette
Quoting Kukjin Kim (2013-09-30 03:11:41)
Quoted 6 lines
Quoted 5 lines · Mike Turquette
Quoting Sylwester Nawrocki (2013-09-16 07:33:45)
Quoted 2 lines · Kukjin Kim
Quoted 1 line
Well...I'm not sure changing to use macro is better or not at this
moment...
Quoted 1 line
I think it is. ;) It's really less error prone to have symbolic
names
Quoted 2 lines
Quoted 2 lines
instead
Quoted 1 line
of the plain numbers. The clock ids are defined in one place and it
is
Quoted 4 lines
Quoted 4 lines
more
Quoted 1 line
clear what a clock is by looking at symbolic name. It's especially
annoying
Quoted 1 line
to use plain numbers where are are many clock in a single node, like
10
Quoted 5 lines
Quoted 4 lines
or
Quoted 1 line
more. What are you main concerns with this ?
I think having the symbolic names is a win for readability.
Hmm...since Mike who is a maintainer for ccf agrees with Sylwester's
opinion, so I agree. Actually, I had no strong objection on this but still I'm not sure using macro is really better because sometimes the name doesn't give readability really I think though.
Quoted 1 line
Mike, can you give me your ack on clk stuff?
Yes, but I was thinking to take this change through the clk tree. The new branch based on -rc3 will be published tonight.
Let me know if it causes problems for you for me to take it.
Quoted 7 lines
Quoted 1 line
Uhm, I think dt changes can make ugly conflicts because of spread dt changing?
Sure, go ahead and take the patches then.
Acked-by Mike Turquette <[email protected]>Regards,
Mike
I can create patchset based on different git branch if neccessary.
Regards
Andrzej
Quoted 1 line
Quoted 1 line
- Kukjin
v2 cover clk/exynos convert clock IDs to macros
Ping
Regards
Andrzej
Quoted 47 lines · Andrzej Hajda
Quoted 32 lines · Mike Turquette
Quoting Kukjin Kim (2013-10-04 19:16:56)
Quoted 31 lines
Quoted 30 lines · Mike Turquette
Quoting Kukjin Kim (2013-09-30 03:11:41)
Quoted 6 lines
Quoted 5 lines · Mike Turquette
Quoting Sylwester Nawrocki (2013-09-16 07:33:45)
Quoted 2 lines · Kukjin Kim
Quoted 1 line
Well...I'm not sure changing to use macro is better or not at this
moment...
Quoted 1 line
I think it is. ;) It's really less error prone to have symbolic
names
Quoted 2 lines
Quoted 2 lines
instead
Quoted 1 line
of the plain numbers. The clock ids are defined in one place and it
is
Quoted 4 lines
Quoted 4 lines
more
Quoted 1 line
clear what a clock is by looking at symbolic name. It's especially
annoying
Quoted 1 line
to use plain numbers where are are many clock in a single node, like
10
Quoted 5 lines
Quoted 4 lines
or
Quoted 1 line
more. What are you main concerns with this ?
I think having the symbolic names is a win for readability.
Hmm...since Mike who is a maintainer for ccf agrees with Sylwester's
opinion, so I agree. Actually, I had no strong objection on this but still I'm not sure using macro is really better because sometimes the name doesn't give readability really I think though.
Quoted 1 line
Mike, can you give me your ack on clk stuff?
Yes, but I was thinking to take this change through the clk tree. The new branch based on -rc3 will be published tonight.
Let me know if it causes problems for you for me to take it.
Quoted 7 lines
Quoted 1 line
Uhm, I think dt changes can make ugly conflicts because of spread dt changing?
Sure, go ahead and take the patches then.
Acked-by Mike Turquette <[email protected]>Regards,
MikeI can create patchset based on different git branch if neccessary.
Regards
AndrzejQuoted 1 line
Quoted 1 line
- Kukjin
v2 cover clk/exynos convert clock IDs to macros
Quoted 49 lines · Andrzej Hajda
Ping
Regards
AndrzejQuoted 43 lines · Andrzej Hajda
Quoted 32 lines · Mike Turquette
Quoting Kukjin Kim (2013-10-04 19:16:56)
Quoted 31 lines
Quoted 30 lines · Mike Turquette
Quoting Kukjin Kim (2013-09-30 03:11:41)
Quoted 6 lines
Quoted 5 lines · Mike Turquette
Quoting Sylwester Nawrocki (2013-09-16 07:33:45)
Quoted 2 lines · Kukjin Kim
Quoted 1 line
Well...I'm not sure changing to use macro is better or not at this
moment...
Quoted 1 line
I think it is. ;) It's really less error prone to have symbolic
names
Quoted 2 lines
Quoted 2 lines
instead
Quoted 1 line
of the plain numbers. The clock ids are defined in one place and it
is
Quoted 4 lines
Quoted 4 lines
more
Quoted 1 line
clear what a clock is by looking at symbolic name. It's especially
annoying
Quoted 1 line
to use plain numbers where are are many clock in a single node, like
10
Quoted 5 lines
Quoted 4 lines
or
Quoted 1 line
more. What are you main concerns with this ?
I think having the symbolic names is a win for readability.
Hmm...since Mike who is a maintainer for ccf agrees with Sylwester's
opinion, so I agree. Actually, I had no strong objection on this but still I'm not sure using macro is really better because sometimes the name doesn't give readability really I think though.
Quoted 1 line
Mike, can you give me your ack on clk stuff?
Yes, but I was thinking to take this change through the clk tree. The new branch based on -rc3 will be published tonight.
Let me know if it causes problems for you for me to take it.
Quoted 7 lines
Quoted 1 line
Uhm, I think dt changes can make ugly conflicts because of spread dt changing?
Sure, go ahead and take the patches then.
Acked-by Mike Turquette<[email protected]>Regards,
MikeI can create patchset based on different git branch if neccessary.
Hi
Unfortunately, this changes would be merged after release of next rc1 because of too many conflicts with other DT changes in Samsung tree.
Thanks,
Kukjin