clk: keystone: Add common clock drivers

v2:
- Aligned the bindings as per the list discussion. Removed the additional parameters by usage of reg-names and additional compatible fields.
- Addressed all the comments from v1 on drivers.
- Split the series into clock drivers($subject series) and platform, dt updates. Will post that one separately.

Special thanks to Mike and Mark for the detailed review on v1.

Series is an attempt to add the clock drivers for Keystone SOCs based on common clock framework. A PLL drivers taking care of SOC PLLs and a gate control driver taking clock management for the IPs. The current Keystone based SOCs don' support dynamic power management usecases like DVFS, SOC ilde etc and hence most of the usage is limited to enabling clocks and finding the current clock rate etc.

Based on to of Mike's dt binding series [1] and tested on Keystone2 EVM.

Santosh Shilimkar (3):
clk: keystone: add Keystone PLL clock driver
clk: keystone: Add gate control clock driver
clk: keystone: Build Keystone clock drivers

 .../devicetree/bindings/clock/keystone-gate.txt    |   29 +++
 .../devicetree/bindings/clock/keystone-pll.txt     |   40 +++
 drivers/clk/Kconfig                                |    7 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/keystone/Makefile                      |    1 +
 drivers/clk/keystone/gate.c                        |  264 ++++++++++++++++++++
 drivers/clk/keystone/pll.c                         |  215 ++++++++++++++++
 7 files changed, 557 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/keystone-gate.txt
 create mode 100644 Documentation/devicetree/bindings/clock/keystone-pll.txt
 create mode 100644 drivers/clk/keystone/Makefile
 create mode 100644 drivers/clk/keystone/gate.c
 create mode 100644 drivers/clk/keystone/pll.c

1.7.9.5

Add the driver for the PLL IPs found on Keystone 2 devices. The PLL IP typically has a multiplier, a divider and a post-divider. The PLL IPs like ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where as the Main PLL is controlled by a PLL controller and memory map registers.

---
 .../devicetree/bindings/clock/keystone-pll.txt     |   40 ++++
 drivers/clk/keystone/pll.c                         |  215 ++++++++++++++++++++
 2 files changed, 255 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/keystone-pll.txt
 create mode 100644 drivers/clk/keystone/pll.c

new file mode 100644
index 0000000..59b16ab
@@ -0,0 +1,40 @@
+Status: Unstable - ABI compatibility may be broken in the future
+
+Binding for keystone PLLs. The main PLL IP typically has a multiplier,
+a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
+and PAPLL are controlled by the memory mapped register where as the Main
+PLL is controlled by a PLL controller registers along with memory mapped
+registers.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- #clock-cells : from common clock binding; shall be set to 0.
+- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
+- clocks : parent clock phandle
+- reg - pll control0 and pll multipler registers
+- reg-names : control and multiplier. The multiplier is applicable only for
+		main pll clock
+- fixed-postdiv : fixed post divider value
+
+Example:
+	mainpllclk: mainpllclk at 2310110 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,main-pll-clock";
+		clocks = <&refclkmain>;
+		reg = <0x02620350 4>, <0x02310110 4>;
+		reg-names = "control", "multiplier";
+		fixed-postdiv = <2>;
+	};
+
+	papllclk: papllclk at 2620358 {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,pll-clock";
+		clocks = <&refclkmain>;
+		clock-output-names = "pa-pll-clk";
+		reg = <0x02620358 4>;
+		reg-names = "control";
+		fixed-postdiv = <6>;
+	};

1.7.9.5

Add the driver for the clock gate control which uses PSC (Power Sleep Controller) IP on Keystone 2 based SOCs. It is responsible for enabling and disabling of the clocks for different IPs present in the SoC.

---
 .../devicetree/bindings/clock/keystone-gate.txt    |   29 +++
 drivers/clk/keystone/gate.c                        |  264 ++++++++++++++++++++
 2 files changed, 293 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/keystone-gate.txt
 create mode 100644 drivers/clk/keystone/gate.c

new file mode 100644
index 0000000..c5aa187
@@ -0,0 +1,29 @@
+Status: Unstable - ABI compatibility may be broken in the future
+
+Binding for Keystone gate control driver which uses PSC controller IP.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,keystone,psc-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : parent clock phandle
+- reg :	psc control and domain address address space
+- reg-names : psc control and domain registers
+- domain-id : psc domain id needed to check the transition state register
+
+Optional properties:
+- clock-output-names : From common clock binding to override the
+			default output clock name
+Example:
+	clkusb: clkusb {
+		#clock-cells = <0>;
+		compatible = "ti,keystone,psc-clock";
+		clocks = <&chipclk16>;
+		clock-output-names = "usb";
+		reg = <0x02350008 0xb00>, <0x02350000 0x400>;
+		reg-names = "control", "domain";
+		domain-id = <0>;
+	};

1.7.9.5

Now build the keystone common clock drivers. The build is made conditional based on COMMON_CLK_KEYSTONE

---
 drivers/clk/Kconfig           |    7 +++++++
 drivers/clk/Makefile          |    1 +
 drivers/clk/keystone/Makefile |    1 +
 3 files changed, 9 insertions(+)
 create mode 100644 drivers/clk/keystone/Makefile

index 51380d6..45c01c6 100644
@@ -87,6 +87,13 @@ config CLK_PPC_CORENET
 	  This adds the clock driver support for Freescale PowerPC corenet
 	  platforms using common clock framework.
 
+config COMMON_CLK_KEYSTONE
+	tristate "Clock drivers for Keystone based SOCs"
+	depends on ARCH_KEYSTONE && OF
+	---help---
+          Supports clock drivers for Keystone based SOCs. These SOCs have local
+	  a power sleep control module that gate the clock to the IPs and PLLs.
+
 endmenu
 
 source "drivers/clk/mvebu/Kconfig"

index 4038c2b..ec9e290 100644
@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)		+= zynq/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
+obj-$(CONFIG_COMMON_CLK_KEYSTONE)	+= keystone/
 
 obj-$(CONFIG_X86)		+= x86/
 

new file mode 100644
index 0000000..0477cf6
@@ -0,0 +1 @@
+obj-y			+= pll.o gate.o

1.7.9.5

Mike,

As aligned off-list, I will revise the series to remove the dependency with your DT bindings series which still seems to be under discussion.

Regards,
Santosh

ACK. I plan to refresh my DT bindings and make them more concise, but I still think it is wise if you do not rely on them. As we discussed you can switch over to those bindings at any point in the future if you wish.

Regards,
Mike

Sounds good.

Regards,
Santosh