mmc: Add APM X-Gene SoC SDHC controller support to Arasan SDHCI driver
Subsystems (4)
cover mmc: Add APM X-Gene SoC SDHC controller support to Arasan SDHCI driver
This patch adds support for the APM X-Gene SoC SDHC controller to Arasan SDHCI driver.
---
Loc Ho (3):
Documentation: Update Arasan SDHC documentation for the APM X-Gene
SoC SDHC DTS binding
mmc: Add APM X-Gene SoC SDHC controller support to Arasan SDHCI
driver
arm64: Add APM X-Gene SoC SDHC controller DTS entry
.../devicetree/bindings/mmc/arasan,sdhci.txt | 9 +- arch/arm64/boot/dts/apm-storm.dtsi | 8 ++ drivers/mmc/host/Kconfig | 4 +- drivers/mmc/host/sdhci-of-arasan.c | 126 ++++++++++++++++++-- 4 files changed, 134 insertions(+), 13 deletions(-)
PATCH 1/3 Documentation: Update Arasan SDHC documentation for the APM X-Gene SoC SDHC DTS binding
This patch updates Arasan SDHC documentation for the APM X-Gene SoC SDHC controller DTS binding.
--- .../devicetree/bindings/mmc/arasan,sdhci.txt | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +6 -3
@@ -8,14 +8,17 @@ Device Tree Bindings for the Arasan SDHCI Controller [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' + - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or + 'xgene,arasan,sdhci-8.9a' - reg: From mmc bindings: Register location and length. - - clocks: From clock bindings: Handles to clock inputs. - - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" - interrupts: Interrupt specifier - interrupt-parent: Phandle for the interrupt controller that services interrupts for this device. +Optional Properties: + - clocks: From clock bindings: Handles to clock inputs. + - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" + Example: sdhci at e0100000 { compatible = "arasan,sdhci-8.9a";
Signature · 1 line
1.5.5
PATCH 2/3 mmc: Add APM X-Gene SoC SDHC controller support to Arasan SDHCI driver
This patch adds support for the APM X-Gene SoC SDHC controller to Arasan SDHCI driver.
--- drivers/mmc/host/Kconfig | 4 +- drivers/mmc/host/sdhci-of-arasan.c | 126 +++++++++++++++++++++++++++++++++--- 2 files changed, 120 insertions(+), 10 deletions(-)
drivers/mmc/host/Kconfig +3 -1
@@ -108,9 +108,11 @@ config MMC_SDHCI_OF_ARASAN tristate "SDHCI OF support for the Arasan SDHCI controllers" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Arasan Secure Digital Host Controller Interface - (SDHCI). This hardware is found e.g. in Xilinx' Zynq SoC. + (SDHCI). This hardware is found e.g. in Xilinx' Zynq and X-Gene + SoC. If you have a controller with this interface, say Y or M here.
drivers/mmc/host/sdhci-of-arasan.c +117 -9
181 lines not on this page · raw message
Signature · 1 line
1.5.5
PATCH 3/3 arm64: Add APM X-Gene SoC SDHC controller DTS entry
This patch adds APM X-Gene SoC SDHC controller DTS entry.
--- arch/arm64/boot/dts/apm-storm.dtsi | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
arch/arm64/boot/dts/apm-storm.dtsi +8 -0
@@ -428,5 +428,13 @@ phys = <&phy3 0>; phy-names = "sata-phy"; }; + + sdhc0: sdhc at 1c000000 { + compatible = "xgene,arasan,sdhci-8.9a"; + reg = <0x0 0x1c000000 0x0 0x100>, + <0x0 0x1f2a0094 0x0 0x10>; + interrupts = <0x0 0x49 0x4>; + no-1-8-v; + }; }; };
Signature · 1 line
1.5.5
PATCH 2/3 mmc: Add APM X-Gene SoC SDHC controller support to Arasan SDHCI driver
In reply to Loc HoQuoted 32 lines · On Sunday 18 May 2014 01:41:57 Loc Ho wrote:
drivers/mmc/host/sdhci-of-arasan.c +21
-0@@ -34,6 +36,19 @@*/ struct sdhci_arasan_data {struct clk *clk_ahb; +struct platform_device *pdev; +void __iomem *ahb_aim_csr; +const struct sdhci_arasan_ahb_ops *ahb_ops; +}; + +/** +* struct sdhci_arasan_ahb_ops +* @init_ahb Initialize translation bus +* @xlat_addr Set up an 64-bit addressing translation +*/ +struct sdhci_arasan_ahb_ops { +int (*init_ahb)(struct sdhci_arasan_data *data); +void (*xlat_addr)(struct sdhci_arasan_data *data,u64 dma_addr); };static unsigned int sdhci_arasan_get_timeout_clock (struct sdhci_host *host)@@ -51,7 +66,21 @@ static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)return freq; } +static void sdhci_arasan_writel (struct sdhci_host *host,u32 val,int reg) +{ +struct sdhci_pltfm_host *pltfm_host =sdhci_priv (host); +struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv; + +if (reg ==SDHCI_DMA_ADDRESS ) { +if (sdhci_arasan->ahb_ops && sdhci_arasan->ahb_ops->xlat_addr) + sdhci_arasan->ahb_ops->xlat_addr(sdhci_arasan,
drivers/mmc/host/sdhci-of-arasan.c static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host) · line 86
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drivers/mmc/host/sdhci-of-arasan.c +6
-0+ sg_dma_address(host->data->sg)); + } +writel (val, host->ioaddr + reg); +} +static struct sdhci_ops sdhci_arasan_ops = { + .write_l = sdhci_arasan_writel, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .get_timeout_clock = sdhci_arasan_get_timeout_clock, };
This looks like you are doing it at the wrong place. From what I understand, you are using the AHB inbound window as a minimal IOMMU. Why don't you make this a proper IOMMU driver instead and leave the SDHCI driver unchanged?
Arnd
PATCH 2/3 mmc: Add APM X-Gene SoC SDHC controller support to Arasan SDHCI driver
Hi Arnd,
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drivers/mmc/host/sdhci-of-arasan.c +13
-0+static void sdhci_arasan_writel (struct sdhci_host *host,u32 val,int reg) +{ +struct sdhci_pltfm_host *pltfm_host =sdhci_priv (host); +struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv; + +if (reg ==SDHCI_DMA_ADDRESS ) { +if (sdhci_arasan->ahb_ops && sdhci_arasan->ahb_ops->xlat_addr) + sdhci_arasan->ahb_ops->xlat_addr (sdhci_arasan, +sg_dma_address (host->data->sg)); + } +writel (val, host->ioaddr + reg); +} +static struct sdhci_ops sdhci_arasan_ops = {
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+ .write_l =
sdhci_arasan_writel,
.get_max_clock =sdhci_pltfm_clk_get_max_clock, .get_timeout_clock =sdhci_arasan_get_timeout_clock,
};This looks like you are doing it at the wrong place. From what I understand, you are using the AHB inbound window as a minimal IOMMU. Why don't you make this a proper IOMMU driver instead and leave the SDHCI driver unchanged?
I looked at the existent iommu driver. It seems like one can install an IO MMU. The question that I have is what happen when we enable the actual IO mmu? Would this be an issue if both existed as there is only one pointer in the bus_type structure?
-Loc
PATCH 1/3 Documentation: Update Arasan SDHC documentation for the APM X-Gene SoC SDHC DTS binding
In reply to Loc HoDocumentation/devicetree/bindings/mmc/arasan,sdhci.txt Device Tree Bindings for the Arasan SDHCI Controller · line 14
Quoted 13 lines · On Sunday 18 May 2014 01:41:56 Loc Ho wrote:
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +2
-3@@ -8,14 +8,17 @@ Device Tree Bindings for the Arasan SDHCI Controller [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' + - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or + 'xgene,arasan,sdhci-8.9a' - reg: From mmc bindings: Register location and length. - - clocks: From clock bindings: Handles to clock inputs. - - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
The driver as you patch is in this version actually requires a second set of registers. As I commented there, it's probably not the best way to do things, but you also forgot to update the binding here.
Always make sure that the binding document actually documents what you implement!
Arnd
PATCH 1/3 Documentation: Update Arasan SDHC documentation for the APM X-Gene SoC SDHC DTS binding
In reply to Loc HoQuoted 13 lines · Loc Ho
This patch updates Arasan SDHC documentation for the APM X-Gene SoC SDHC controller DTS binding.
Signed-off-by Loc Ho <[email protected]>--- .../devicetree/bindings/mmc/arasan,sdhci.txt | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-)Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +0
-0
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt Device Tree Bindings for the Arasan SDHCI Controller · line 12
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Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +2
-1@@ -8,14 +8,17 @@ Device Tree Bindings for the Arasan SDHCI Controller [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' + - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or + 'xgene,arasan,sdhci-8.9a'
"xgene" is not a vendor, nor is it documented as such.
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt Device Tree Bindings for the Arasan SDHCI Controller · line 20
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Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +3
-2- reg: From mmc bindings: Register location and length. - - clocks: From clock bindings: Handles to clock inputs. - - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" - interrupts: Interrupt specifier - interrupt-parent: Phandle for the interrupt controller that services interrupts for this device. +Optional Properties: + - clocks: From clock bindings: Handles to clock inputs. + - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
Given that these used to be required, they are presumably still required in some cases?
If we're going to alter these lines, it'd be nice to clean them up at the same time (a list is not a tuple, clocks aren't just phandles).
Cheers,
Mark.
PATCH 1/3 Documentation: Update Arasan SDHC documentation for the APM X-Gene SoC SDHC DTS binding
Hi Mark,
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Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +0
-0@@ -8,14 +8,17 @@ Device Tree Bindings for the Arasan SDHCI Controller [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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Documentation/devicetree/bindings/mmc/arasan,sdhci.txt Device Tree Bindings for the Arasan SDHCI Controller · line 12
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Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +2
-1Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' + - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or + 'xgene,arasan,sdhci-8.9a'"xgene" is not a vendor, nor is it documented as such.
I will change to "apm".
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Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +0
-2- reg: From mmc bindings: Register location and length. - - clocks: From clock bindings: Handles to clock inputs. - - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" - interrupts: Interrupt specifier - interrupt-parent: Phandle for the interrupt controller that services interrupts for this device.
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Documentation/devicetree/bindings/mmc/arasan,sdhci.txt Device Tree Bindings for the Arasan SDHCI Controller · line 20
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Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +3
-0+Optional Properties: + - clocks: From clock bindings: Handles to clock inputs. + - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"Given that these used to be required, they are presumably still required in some cases?
From the driver point of view, it is optional as it no longer requires
this. But from usage point of view, if an HW requires this to work correctly, then it musts be provided.
Quoted 4 lines
If we're going to alter these lines, it'd be nice to clean them up at the same time (a list is not a tuple, clocks aren't just phandles).
I will update this.
-Loc