clockevents/clocksource : new material for 3.14

Hi Thomas and Ingo,

here is the new material for 3.14. I created a branch for Simon Horman as requested [1] where he can pull from and merged it in the clockevents/3.14 branch.

* Axel Lin removed an unused structure defining the ids for the bcm
kona driver

* Ezequiel Garcia enabled the timer divider only when the 25MHz timer
is not used for the armada 370 XP

* Jingoo Han removed a pointless platform data initialization for the
sh_mtu and sh_mtu2

* Laurent Pinchart added the clk_prepare/clk_unprepare for sh_cmt

* Linus Walleij added an useful warning in clk_of when no clocks are
found while the old behavior was to silently hang at boot time

* Maxime Ripard added the high speed timer drivers for the Allwinner
SoCs (A10, A13, A20). He increased the rating, shared the irq across all available cpus and fixed the clockevent's irq initialization for the sun4i

* Michael Opdenacker removed the usage of the IRQF_DISABLED for the
all the timers driver located in drivers/clocksource

* Stephen Boyd switched to sched_clock_register for the
arm_global_timer, cadence_ttc, sun4i and orion timers

Resolved conflicts:

* (31f8ad387) "sun7i: a20: Add support for the High Speed Timers" and
(428abbb8) "Enable the I2C controllers"

* (67905540) "clocksource: Add Allwinner SoCs HS timers driver" and
(b788beda) "Order Kconfig options alphabetically"

Thanks and happy new year !

-- Daniel

[1] http://www.spinics.net/lists/linux-sh/msg26645.html

-------------------------------------------------------------------------

The following changes since commit 0e6601eee039893a3f6420596ae4588d90d13cbe:

Merge branch 'timers/posix-timers-for-tip-v2' of
git://git.kernel.org/pub/scm/linux/kernel/git/frederic/linux-dynticks
into timers/core (2013-12-10 12:32:36 +0100)

are available in the git repository at:

git://git.linaro.org/people/daniel.lezcano/linux.git clockevents/3.14

for you to fetch changes up to 98aefbe72ec6015f90fe045ed16c5cf755da283d:

Merge branch 'clockevents/for-Simon-3.13-rc2' into clockevents/3.14
(2013-12-18 15:14:36 +0100)

----------------------------------------------------------------

Axel Lin (1):
clocksource: bcm_kona_timer: Remove unused bcm_timer_ids

Daniel Lezcano (1):
Merge branch 'clockevents/for-Simon-3.13-rc2' into clockevents/3.14

Ezequiel Garcia (1):
clocksource: armada-370-xp: Enable timer divider only when needed

Jingoo Han (2):
clocksource: sh_tmu: Remove unnecessary platform_set_drvdata()
clocksource: sh_mtu2: Remove unnecessary platform_set_drvdata()

Laurent Pinchart (1):
clocksource: sh_cmt: Add clk_prepare/unprepare support

Linus Walleij (1):
clocksource: clksrc-of: Warn if no clock sources are found

Maxime Ripard (7):
clockevent: sun4i: Fill the irq field in the clockevent structure
clocksource: sun4i: Change CPU mask to cpu_possible_mask
clocksource: sun4i: Increase a bit the clock event and sources rating
clocksource: Add Allwinner SoCs HS timers driver
ARM: sun5i: a10s: Add support for the High Speed Timers
ARM: sun5i: a13: Add support for the High Speed Timers
ARM: sun7i: a20: Add support for the High Speed Timers

Michael Opdenacker (3):
clocksource: misc drivers: Remove deprecated IRQF_DISABLED
clocksource: tegra: Remove deprecated IRQF_DISABLED
clocksource: vt8500: Remove deprecated IRQF_DISABLED

Stephen Boyd (4):
clocksource: arm_global_timer: Switch to sched_clock_register()
clocksource: cadence_ttc_timer: Switch to sched_clock_register()
clocksource: sun4i: Switch to sched_clock_register()
clocksource: orion: Switch to sched_clock_register()

  .../bindings/timer/allwinner,sun5i-a13-hstimer.txt |   22 +++
  arch/arm/boot/dts/sun5i-a10s.dtsi                  |    7 +
  arch/arm/boot/dts/sun5i-a13.dtsi                   |    7 +
  arch/arm/boot/dts/sun7i-a20.dtsi                   |   10 +
  arch/arm/mach-sunxi/Kconfig                        |    1 +
  drivers/clocksource/Kconfig                        |    4 +
  drivers/clocksource/Makefile                       |    1 +
  drivers/clocksource/arm_global_timer.c             |    4 +-
  drivers/clocksource/bcm_kona_timer.c               |    6 -
  drivers/clocksource/cadence_ttc_timer.c            |    7 +-
  drivers/clocksource/clksrc-of.c                    |    4 +
  drivers/clocksource/cs5535-clockevt.c              |    2 +-
  drivers/clocksource/dw_apb_timer.c                 |    3 +-
  drivers/clocksource/nomadik-mtu.c                  |    2 +-
  drivers/clocksource/samsung_pwm_timer.c            |    2 +-
  drivers/clocksource/sh_cmt.c                       |   23 ++-
  drivers/clocksource/sh_mtu2.c                      |    4 +-
  drivers/clocksource/sh_tmu.c                       |    4 +-
  drivers/clocksource/sun4i_timer.c                  |   11 +-
  drivers/clocksource/tegra20_timer.c                |    2 +-
  drivers/clocksource/time-armada-370-xp.c           |   18 +-
  drivers/clocksource/time-orion.c                   |    4 +-
  drivers/clocksource/timer-sun5i.c                  |  192 
++++++++++++++++++++
  drivers/clocksource/vt8500_timer.c                 |    2 +-
  24 files changed, 295 insertions(+), 47 deletions(-)

create mode 100644
Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
create mode 100644 drivers/clocksource/timer-sun5i.c

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From: Maxime Ripard <[email protected]>

The clock event structure irq field was not filled previously to the interrupt we're using.

This was resulting in the timer not being used at all when using a configuration with SMP enabled on a system with several CPUs, and with the cpumask set to the cpu_possible_mask.

---
 drivers/clocksource/sun4i_timer.c |    1 +
 1 file changed, 1 insertion(+)

index 2fb4695..a7f492e 100644
@@ -188,6 +188,7 @@ static void __init sun4i_timer_init(struct device_node *node)
 	writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 
 	sun4i_clockevent.cpumask = cpumask_of(0);
+	sun4i_clockevent.irq = irq;
 
 	clockevents_config_and_register(&sun4i_clockevent, rate,
 					TIMER_SYNC_TICKS, 0xffffffff);

1.7.9.5

From: Maxime Ripard <[email protected]>

The interrupt for the timer is a shared processor interrupt, so any CPU found in the system can handle it. Switch to our cpumask to cpu_possible_mask instead of cpumask_of(0).

---
 drivers/clocksource/sun4i_timer.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index a7f492e..6a76b4e 100644
@@ -187,7 +187,7 @@ static void __init sun4i_timer_init(struct device_node *node)
 	val = readl(timer_base + TIMER_IRQ_EN_REG);
 	writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 
-	sun4i_clockevent.cpumask = cpumask_of(0);
+	sun4i_clockevent.cpumask = cpu_possible_mask;
 	sun4i_clockevent.irq = irq;
 
 	clockevents_config_and_register(&sun4i_clockevent, rate,

1.7.9.5

From: Maxime Ripard <[email protected]>

We want to keep this driver as the default provider of the clock events and source, yet some other driver might fit in the "desired" category of ratings. Hence, we need to increase a bit the rating so that we can have more flexibility in the ratings we choose.

---
 drivers/clocksource/sun4i_timer.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 6a76b4e..d7a1a1a 100644
@@ -114,7 +114,7 @@ static int sun4i_clkevt_next_event(unsigned long evt,
 
 static struct clock_event_device sun4i_clockevent = {
 	.name = "sun4i_tick",
-	.rating = 300,
+	.rating = 350,
 	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 	.set_mode = sun4i_clkevt_mode,
 	.set_next_event = sun4i_clkevt_next_event,

@@ -172,7 +172,7 @@ static void __init sun4i_timer_init(struct device_node *node)
 
 	setup_sched_clock(sun4i_timer_sched_read, 32, rate);
 	clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
-			      rate, 300, 32, clocksource_mmio_readl_down);
+			      rate, 350, 32, clocksource_mmio_readl_down);
 
 	ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
 

1.7.9.5

From: Maxime Ripard <[email protected]>

Most of the Allwinner SoCs (at this time, all but the A10) also have a High Speed timers that are not using the 24MHz oscillator as a source but rather the AHB clock running much faster.

The IP is slightly different between the A10s/A13 and the one used in the A20/A31, since the latter have 4 timers available, while the former have only 2 of them.

[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
alphabetically"

---
 .../bindings/timer/allwinner,sun5i-a13-hstimer.txt |   22 +++
 arch/arm/mach-sunxi/Kconfig                        |    1 +
 drivers/clocksource/Kconfig                        |    4 +
 drivers/clocksource/Makefile                       |    1 +
 drivers/clocksource/timer-sun5i.c                  |  192 ++++++++++++++++++++
 5 files changed, 220 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
 create mode 100644 drivers/clocksource/timer-sun5i.c

new file mode 100644
index 0000000..7c26154
@@ -0,0 +1,22 @@
+Allwinner SoCs High Speed Timer Controller
+
+Required properties:
+
+- compatible :	should be "allwinner,sun5i-a13-hstimer" or
+		"allwinner,sun7i-a20-hstimer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts :	The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
+		one)
+- clocks: phandle to the source clock (usually the AHB clock)
+
+Example:
+
+timer at 01c60000 {
+	compatible = "allwinner,sun7i-a20-hstimer";
+	reg = <0x01c60000 0x1000>;
+	interrupts = <0 51 1>,
+		     <0 52 1>,
+		     <0 53 1>,
+		     <0 54 1>;
+	clocks = <&ahb1_gates 19>;
+};

index c9e72c8..bce0d42 100644
@@ -12,3 +12,4 @@ config ARCH_SUNXI
 	select PINCTRL_SUNXI
 	select SPARSE_IRQ
 	select SUN4I_TIMER
+	select SUN5I_HSTIMER

index bdb953e..884eeff 100644
@@ -37,6 +37,10 @@ config SUN4I_TIMER
 	select CLKSRC_MMIO
 	bool
 
+config SUN5I_HSTIMER
+	select CLKSRC_MMIO
+	bool
+
 config VT8500_TIMER
 	bool
 

index 33621ef..358358d 100644
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_MOXART)	+= moxart_timer.o
 obj-$(CONFIG_ARCH_MXS)		+= mxs_timer.o
 obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o
 obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o
+obj-$(CONFIG_SUN5I_HSTIMER)	+= timer-sun5i.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)	+= vt8500_timer.o
 obj-$(CONFIG_ARCH_NSPIRE)	+= zevio-timer.o

1.7.9.5

From: Maxime Ripard <[email protected]>

The Allwinner A10s has support for two high speed timers. Now that we have a driver to support it, we can enable them in the device tree.

---
 arch/arm/boot/dts/sun5i-a10s.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

index 5247674..e674c94 100644
@@ -332,5 +332,12 @@
 			clock-frequency = <100000>;
 			status = "disabled";
 		};
+
+		timer at 01c60000 {
+			compatible = "allwinner,sun5i-a13-hstimer";
+			reg = <0x01c60000 0x1000>;
+			interrupts = <82>, <83>;
+			clocks = <&ahb_gates 28>;
+		};
 	};
 };

1.7.9.5

From: Maxime Ripard <[email protected]>

The Allwinner A13 has support for two high speed timers. Now that we have a driver to support it, we can enable them in the device tree.

---
 arch/arm/boot/dts/sun5i-a13.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

index ce8ef2a..1ccd75d 100644
@@ -273,5 +273,12 @@
 			clock-frequency = <100000>;
 			status = "disabled";
 		};
+
+		timer at 01c60000 {
+			compatible = "allwinner,sun5i-a13-hstimer";
+			reg = <0x01c60000 0x1000>;
+			interrupts = <82>, <83>;
+			clocks = <&ahb_gates 28>;
+		};
 	};
 };

1.7.9.5

From: Maxime Ripard <[email protected]>

The Allwinner A20 has support for four high speed timers. Apart for the number of timers (4 vs 2), it's basically the same logic than the high speed timers found in the sun5i chips.

Now that we have a driver to support it, we can enable them in the device tree.

[dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"

---
 arch/arm/boot/dts/sun7i-a20.dtsi |   10 ++++++++++
 1 file changed, 10 insertions(+)

index e46cfed..ee6cec7 100644
@@ -395,6 +395,16 @@
 			status = "disabled";
 		};
 
+		hstimer at 01c60000 {
+			compatible = "allwinner,sun7i-a20-hstimer";
+			reg = <0x01c60000 0x1000>;
+			interrupts = <0 81 1>,
+				     <0 82 1>,
+				     <0 83 1>,
+				     <0 84 1>;
+			clocks = <&ahb_gates 28>;
+		};
+
 		gic: interrupt-controller at 01c81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,

1.7.9.5

From: Stephen Boyd <[email protected]>

The 32 bit sched_clock interface now supports 64 bits. Upgrade to the 64 bit function to allow us to remove the 32 bit registration interface. While we're here increase the number of bits that sched_clock can handle to 64 to make full use of the counter.

---
 drivers/clocksource/arm_global_timer.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index c639b1a..0fc31d0 100644
@@ -202,7 +202,7 @@ static struct clocksource gt_clocksource = {
 };
 
 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-static u32 notrace gt_sched_clock_read(void)
+static u64 notrace gt_sched_clock_read(void)
 {
 	return gt_counter_read();
 }

@@ -217,7 +217,7 @@ static void __init gt_clocksource_init(void)
 	writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
 
 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-	setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate);
+	sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
 #endif
 	clocksource_register_hz(&gt_clocksource, gt_clk_rate);
 }

1.7.9.5

From: Stephen Boyd <[email protected]>

The 32 bit sched_clock interface now supports 64 bits. Upgrade to the 64 bit function to allow us to remove the 32 bit registration interface.

---
 drivers/clocksource/cadence_ttc_timer.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index b2bb3a4b..b865b4e 100644
@@ -158,7 +158,7 @@ static cycle_t __ttc_clocksource_read(struct clocksource *cs)
 				TTC_COUNT_VAL_OFFSET);
 }
 
-static u32 notrace ttc_sched_clock_read(void)
+static u64 notrace ttc_sched_clock_read(void)
 {
 	return __raw_readl(ttc_sched_clock_val_reg);
 }

@@ -306,7 +306,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
 	}
 
 	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
-	setup_sched_clock(ttc_sched_clock_read, 16,
+	sched_clock_register(ttc_sched_clock_read, 16,
 			clk_get_rate(ttccs->ttc.clk) / PRESCALE);
 }
 

1.7.9.5

From: Stephen Boyd <[email protected]>

The 32 bit sched_clock interface now supports 64 bits. Upgrade to the 64 bit function to allow us to remove the 32 bit registration interface. While we're here, mark the sched_clock function as notrace to prevent ftrace recursion crashes.

---
 drivers/clocksource/sun4i_timer.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index d7a1a1a..1911874 100644
@@ -138,7 +138,7 @@ static struct irqaction sun4i_timer_irq = {
 	.dev_id = &sun4i_clockevent,
 };
 
-static u32 sun4i_timer_sched_read(void)
+static u64 notrace sun4i_timer_sched_read(void)
 {
 	return ~readl(timer_base + TIMER_CNTVAL_REG(1));
 }

@@ -170,7 +170,7 @@ static void __init sun4i_timer_init(struct device_node *node)
 	       TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
 	       timer_base + TIMER_CTL_REG(1));
 
-	setup_sched_clock(sun4i_timer_sched_read, 32, rate);
+	sched_clock_register(sun4i_timer_sched_read, 32, rate);
 	clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
 			      rate, 350, 32, clocksource_mmio_readl_down);
 

1.7.9.5

From: Stephen Boyd <[email protected]>

The 32 bit sched_clock interface now supports 64 bits. Upgrade to the 64 bit function to allow us to remove the 32 bit registration interface.

---
 drivers/clocksource/time-orion.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 9c7f018..2006622 100644
@@ -53,7 +53,7 @@ EXPORT_SYMBOL(orion_timer_ctrl_clrset);
 /*
  * Free-running clocksource handling.
  */
-static u32 notrace orion_read_sched_clock(void)
+static u64 notrace orion_read_sched_clock(void)
 {
 	return ~readl(timer_base + TIMER0_VAL);
 }

@@ -135,7 +135,7 @@ static void __init orion_timer_init(struct device_node *np)
 	clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource",
 			      clk_get_rate(clk), 300, 32,
 			      clocksource_mmio_readl_down);
-	setup_sched_clock(orion_read_sched_clock, 32, clk_get_rate(clk));
+	sched_clock_register(orion_read_sched_clock, 32, clk_get_rate(clk));
 
 	/* setup timer1 as clockevent timer */
 	if (setup_irq(irq, &orion_clkevt_irq))

1.7.9.5

From: Linus Walleij <[email protected]>

Many platforms rely on clocksource_of_init() being implicitly called for registering clock sources and will get zero warnings if no working clock source is available. Let's print a critical error message if no clock source is found.

---
 drivers/clocksource/clksrc-of.c |    4 ++++
 1 file changed, 4 insertions(+)

index 35639cf4..a30b42c 100644
@@ -28,6 +28,7 @@ void __init clocksource_of_init(void)
 	struct device_node *np;
 	const struct of_device_id *match;
 	clocksource_of_init_fn init_func;
+	unsigned clocksources = 0;
 
 	for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
 		if (!of_device_is_available(np))

@@ -36,5 +37,8 @@ void __init clocksource_of_init(void)
 		init_func = match->data;
 		init_func(np);
 		of_node_put(np);
+		clocksources++;
 	}
+	if (!clocksources)
+		pr_crit("%s: no matching clocksources found\n", __func__);
 }

1.7.9.5

From: Ezequiel Garcia <[email protected]>

The current code sets the timer divider bits always. However, when the 25 MHz timer is enabled, this is not needed and has no effect. As this causes some confusion, rework the code so the divider is set only when needed, i.e. when the 25 MHz timer is not in use.

---
 drivers/clocksource/time-armada-370-xp.c |   18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

index d8e47e5..0450f6b 100644
@@ -76,6 +76,7 @@
 static void __iomem *timer_base, *local_base;
 static unsigned int timer_clk;
 static bool timer25Mhz = true;
+static u32 enable_mask;
 
 /*
  * Number of timer ticks per jiffy.

@@ -121,8 +122,7 @@ armada_370_xp_clkevt_next_event(unsigned long delta,
 	/*
 	 * Enable the timer.
 	 */
-	local_timer_ctrl_clrset(TIMER0_RELOAD_EN,
-				TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT));
+	local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
 	return 0;
 }
 

@@ -141,9 +141,7 @@ armada_370_xp_clkevt_mode(enum clock_event_mode mode,
 		/*
 		 * Enable timer.
 		 */
-		local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN |
-					   TIMER0_EN |
-					   TIMER0_DIV(TIMER_DIVIDER_SHIFT));
+		local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
 	} else {
 		/*
 		 * Disable timer.

@@ -240,10 +238,13 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
 	WARN_ON(!timer_base);
 	local_base = of_iomap(np, 1);
 
-	if (timer25Mhz)
+	if (timer25Mhz) {
 		set = TIMER0_25MHZ;		
-	else
+		enable_mask = TIMER0_EN;
+	} else {
 		clr = TIMER0_25MHZ;
+		enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
+	}
 	timer_ctrl_clrset(clr, set);
 	local_timer_ctrl_clrset(clr, set);
 

@@ -267,8 +268,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
 	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 
-	timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN |
-			     TIMER0_DIV(TIMER_DIVIDER_SHIFT));
+	timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
 
 	clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
 			      "armada_370_xp_clocksource",

1.7.9.5

From: Jingoo Han <[email protected]>

The driver core clears the driver data to NULL after device_release or on probe failure. Thus, it is not needed to manually clear the device driver data to NULL.

---
 drivers/clocksource/sh_tmu.c |    1 -
 1 file changed, 1 deletion(-)

index 78b8dae..54ab475 100644
@@ -509,7 +509,6 @@ static int sh_tmu_probe(struct platform_device *pdev)
 	ret = sh_tmu_setup(p, pdev);
 	if (ret) {
 		kfree(p);
-		platform_set_drvdata(pdev, NULL);
 		pm_runtime_idle(&pdev->dev);
 		return ret;
 	}

1.7.9.5

From: Jingoo Han <[email protected]>

The driver core clears the driver data to NULL after device_release or on probe failure. Thus, it is not needed to manually clear the device driver data to NULL.

---
 drivers/clocksource/sh_mtu2.c |    1 -
 1 file changed, 1 deletion(-)

index 4aac9ee..f02648e 100644
@@ -346,7 +346,6 @@ static int sh_mtu2_probe(struct platform_device *pdev)
 	ret = sh_mtu2_setup(p, pdev);
 	if (ret) {
 		kfree(p);
-		platform_set_drvdata(pdev, NULL);
 		pm_runtime_idle(&pdev->dev);
 		return ret;
 	}

1.7.9.5

From: Michael Opdenacker <[email protected]>

This patch removes the use of the IRQF_DISABLED flag

It's a NOOP since 2.6.35 and it will be removed one day.

[dlezcano] : slightly changed the changelog

---
 drivers/clocksource/cadence_ttc_timer.c |    3 +--
 drivers/clocksource/cs5535-clockevt.c   |    2 +-
 drivers/clocksource/dw_apb_timer.c      |    3 +--
 drivers/clocksource/nomadik-mtu.c       |    2 +-
 drivers/clocksource/samsung_pwm_timer.c |    2 +-
 drivers/clocksource/sh_cmt.c            |    3 +--
 drivers/clocksource/sh_mtu2.c           |    3 +--
 drivers/clocksource/sh_tmu.c            |    3 +--
 8 files changed, 8 insertions(+), 13 deletions(-)

index b865b4e..8c7382b 100644
@@ -388,8 +388,7 @@ static void __init ttc_setup_clockevent(struct clk *clk,
 	__raw_writel(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
 
 	err = request_irq(irq, ttc_clock_event_interrupt,
-			  IRQF_DISABLED | IRQF_TIMER,
-			  ttcce->ce.name, ttcce);
+			  IRQF_TIMER, ttcce->ce.name, ttcce);
 	if (WARN_ON(err)) {
 		kfree(ttcce);
 		return;

index ea21048..db21052 100644
@@ -131,7 +131,7 @@ static irqreturn_t mfgpt_tick(int irq, void *dev_id)
 
 static struct irqaction mfgptirq  = {
 	.handler = mfgpt_tick,
-	.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
+	.flags = IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
 	.name = DRV_NAME,
 };
 

index e54ca10..f3656a6 100644
@@ -243,8 +243,7 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
 	dw_ced->irqaction.dev_id	= &dw_ced->ced;
 	dw_ced->irqaction.irq		= irq;
 	dw_ced->irqaction.flags		= IRQF_TIMER | IRQF_IRQPOLL |
-					  IRQF_NOBALANCING |
-					  IRQF_DISABLED;
+					  IRQF_NOBALANCING;
 
 	dw_ced->eoi = apbt_eoi;
 	err = setup_irq(irq, &dw_ced->irqaction);

index ed7b73b..152a3f3 100644
@@ -187,7 +187,7 @@ static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction nmdk_timer_irq = {
 	.name		= "Nomadik Timer Tick",
-	.flags		= IRQF_DISABLED | IRQF_TIMER,
+	.flags		= IRQF_TIMER,
 	.handler	= nmdk_timer_interrupt,
 	.dev_id		= &nmdk_clkevt,
 };

index 85082e8..5645cfc 100644
@@ -264,7 +264,7 @@ static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
 
 static struct irqaction samsung_clock_event_irq = {
 	.name		= "samsung_time_irq",
-	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
 	.handler	= samsung_clock_event_isr,
 	.dev_id		= &time_event_device,
 };

index 0965e98..c618633 100644
@@ -726,8 +726,7 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
 	p->irqaction.name = dev_name(&p->pdev->dev);
 	p->irqaction.handler = sh_cmt_interrupt;
 	p->irqaction.dev_id = p;
-	p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
-			     IRQF_IRQPOLL  | IRQF_NOBALANCING;
+	p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
 
 	/* get hold of clock */
 	p->clk = clk_get(&p->pdev->dev, "cmt_fck");

index f02648e..b6a56b1 100644
@@ -302,8 +302,7 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
 	p->irqaction.handler = sh_mtu2_interrupt;
 	p->irqaction.dev_id = p;
 	p->irqaction.irq = irq;
-	p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
-			     IRQF_IRQPOLL  | IRQF_NOBALANCING;
+	p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
 
 	/* get hold of clock */
 	p->clk = clk_get(&p->pdev->dev, "mtu2_fck");

index 54ab475..fc752f7 100644
@@ -462,8 +462,7 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
 	p->irqaction.handler = sh_tmu_interrupt;
 	p->irqaction.dev_id = p;
 	p->irqaction.irq = irq;
-	p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
-			     IRQF_IRQPOLL  | IRQF_NOBALANCING;
+	p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
 
 	/* get hold of clock */
 	p->clk = clk_get(&p->pdev->dev, "tmu_fck");

1.7.9.5

From: Michael Opdenacker <[email protected]>

This patch removes the use of the IRQF_DISABLED flag.

It's a NOOP since 2.6.35 and it will be removed one day.

[dlezcano] : slightly changed the changelog

---
 drivers/clocksource/tegra20_timer.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 6428492..d1869f0 100644
@@ -149,7 +149,7 @@ static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction tegra_timer_irq = {
 	.name		= "timer0",
-	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
+	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
 	.handler	= tegra_timer_interrupt,
 	.dev_id		= &tegra_clockevent,
 };

1.7.9.5

From: Michael Opdenacker <[email protected]>

This patch removes the use of the IRQF_DISABLED flag.

It's a NOOP since 2.6.35 and it will be removed one day.

[dlezcano] : slightly changed the changelog

---
 drivers/clocksource/vt8500_timer.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index ad3c0e8..1098ed3 100644
@@ -124,7 +124,7 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction irq = {
 	.name    = "vt8500_timer",
-	.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.flags   = IRQF_TIMER | IRQF_IRQPOLL,
 	.handler = vt8500_timer_interrupt,
 	.dev_id  = &clockevent,
 };

1.7.9.5

From: Axel Lin <[email protected]>

bcm_timer_ids is no longer used after converting to CLOCKSOURCE_OF_DECLARE.

---
 drivers/clocksource/bcm_kona_timer.c |    6 ------
 1 file changed, 6 deletions(-)

index 0d7d8c3..5176e76 100644
@@ -98,12 +98,6 @@ kona_timer_get_counter(void *timer_base, uint32_t *msw, uint32_t *lsw)
 	return;
 }
 
-static const struct of_device_id bcm_timer_ids[] __initconst = {
-	{.compatible = "brcm,kona-timer"},
-	{.compatible = "bcm,kona-timer"}, /* deprecated name */
-	{},
-};
-
 static void __init kona_timers_init(struct device_node *node)
 {
 	u32 freq;

1.7.9.5

From: Laurent Pinchart <[email protected]>

Prepare the clock at probe time, as there is no other appropriate place in the driver where we're allowed to sleep.

---
 drivers/clocksource/sh_cmt.c |   20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

index 0965e98..940341a 100644
@@ -634,12 +634,18 @@ static int sh_cmt_clock_event_next(unsigned long delta,
 
 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 {
-	pm_genpd_syscore_poweroff(&ced_to_sh_cmt(ced)->pdev->dev);
+	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
+
+	pm_genpd_syscore_poweroff(&p->pdev->dev);
+	clk_unprepare(p->clk);
 }
 
 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 {
-	pm_genpd_syscore_poweron(&ced_to_sh_cmt(ced)->pdev->dev);
+	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
+
+	clk_prepare(p->clk);
+	pm_genpd_syscore_poweron(&p->pdev->dev);
 }
 
 static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,

@@ -737,6 +743,10 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
 		goto err2;
 	}
 
+	ret = clk_prepare(p->clk);
+	if (ret < 0)
+		goto err3;
+
 	if (res2 && (resource_size(res2) == 4)) {
 		/* assume both CMSTR and CMCSR to be 32-bit */
 		p->read_control = sh_cmt_read32;

@@ -773,19 +783,21 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
 			      cfg->clocksource_rating);
 	if (ret) {
 		dev_err(&p->pdev->dev, "registration failed\n");
-		goto err3;
+		goto err4;
 	}
 	p->cs_enabled = false;
 
 	ret = setup_irq(irq, &p->irqaction);
 	if (ret) {
 		dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
-		goto err3;
+		goto err4;
 	}
 
 	platform_set_drvdata(pdev, p);
 
 	return 0;
+err4:
+	clk_unprepare(p->clk);
 err3:
 	clk_put(p->clk);
 err2:

1.7.9.5

Pulled into tip:timers/core, thanks Daniel!

Note that there was a conflict in drivers/clocksource/clksrc-of.c, caused by interaction with this commit:

4c4b053235fa clocksource: clksrc-of: Do not drop unheld reference on device node

I've resolved it, but please double check the end result once I've pushed it all out.

Thanks,

Ingo

On 01/12/2014 05:33 PM, Ingo Molnar wrote:

[ ... ]

Done. The resolution is ok.

Thanks !
-- Daniel

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