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board/t1040qds: Relax IFC FPGA timings

PATCH New Prabhakar Kushwaha 2 participants 2 messages Dec 12, 2013 – Jan 2, 2014

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Prabhakar Kushwaha

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PATCH 1/1 board/t1040qds: Relax IFC FPGA timings

Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion) is 0 i.e. 0 ns hold time on writes. This may not work on higher clock freqencies.

So, Increase TCH as 0x8 i.e. 8 ip_clk.

Signed-off-by Prabhakar Kushwaha <[email protected]>
---
 include/configs/T1040QDS.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
include/configs/T1040QDS.h +1 -1
index 74f4bde..521a0dc 100644
@@ -247,7 +247,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH 1/1 board/t1040qds: Relax IFC FPGA timings

Quoted 8 lines · Prabhakar Kushwaha

Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion) is 0 i.e. 0 ns hold time on writes. This may not work on higher clock freqencies.

So, Increase TCH as 0x8 i.e. 8 ip_clk.

Signed-off-by Prabhakar Kushwaha <[email protected]>

---

Applied to u-boot-mpc85xx/master. Thanks.

York