i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
PATCH 1/1 i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
For low freq boot mode(ARM boot up with 396MHz), ROM will not set AHB clock to 132MHz, and the reset value of AHB divider is incorrect which will lead to wrong AHB rate, need to correct it. To enable low freq boot mode, need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL SabreSD board and i.MX6SL EVK board.
--- arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/arm/cpu/armv7/mx6/soc.c +20 -0
@@ -131,10 +131,30 @@ static void imx_set_wdog_powerdown(bool enable)writew (enable, &wdog2->wmcr); } +static void set_ahb_rate (u32 val) +{ +struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR ; +u32 reg, div; + + div =get_periph_clk () / val -1 ; + reg =readl (&mxc_ccm->cbcdr); + +writel ((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK )) | + (div <<MXC_CCM_CBCDR_AHB_PODF_OFFSET ), &mxc_ccm->cbcdr); +} +int arch_cpu_init (void ) {init_aips (); +/* +* When low freq boot is enabled, ROM will not set AHB +* freq, so we need to ensure AHB freq is 132MHz in such +* scenario. +*/ +if (mxc_get_clock (MXC_ARM_CLK ) ==396000000 ) +set_ahb_rate (132000000 ); +set_vddsoc (1200 );/* Set VDDSOC to 1.2V */ imx_set_wdog_powerdown (false);/* Disable PDE bit of WMCR register */
Signature · 1 line
1.7.9.5
PATCH 1/1 i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
Hi Anson,
arch/arm/cpu/armv7/mx6/soc.c static void imx_set_wdog_powerdown(bool enable) · line 158
Quoted 13 lines · Anson Huang
int
arch_cpu_init(void){ init_aips();arch/arm/cpu/armv7/mx6/soc.c +8
-0+/* +* When low freq boot is enabled, ROM will not set AHB +* freq, so we need to ensure AHB freq is 132MHz in such +* scenario. +*/ +if (mxc_get_clock (MXC_ARM_CLK ) ==396000000 ) +set_ahb_rate (132000000 ); +set_vddsoc (1200 );/* Set VDDSOC to 1.2V */
Your patch looks good, but please rebase it against the latest u-boot-imx tree because I sent a recent patch that sets vddsoc to 1.175V.
After doing so, you can add:
Regards,
Fabio Estevam
PATCH 1/1 i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
In reply to Anson HuangQuoted 8 lines
-----Original Message-----
From: Anson Huang [mailto:b20788 at freescale.com]
Sent: Tuesday, January 07, 2014 5:32 AM
To: sbabic at denx.de; eric.nelson at boundarydevices.com; troy.kisky at boundarydevices.com; Estevam Fabio-R49496; Liu Hui-R64343
Cc: u-boot at lists.denx.de
Subject: [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
Quoted 7 lines
For low freq boot mode(ARM boot up with 396MHz), ROM will not set AHB clock to 132MHz, and the reset value of AHB divider is incorrect which will lead to wrong AHB rate, need to correct it. To enable low freq boot mode, need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL SabreSD board and i.MX6SL EVK board.
Signed-off-by Anson Huang <[email protected]>
Looks good to me.
Quoted 42 lines
--- arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)arch/arm/cpu/armv7/mx6/soc.c +19
-0@@ -131,10 +131,30 @@ static void imx_set_wdog_powerdown(bool enable)writew (enable, &wdog2->wmcr); } +static void set_ahb_rate (u32 val) +{ +struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR ; +u32 reg, div; + + div =get_periph_clk () / val -1 ; + reg =readl (&mxc_ccm->cbcdr); + +writel ((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK )) | + (div <<MXC_CCM_CBCDR_AHB_PODF_OFFSET ), &mxc_ccm->cbcdr); } +int arch_cpu_init (void ) {init_aips (); +/* +* When low freq boot is enabled, ROM will not set AHB +* freq, so we need to ensure AHB freq is 132MHz in such +* scenario. +*/ +if (mxc_get_clock (MXC_ARM_CLK ) ==396000000 ) +set_ahb_rate (132000000 ); +set_vddsoc (1200 );/* Set VDDSOC to 1.2V */ imx_set_wdog_powerdown (false);/* Disable PDE bit of WMCR register */
--
1.7.9.5
PATCH 1/1 i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
In reply to Anson HuangHi Anson,
Quoted 34 lines · Anson Huang
For low freq boot mode(ARM boot up with 396MHz), ROM will not set AHB clock to 132MHz, and the reset value of AHB divider is incorrect which will lead to wrong AHB rate, need to correct it. To enable low freq boot mode, need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL SabreSD board and i.MX6SL EVK board.
Signed-off-by Anson Huang <[email protected]>--- arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)arch/arm/cpu/armv7/mx6/soc.c +12
-0@@ -131,10 +131,30 @@ static void imx_set_wdog_powerdown(bool enable)writew (enable, &wdog2->wmcr); } +static void set_ahb_rate (u32 val) +{ +struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR ; +u32 reg, div; + + div =get_periph_clk () / val -1 ; + reg =readl (&mxc_ccm->cbcdr); + +writel ((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK )) | + (div <<MXC_CCM_CBCDR_AHB_PODF_OFFSET ), &mxc_ccm->cbcdr); +} +int arch_cpu_init (void ) {
arch/arm/cpu/armv7/mx6/soc.c static void imx_set_wdog_powerdown(bool enable) · line 157
Quoted 10 lines
arch/arm/cpu/armv7/mx6/soc.c +8
-0init_aips (); +/* +* When low freq boot is enabled, ROM will not set AHB +* freq, so we need to ensure AHB freq is 132MHz in such +* scenario. +*/ +if (mxc_get_clock (MXC_ARM_CLK ) ==396000000 ) +set_ahb_rate (132000000 ); +
Are we sure that mxc_get_clock() returns *exactly* 396000000 ?
As far as I see, this depends firstly from MXC_HCLK, that can be configurable with CONFIG_SYS_MX6_HCLK and could have a different value from the default 24000000. I do not know if there is cases where CONFIG_SYS_MX6_HCLK is useful, no boards at the moment are setting it.
But the test requires that the computed frequency is exactly 396Mhz. Is this reliable or should we simply test if frequency is lower of a defined threshold ?
Best regards,
Stefano Babic
Signature · 5 lines
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