ARM: sun7i: irqchip: Irqchip driver for NMI
v2 cover ARM: sun7i: irqchip: Irqchip driver for NMI
Allwinner A20 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.
Changes since v1:
- added binding document
Carlo Caione (3):
ARM: sun7i: irqchip: Add irqchip driver for NMI controller
ARM: sun7i: dts: Add NMI irqchip support
ARM: sun7i: irqchip: Update the documentation
.../allwinner,sun7i-sc-nmi.txt | 25 +++ arch/arm/boot/dts/sun7i-a20.dtsi | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sun7i-nmi.c | 191 +++++++++++++++++++++ 4 files changed, 226 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt create mode 100644 drivers/irqchip/irq-sun7i-nmi.c
Signature · 1 line
1.8.5.2
PATCH v2 1/3 ARM: sun7i: irqchip: Add irqchip driver for NMI controller
Allwinner A20 SoCs have special registers to control / (un)mask / acknowledge NMI. This NMI controller is separated and independent from GIC. This patch adds a new irqchip to manage NMI.
--- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sun7i-nmi.c | 191 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 192 insertions(+) create mode 100644 drivers/irqchip/irq-sun7i-nmi.c
drivers/irqchip/Makefile +1 -0
@@ -11,6 +11,7 @@ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o +obj-$(CONFIG_ARCH_SUNXI) += irq-sun7i-nmi.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
drivers/irqchip/irq-sun7i-nmi.c new file +191 -0
191 lines not on this page · raw message
Signature · 1 line
1.8.5.2
PATCH v2 2/3 ARM: sun7i: dts: Add NMI irqchip support
In reply to Carlo CaioneThis patch adds DTS entry for NMI controller as child of GIC.
--- arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/boot/dts/sun7i-a20.dtsi +9 -0
@@ -310,6 +310,15 @@ #size-cells = <1>; ranges; + nmi_intc: sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 1>; + }; + emac: ethernet at 01c0b000 { compatible = "allwinner,sun4i-emac"; reg = <0x01c0b000 0x1000>;
Signature · 1 line
1.8.5.2
PATCH v2 3/3 ARM: sun7i: irqchip: Update the documentation
In reply to Carlo CaioneAdded documentation for NMI irqchip.
--- .../allwinner,sun7i-sc-nmi.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +25 -0
@@ -0,0 +1,25 @@ +Allwinner Sunxi NMI Controller +============================== + +Required properties: + +- compatible : should be "allwinner,sun7i-sc-nmi" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2. +- interrupt-parent: Specifies the parent interrupt controller. +- interrupts: Specifies the list of interrupt lines which are handled by + the interrupt controller in the parent controller's notation. This value + shall be the NMI. + +Example: + +sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 1>; +};
Signature · 1 line
1.8.5.2
PATCH v2 3/3 ARM: sun7i: irqchip: Update the documentation
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 10
Quoted 10 lines · Carlo Caione
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +10
-0+Allwinner Sunxi NMI Controller +============================== + +Required properties: + +- compatible : should be "allwinner,sun7i-sc-nmi" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2.
I think you should list what the two cells are so users know what to put in the irq specifier.
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 25
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +8
-0+sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 1>; +};
Is <0 0 1> the correct representation of the NMI? This question has recently come up on IRC and I didn't know the answer at the time.
Arnd
PATCH v2 3/3 ARM: sun7i: irqchip: Update the documentation
Quoted 14 lines · Arnd Bergmann
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 10
Quoted 10 lines · Carlo Caione
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +10
-0+Allwinner Sunxi NMI Controller +============================== + +Required properties: + +- compatible : should be "allwinner,sun7i-sc-nmi" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2.I think you should list what the two cells are so users know what to put in the irq specifier.
Agree, I'll fix in v3
Quoted 11 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 25
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +8
-0+sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 1>; +};Is <0 0 1> the correct representation of the NMI? This question has recently come up on IRC and I didn't know the answer at the time.
Why shouldn't it be a correct representation? I think I missed the discussion on IRC.
Actually I already have a MFD driver using this irqchip without any problems.
Thanks,
--
Carlo Caione
PATCH v2 3/3 ARM: sun7i: irqchip: Update the documentation
Hi,
Quoted 30 lines · Carlo Caione
Quoted 14 lines · Arnd Bergmann
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 10
Quoted 10 lines · Carlo Caione
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +10
-0+Allwinner Sunxi NMI Controller +============================== + +Required properties: + +- compatible : should be "allwinner,sun7i-sc-nmi" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2.I think you should list what the two cells are so users know what to put in the irq specifier.
Agree, I'll fix in v3
Quoted 11 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 25
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +8
-0+sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 1>; +};Is <0 0 1> the correct representation of the NMI? This question has recently come up on IRC and I didn't know the answer at the time.
Quoted 2 lines
Why shouldn't it be a correct representation? I think I missed the discussion on IRC.
I did not see the discussion on irc either, but this almost certainly should be <0 0 4>, as all interrupts on sun7i are level sensitive, not edge sensitive, making it <0 0 1> and thus edge sensitive can cause lost interrupts if an interrupt fires between the handler has reading the interrupt status register, and it writing it to clear the bits it has seen. In this case the interrupt line stays high, but the interrupt handler won't get re-run when configured for level interrupts.
Regards,
Hans
PATCH v2 3/3 ARM: sun7i: irqchip: Update the documentation
Quoted 46 lines · Hans de Goede
Hi,
Quoted 38 lines · Carlo Caione
Quoted 17 lines · Arnd Bergmann
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 10
Quoted 11 lines · Carlo Caione
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +10
-0+Allwinner Sunxi NMI Controller +============================== + +Required properties: + +- compatible : should be "allwinner,sun7i-sc-nmi" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2.I think you should list what the two cells are so users know what to put in the irq specifier.
Agree, I'll fix in v3
Quoted 5 lines
Quoted 5 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +5
-0+sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>;Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 25
Quoted 3 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +3
-0+ interrupt-parent = <&gic>; + interrupts = <0 0 1>; +};Is <0 0 1> the correct representation of the NMI? This question has recently
come up on IRC and I didn't know the answer at the time.Quoted 2 lines
Why shouldn't it be a correct representation? I think I missed the discussion on IRC.
Quoted 7 lines
I did not see the discussion on irc either, but this almost certainly should be <0 0 4>, as all interrupts on sun7i are level sensitive, not edge sensitive, making it <0 0 1> and thus edge sensitive can cause lost interrupts if an interrupt fires between the handler has reading the interrupt status register, and it writing it to clear the bits it has seen. In this case the interrupt line stays high, but the interrupt handler won't get re-run when configured for level interrupts.
Ouch, right! fix coming in v3.
Thanks,
--
Carlo Caione
PATCH v2 3/3 ARM: sun7i: irqchip: Update the documentation
In reply to Carlo CaioneQuoted 12 lines · On Wednesday 08 January 2014 12:49:10 Carlo Caione wrote:
Quoted 11 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 25
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +8
-0+sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 1>; +};Is <0 0 1> the correct representation of the NMI? This question has recently come up on IRC and I didn't know the answer at the time.
Quoted 2 lines
Why shouldn't it be a correct representation? I think I missed the discussion on IRC.
For all I know, the NMI and the IRQ input to the CPU are separate pins, so the NMI irqchip is not actually cascaded to the GIC, and SPI-0 might in fact be a different interrupt source.
Arnd
[linux-sunxi] Re: [PATCH v2 3/3] ARM: sun7i: irqchip: Update the documentation
Quoted 13 lines · Arnd Bergmann
Quoted 12 lines · On Wednesday 08 January 2014 12:49:10 Carlo Caione wrote:
Quoted 11 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt line 25
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-sc-nmi.txt new file +8
-0+sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 1>; +};Is <0 0 1> the correct representation of the NMI? This question has recently come up on IRC and I didn't know the answer at the time.
Quoted 6 lines
Quoted 2 lines
Why shouldn't it be a correct representation? I think I missed the discussion on IRC.
For all I know, the NMI and the IRQ input to the CPU are separate pins, so the NMI irqchip is not actually cascaded to the GIC, and SPI-0 might in fact be a different interrupt source.
In Allwinner A20/A31 SoCs NMI controller is an independent module external and in cascade with the GIC. It catches the NMI pin's state and generates irq to GIC.
(therefore NMI is not really not Non-maskable but it is a normal interrupt). Here is an ascii-plot of the system (thanks to Maxime and the Allwinner engineers for this)
+---------+ +-----------+
| +------------+ FIQ |
| GIC | | |
| +------------+ INT CPU |
+--+---+--+ | |
| | | |
| +------+ | |
| | | |
+-----+ +--+--+ +---+---+ | |
| AXP +-+-+ NMI + | ALARM | | |
+-----+ | +-----+ +---+---+ +-----------+
| |
+---------------+Best,
--
Carlo Caione
[linux-sunxi] Re: [PATCH v2 3/3] ARM: sun7i: irqchip: Update the documentation
Quoted 7 lines · Carlo Caione
In Allwinner A20/A31 SoCs NMI controller is an independent module external and in cascade with the GIC. It catches the NMI pin's state and generates irq to GIC.
(therefore NMI is not really not Non-maskable but it is a normal interrupt). Here is an ascii-plot of the system (thanks to Maxime and the Allwinner engineers for this)
Quoted 13 lines
+---------+ +-----------+
| +------------+ FIQ |
| GIC | | |
| +------------+ INT CPU |
+--+---+--+ | |
| | | |
| +------+ | |
| | | |
+-----+ +--+--+ +---+---+ | |
| AXP +-+-+ NMI + | ALARM | | |
+-----+ | +-----+ +---+---+ +-----------+
| |
+---------------+Ah, cool. That certianly makes sense now. Thanks for the explanation.
Arnd
v2 cover ARM: sun7i: irqchip: Irqchip driver for NMI
In reply to Carlo CaioneQuoted 6 lines · Carlo Caione
Allwinner A20 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.
Changes since v1:
- added binding document
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